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Электронный компонент: MX23J12840TC-50G

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1
P/N:PM1097
REV. 1.2, OCT. 28, 2005
FEATURES
Word organization
- (16,777,216 + 1,048,576
Note
) by 8 bits
Page size
- (512 + 16
Note
) by 8 bits
Block size
- (16,384 + 512
Note
) by 8 bits
Note : Underlined parts are redundancy and fixed to
all FFH.
Operation mode
- READ mode (1), READ mode (2), READ mode (3),
RESET
Operating supply voltage : VCC = 2.7~3.6V
MX23J12840
128M-BIT NAND INTERFACE XtraROM
TM
Access Time
- Memory cell array to starting address : 7 us (MAX.)
- Read cycle time : 50 ns (MAX.)
- RE access time : 35 ns (MAX.)
Operating supply current
- During read : 30 mA (MAX.) (50 ns cycle operation)
- During standby (CMOS) : 40 uA (MAX.)
Package Type
- 48-pin TSOP(I) (12mmx20mm)
XtraROM
TM
: factory pre-programmed ROM with
Macronix NBit
TM
technology, supporting short TAT
Process
- 0.15um
PIN DESCRIPTION
SYMBOL
PIN NAME
I/O0~I/O7
Address Input/Command Inputs/
Data Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
WE
Write Enable
RE
Read Enable
CE
Chip Enable
RB
READY, /BUSY pin
VCC
Supply Voltage
NC
No Connection
GND
Ground
PIN CONFIGURATIONS
48 TSOP
NC
NC
NC
NC
NC
GND
RB
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VCC
GND
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX23J12840
(Normal Type)
ORDER INFORMATION
Part No.
Package
Grade
MX23J12840TC-50G
48 pin TSOP (Pb-free, RoHS)
Commercial
MX23J12840TC-50
48 pin TSOP
Commercial
MX23J12840TI-50G
48 pin TSOP (Pb-free, RoHS)
Industrial
2
P/N:PM1097
REV. 1.2, OCT. 28, 2005
MX23J12840
BLOCK DIAGRAM
Input/Output Buff
er
Command
Register
READ Contorol Circuit
Memory Cell Matrix
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Control Logic
X-Decoder
CE
CLE
ALE
WE
RE
VCC
RB (Open-drain)
Sense Amplifier
Y-Selector
Data Register Circuit
Address
Register
READY/BUSY
Control Circuit
3
P/N:PM1097
REV. 1.2, OCT. 28, 2005
MX23J12840
MEMORY MAP
The start address (SA) during read operation is specified divided into three areas using three types of read
commands.
- In read mode (1), start address (SA) is set in area (A).
- In read mode (2), start address (SA) is set in area (B).
- In read mode (3), start address (SA) is set in area (C).
One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy).
One block consists of 32 pages.
Caution The data of area (C) is redundancy, which is not programmable and is fixed to all FFH.
1 Block
=32 Pages
512 Bytes
(Main memory)
16 Bytes
(Redundancy)
0
.
.
.
255
0
1
2
.
.
30
31
.
.
.
.
.
.
.
.
.
32,765
32,766
32,767
256
1 Page=528 Bytes
.
.
.
511
.
527
1,024 Blocks
=32,768 Pages
(B)
(A)
(C)
4
P/N:PM1097
REV. 1.2, OCT. 28, 2005
MX23J12840
Operation Modes
Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are
controlled by the CLE, ALE, WE, RE, and CE signals.
Operation mode during serial read
Mode
CLE
ALE
CE
WE
RE
I/O0 - I/O7
Data output
L
L
L
H
L
Data output
Output Hi-Z
L
L
L
H
H
Hi-Z
Standby
L
L
H
H
x
Hi-Z
Operation mode
Mode
CLE
ALE
CE
WE
RE
Command input cycle
H
L
L
H
Address input cycle
L
H
L
H
Serial read cycle
L
L
L
H
Remark : VIH or VIL
Command
input cycle
Address input cycle
Serial read cycle
Busy
CLE
CE
WE
RE
I/O0~
I/O7
RB
ALE
5
P/N:PM1097
REV. 1.2, OCT. 28, 2005
MX23J12840
Operation Commands
The following six operation settings are possible by inputting commands from I/O pins.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]
Command
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st address cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd address cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd address cycle
X
A23
A22
A21
A20
A19
A18
A17
(2) When 50H command is set [Read mode (3)]
Command
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st address cycle
X
X
X
X
A3
A2
A1
A0
2nd address cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd address cycle
X
A23
A22
A21
A20
A19
A18
A17
Remarks
1. A0 to A23 are internal addresses.
2. Internal address A8 is set internally with command 00H or 01H.
3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address cycle are VIH
or VIL.
Command
Hex
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Command receivable
during Busy
Read mode(1)
00
L
L
L
L
L
L
L
L
Read mode(2)
01
L
L
L
L
L
L
L
H
Read mode(3)
Note1
50
L
H
L
H
L
L
L
L
Reset
Note2
FF
H
H
H
H
H
H
H
H
Notes:
1. The data output in read mode (3) is all FFH.
2. The only command that can be executed when the device is Busy is the reset command. Do not set any of the other
commands while the device is Busy.