REV. 1.0, MAY 16, 2006

P/N: PM1291

16M-BIT [x 1] CMOS SERIAL eLiteFlash

MEMORY

GENERAL

· Serial Peripheral Interface (SPI) compatible -- Mode 0

and Mode 3

· 16,777,216 x 1 bit structure

· 32 Equal Sectors with 64K byte each

- Any sector can be erased

· Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

· Latch-up protected to 100mA from -1V to Vcc +1V

· Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

· High Performance

- Fast access time: 50MHz serial clock (30pF + 1TTL

Load)

- Fast program time: 3ms/page (typical, 256-byte per

page)

- Fast erase time: 1s/sector (typical, 64K-byte per

sector) and 32s/chip (typical)

- Acceleration mode:

- Program time: 2.4ms/page (typical)

- Erase time: 0.8s/sector (typical) and 25s/chip

(typical)

· Low Power Consumption

- Low active read current: 30mA (max.) at 50MHz

- Low active programming current: 30mA (max.)

- Low active erase current: 38mA (max.)

- Low standby current: 50uA (max.)

- Deep power-down mode 1uA (typical)

· Minimum 10K erase/program cycle for array
· Minimum 100K erase/program cycle for additional 4Kb

SOFTWARE FEATURES

· Input Data Format

- 1-byte Command code

· Auto Erase and Auto Program Algorithm

Automatically erases and verifies data at selected

sector

Automatically programs and verifies data at selected

page by an internal algorithm that automatically times

the program pulse widths (Any page to be programed

should have page in the erased state first)

· Status Register Feature

· Electronic Identification

JEDEC 2-byte Device ID

- RES command, 1-byte Device ID

- REMS command, ADD=00H will output the

manufacturer's ID first and ADD=01H will output device

ID first

· Additional 4Kb sector independent from main memory

for parameter storage to eliminate EEPROM from

system

HARDWARE FEATURES

· SCLK Input

Serial clock input

· SI Input

Serial Data Input

· SO/PO7
- Serial Data Output or Parallel mode Data output/input

· WP#/ACC Pin

Hardware write protection and Program/erase accel-

eration

· HOLD# pin

pause the chip without diselecting the chip (not for

paralled mode, please connect HOLD# pin to VCC dur-

ing parallel mode)

· PO0~PO6

- for parallel mode data output/input

· PACKAGE

- 8-land SON (8x6mm)

FEATURES

Macronix NBit

Memory Family

MX25L1605ZM

P/N: PM1291

REV. 1.0, MAY 16, 2006

MX25L1605ZM

PIN CONFIGURATIONS

SYMBOL

DESCRIPTION

CS#

Chip Select

Serial Data Input

SO/PO7(1) Serial Data Output or Parallel Data

output/input

SCLK

Clock Input

HOLD#(2)

Hold, to pause the serial communication

(HOLD# is not for parallel mode)

WP#/ACC

Write Protection: connect to GND;

12V for program/erase acceleration:

connect to 12V

VCC

+ 3.3V Power Supply

GND

Ground

PO0~PO6

Parallel data output/input (PO0~PO6 can
be connected to NC in serial mode)

No Internal Connection

PIN DESCRIPTION

Note:
HOLD# is recommended to connect to VCC during parallel
mode.

GENERAL DESCRIPTION

The MX25L1605 is a CMOS 16,777,216 bit serial
eLiteFlash

Memory, which is configured as 2,097,152 x

8 internally. The MX25L1605 features a serial peripheral
interface and software protocol allowing operation on a
simple 3- wire bus. The three bus signals are a clock input
(SCLK), a serial data input (SI), and a serial data output
(SO). SPI access to the device is enabled by CS# input.

The MX25L1605 provide sequential read operation on
whole chip. User may start to read from any byte of the
array. While the end of the array is reached, the device will
wrap around to the beginning of the array and continuously
outputs data until CS# goes high.

After program/erase command is issued, auto program/
erase algorithms which program/erase and verify the
specified page locations will be executed. Program com-
mand is executed on a page (256 bytes) basis, and erase
command is executed on both chip and sector (64K bytes)
basis.

To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion and error
flag status of a program or erase operation.

To increase user's factory throughputs, a parallel mode is
provided. The performance of read/program is dramatically
improved than serial mode on programmer machine.

When the device is not in operation and CS# is high, it is
put in standby mode and draws less than 50uA DC current.

The additional 4Kb sector with 100K erase/program endur-
ance cycles is suitable for parameter storage and replaces
the EEPROM on system.

The MX25L1605 utilizes MXIC's proprietary memory cell
which reliably stores memory contents even after 10K
program and erase cycles.

8-LAND SON (8x6mm small outline no-lead)

CS#

WP#

GND

VCC

HOLD#

SCLK

P/N: PM1291

REV. 1.0, MAY 16, 2006

MX25L1605ZM

DATA PROTECTION

The MX25L1605 are designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of
specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down
transition or system noise.

· Power-On Reset and an internal timer (tPUW) can

provide protection against inadvertant changes while
the power supply is outside the operating specification.

Program, Erase and Write Status Register instructions
are checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.

· All instructions that modify data must be preceded by

a Write Enable (WREN) instruction to set the Write
Enable Latch (WEL) bit . This bit is returned to its reset
state by the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Chip Erase (CE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of
the memory to be configured as readonly. This is the
Software Protected Mode (SPM).

The Write Protect (WP#) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status Register
Write Disable (SRWD) bit to be protected. This is the
Hardware Protected Mode (HPM).

In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protec-
tion from inadvertent Write, Program and Erase in-
structions, as all instructions are ignored except one
particular instruction (the Release from Deep
Powerdown instruction).

· To avoid unexpected changes by system power supply

transition, the Power-On Reset and an internal timer
(tPUW) can protect the device.

· Before the Program, Erase, and Write Status Register

execution, instruction length will be checked on follow-
ing the clock pulse number to be multiple of eight base.

· Write Enable (WREN) instruction must set to Write

Enable Latch (WEL) bit before writing other instructions
to modify data. The WEL bit will return to reset state by
following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Chip Erase (CE) instruction completion

· The Software Protected Mode (SPM) use (BP2, BP1,

BP0) bits to allow part of memory to be protected as
read only.

· The Hardware Protected Mode (HPM) use WP# to

protect the (BP2, BP1, BP0) bits and SRWD bit.

· Deep-Power Down Mode also protects the device by

ignoring all instructions except Release from Deep-
Power Down (RDP) instruction and RES instruction.

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