REV. 1.0, SEP. 29, 2004

P/N: PM1040

MX25L6402A

64M-BIT [x 1] CMOS SERIAL eLite Flash

MEMORY

GENERAL

· 67,108,864 x 1 bit structure

· 128 Equal Sectors with 64K byte each

- Any sector can be erased

· Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

· Latch-up protected to 100mA from -1V to Vcc +1V

· Low Vcc write inhibit is equal to or less than 2.2V

PERFORMANCE

High Performance

Fast access time: 25MHz serial clock (50pF + 1TTL

Load)

Fast program time: 2ms/page (typical, 128-byte per

page)

Fast erase time: 2s/sector (typical, 64K-byte per

sector)

- Acceleration mode:

- Program time: 1.6ms/page (typical)

- Erase time: 1.6s/sector (typical)

Low Power Consumption

Low active read current: 24mA (typical) at 25MHz

Low active programming current: 35mA (typical)

Low active erase current: 35mA (typical)

Low standby current: 5uA (typical, CMOS)

Minimum 100 erase/program cycle

SOFTWARE FEATURES

· Input Data Format

1-byte Command code, 3-byte address, 1-byte byte

address

· Auto Erase and Auto Program Algorithm

Automatically erases and verifies data at selected

sector

Automatically programs and verifies data at selected

page by an internal algroithm that automatically times

the program pulse widths (Any page to be programed

should have page in the erased state first)

· Status Register Feature

Provides detection of program and erase operation

completion.

Provides auto erase/ program error report

Provides detection of parallel mode (for production

throughputs increasing)

HARDWARE FEATURES

· SCLK Input

Serial clock input

· SI Input

Serial Data Input

· SO/PO7 Output

Serial Data Output/Parallel mode PO7 output

· ACC Pin

Program/erase acceleration

· RESET# Pin

to reset

· PO0~PO6 Output

- for parallel mode

· PACKAGE

28-pin SOP (330mil)

FEATURES

Macronix NBit

Memory Family

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

PIN CONFIGURATIONS

SYMBOL

DESCRIPTION

CS#

Chip Select

Serial Data Input

SO/PO7

Serial Data Output/Paralled Data Output

SCLK

Clock Input

ACC

12V for program/erase acceleration

VCC

+ 3.3V Power Supply

GND

Ground

DU(1)

Do Not Use(for Test Mode only)

No Internal Connection

PO0~PO6

Parallel data output (PO0~PO6 can

be connected to NC in serial mode)

RESET#

Reset

PIN DESCRIPTION

28-PIN SOP (330 mil)

Note:
1.DU pin is used for in-house testing and can be tied to

VCC, GND or open for normal operation. There is a weak
pull-up resister from VCC to DU pin.

GENERAL DESCRIPTION

The MX25L6402A is a CMOS 67,108,864 bit serial eLite
Flash

Memory, which is configured as 8,388,608 x 8

internally. The MX25L6402A features a serial peripheral
interface and software protocol allowing operation on a
simple 3- wire bus. The three bus signals are a clock input
(SCLK), a serial data input (SI), and a serial data output
(SO). SPI access to the device is enabled by CS# input.

The MX25L6402A provide sequential read operation on
whole chip. User may start to read from any byte of the
array. While the end of the array is reached, the device will
wrap around to the beginning of the array and continuously
outputs data until CS# goes high.

After program/erase command is issued, auto program/
erase algorithms which program/erase and verify the
specified page locations will be executed. Program
command is executed on a page (128 bytes) basis, and

erase command is executed on both chip and sector (64K
bytes) basis.

To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion and error
flag status of a program or erase operation.

To increase user's factory throughputs, a parallel mode is
provided. The performance of read/program is dramatically
improved than serial mode.

When the device is not in operation and CS# is high, it is
put in standby mode and draws less than 5uA DC current.

The MX25L6402A utilizes MXIC's proprietary memory cell
which reliably stores memory contents even after 100
program and erase cycles.

RESET#

PO6

GND

VCC

PO5

PO4

PO3

SO/PO7

CS#

SCLK

ACC

PO2

PO1

PO0

MX25L6402A

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

1-byte command code

Bit7(MSB) Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

3-byte address(0 to 0FFFH)

AD1:

A22

A21

A20

A19

A18

A17

AD2:

A16

A15

A14

A13

A12

A11

A10

AD3:

1-byte byte address(0 to 7FH)

BA:

Note:
1.X is dummy cycle and is necessary
2.AD1 to AD3 are address input data
3.BA is byte address

Note:
A22 to A16=Sector address

COMMAND DEFINITION

Com-

Read

Status

Clear

Read

Sector

Chip

Page

Parallel

mand

Array

Read

Status

Erase

Program

Mode

(byte)

1st

52H

83H

89H

85H

F1H

F4H

F2H

55H

2nd

AD1

3rd

AD2

4th

AD3

5th

6th

7th

8th

9th

Action

n bytes

Output

Clear

Output

Start to

Load

Enter and

read out

status

vendor

erase at

n bytes

stay in

until

byte

code

CS rising

data to

parallel

CS goes

until

rising

edge

buffer

mode

high

CS goes

edge

until

high

CS goes

power

high &

off

start to

program

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

program

/erase

parallel

erase

program

ready/busy

completion

mode

error

Note1

1=in parallel

1=error

1=ready

0=not in parallel mode

0=busy

DEVICE OPERATION

1.Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2.When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS falling edge. In standby mode, SO pin of this LSI should be High-Z.

3.When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS

rising edge.

When this command is sent, the device will continuously send out the status register contents starting at bit7. The clock
to clock out the data is supplied by the master SPI.

Bit 6,5,2,1 = Reserve for future use.
Bit 4 = "1" -----> There is an error occurred in last erase operation.

= "0" -----> There is no error occurred in last erase operation.

Bit 3 = "1" -----> There is an error occurred in last program operation.

= "0" -----> There is no error occurred in last program operation.

Bit 0 ="1" -----> Device is in ready mode.

="0" -----> Device is in busy mode.

COMMAND DESCRIPTION

(1) Read Array

This command is sent with the 4-byte address (command included), and the byte address, followed by four dummy bytes
sent to give the device time to stabilize. The device will then send out data starting at the byte address until CS goes
high. The clock to clock out the data is supplied by the master SPI. The read operation is executed on whole array. If
the end of the array is reached then the device will wrap around to the beginning of the array.

(2) Read Status Register

(3) Clear Status Register
This command only resets erase error bit (bit 4) and program error bit (bit 3) . These two bits are set by on-chip state machine
during program/erase operation, and can only be reset by issuing a clear status register command or by powering down
VCC .

If status register indicates that error occurred in the last program/erase operation, any further program/erase operation will
be prohibited until status register is cleared.

(4) Read ID

This command is sent with an extra dummy byte( 2-byte command). The device will clock out manufacturer code (C2H)
and device code (9CH) when this command is issued. The clock to clock out the data is supplied by the master SPI.

Note 1: The initial value of Bit7 is "1". Bit7 will have "1" to "0" transit only after program/erase operation is completed. Bit7
will shift from "0" to "1" only after issued program/erase/Clear status register command. Please note the Bit7=0 if program/
erase fail.

Note 2: The value of Bit 0 is "1", no matter the result of program/erase is pass or fail.

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

(5) Sector/Chip Erase

This command is sent with the sector address(A22~A16) when operating Sector Erase. The device will start the erase
sequence after CS# goes high without any further input. A sector should be erased in a typical of 2sec. The average current
is less than 26mA. The chip erase operation does not require the sector address input but two extra dummy bytes are
necessary. During this operation, customer can also access Read Status & Read ID operations.

(6) Page Program

This command is sent with the page number(A22~A7), and 128-byte page address(A6~A0), followed by programming data.
The 128-byte page address (A6-A0) must start from 0. One to 128 bytes of data can be loaded into the buffer of the device
until CS# goes high. If the end of the page is reached, then the device will wrap around to the beginning of the page. The
device will program the specified page with buffered data(Until CS# goes high) without any further input. The typical page
program time is 2mS. The average current is less than 26mA.

During this operation, customer can also access Read Status & Read ID operations.

(7) Standby Mode

When CS# is high and there is no operation in progress, the device is put in standby mode. Typical standby current is
less than 5uA.

(8) Parallel Mode (Highly recommended for production throughputs increasing)

The parallel mode provides 8 bit outputs for increasing throughputs of factory production purpose. The parallel mode
requires 55H command code, after writing the parallel mode command and then CS# going high, after that, the eLite Flash

Memory can be available to accept read/program/read status/read ID command as the normal writing command procedure.
The eLite Flash

Memory will be in parallel mode until VCC power-off.

a. Only effective for Read Array, Read Status, Read ID & Page Program write data period. (refer to page 16,18,21,23)
b. For normal write command (by SI), No effect
c.Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.)
d. For parallel mode, the tAA will be change to 50ns.

POWER-ON STATE

After power-up, the device is placed in the standby state with following status:

The status register is reset with following status :

Bit 7 = "1" -----> Refer to page 5 for detail.
Bit 6 = "0" -----> Device is not in parallel mode.
Bit 5,2,1 = Reserve for future use.
Bit 4 = "0" -----> Erase error flag is reset.
Bit 3 = "0" -----> Program error flag is reset.
Bit 0="1" -----> Device is in ready state.

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

ADDRESS SEQUENCE

The address assignment is described as follows :

BA: Byte address Bit sequence:

AD1:First Address Bit sequence:

A22

A21

A20

A19

A18

A17

AD2:Second Address Bit sequence:

A16

A15

A14

A13

A12

A11

A10

AD3:Thrid Address Bit sequence:

DATA SEQUENCE

Output data is serially sent out through SO pin, synchronized with the rising edge of SCLK, whereas input data is serially
read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data is bit
7 (MSB) first, then bit 6, bit 5, ...., and bit 0.(LSB)

RESET OPERATION

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven
low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all output pins, and
ignores all commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command
sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at
VSS + 0.3V, the device draws reset current (ICC4). If RESET# is held at VIL but not within VSS + 0.3V, the reset current
will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the SPI memory.
Refer to the AC Characteristics tables for RESET# parameters.

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

Auto Page Program Flow Chart

START

F2H

AD1

AD2

AD3

83H

Dummy

Read Status Register

Data are written

(Until CS goes high)

Set Page Program

Command.

Set Read Status

To Continue Other

Operation, Do Clear

Status Register

Command First.

Operation Done,

Device stays at Read

Status Register Mode

until CS goes high.

Pgae Program Completed

YES

Bit7 = 0?

Bit3 = 0?

Program

Another

Page

Program Error

YES

Auto Chip Erase Flow Chart

START

F4H

Dummy

Read Status Register

To Continue Other

Operation, Do Clear

Status Register

Command First

Operation Done,

Device stays at Read

Status Register Mode

until CS goes high.

Chip Erase Completed

Bit 7= 0?

Bit 4 = 0?

Erase Error

YES

83H

Dummy

Set Read Status

Set Chip Erase

Command.

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

Auto Sector Erase Flow Chart

START

F1H

AD1

Read Status Register

To Continue Other

Operation, Do Clear

Status Register

Command First.

Operation Done,

Device stays at Read

Status Register Mode

until CS goes high.

Sector Erase Completed

YES

Bit7 = 0?

Bit4 = 0?

Erase

Another Sector ?

Erase Error

YES

83H

Dummy

AD2

Set Read Status

Set Sector Eraes

Command.

Parallel Mode for Read/Program Flow Chart

START

55H

Auto Page Program, Read,

Read ID or Read Status

Power-off

to exit

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

NOTICE:
1.Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended period
may affect reliability.

2.Specifications contained within the following tables are
subject to change.

3.During voltage transitions, all pins may overshoot to 4.6V
or -0.5V for period up to 20ns.

4.All input and output pins may overshoot to VCC+0.5V
while VCC+0.5V is smaller than or equal to 4.6V.

RATING

VALUE

Ambient Operating

C to 70

C for Commercial grade

Temperature

-40

C to 85

C for Industrial grade

Storage Temperature

-55

C to 125

Applied Input Voltage

-0.5V to 4.6V

Applied Output Voltage

-0.5V to 4.6V

VCC to Ground Potential -0.5V to 4.6V

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL SPECIFICATIONS

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

Maximum Negative Overshoot Waveform

-0.5V

20ns

Maximum Positive Overshoot Waveform

4.6V

3.6V

20ns

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

SYMBOL PARAMETER

NOTES

MIN.

TYP

MAX.

UNITS

TEST CONDITIONS

ILI

Input Load

1,3

VCC = VCC Max

Current

VIN = VCC or GND

ILO

Output Leakage

VCC = VCC Max

Current

VIN = VCC or GND

ISB1

VCC Standby

VCC = VCC Max

Current(CMOS)

CS# = VCC

0.2V

ISB2

VCC Standby

VCC = VCC Max

Current(TTL)

CS# = VIH

ICC1

VCC Read

f=25MHz (serial)

f=1.25MHz (parallel)

ICC2

VCC Program

Program in Progress

Current

ICC3

VCC Erase Current

Erase in Progress

ICC4

VCC Reset Current

RESET# = GND

0.3V

VHH

Voltage for ACC

11.5

12.5

VCC=3.0V~3.6V

Program Acceleration

VIL

Input Low Voltage

-0.5

0.3VCC

VIH

Input High Voltage

0.7VCC

VCC+0.5

VOL

Output Low Voltage

0.4

IOL = 500uA, VCC=2/3 x VCC

VOH

Output High Voltage

0.8VCC

IOH = -100uA, VCC=VCC min.

DC CHARACTERISTICS

(Temperature = -40

C to 85

C for Industrial grade, VCC = 2.7V ~ 3.6V)

(Temperature = 0

C to 70

C for Commercial grade, VCC = 2.7V ~ 3.6V)

NOTES:
1. Typical values at VCC = 3.3V, T = 25

C. These currents are valid for all product versions (package and speeds).

2. Typical value is calculated by simulation.

3. For the DU pin only, the maximum input load current is

5uA when DU pin=VIL (there is weak pull-up resistor from VCC

to DU pin.)

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

SYMBOL

PARAMETER

Min.

Typ.

Max.

Units

Condition

fSCLK

Clock Frequency

Serial

MHz

Parallel

1.25

MHz

tCYC

Clock Cycle Time

Serial

Parallel

800

tSKH

Clock High Time

Serial

Parallel

400

tSKL

Clock Low Time

Serial

Parallel

150

Clock Rise Time

Serial

f=25MHz

Parallel

100

f=1.25MHz

Clock Fall Time

Serial

f=25MHz

Parallel

100

f=1.25MHz

tCSA

CS# Lead Clock Time

tCSB

CS# Lag Clock Time

tCSH

CS# High Time

tCSR

CS# Rise Time

tCSF

CS# Fall Time

tCSHR

RESET# High Time to Write Command Valid

500

tRP

RESET# Pulse Width

500

tRST

RESET# Rise Time

100

tRFT

RESET# Fall Time

100

tDS

SI Setup Time

tDH

SI Hold Time

tAA

Access Time

Serial

Parallel

tDOH

SO Hold Time

tDOZ

SO Floating Time

AC CHARACTERISTICS

(Temperature = -40

C to 85

C for Industrial grade, VCC = 2.7V ~ 3.6V)

(Temperature = 0

C to 70

C for Commercial grade, VCC = 2.7V ~ 3.6V)

NOTES:
1. Typical value is calculated by simulation.

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

STANDBY TIMING WAVEFORM

When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next
CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. While CS#=VIH, current=standby current, while
CS#=VIL and commands are issuing, or commands are invalid, current=24mA(typ.) to 29mA(max.).

SCLK

1st byte

Bit 7

Hi-Z

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CS#

RESET# TIMING WAVEFORM

VIH

VCC(3.3V)

tRP: RESET#=Vil hold time from VCC min.

VIL

VIH

VIL

VDD

RESET#

CS#

tRP

(500ns)

tRST

tCSF

tCSR

tRFT

Reset state

tCSHR

(500ns)

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

READ ARRAY TIMING WAVEFORM (Serial)

CS#

SCLK

1st data output byte

2nd data output byte

9th byte (Dumm y)

CS#

SCLK

(N-1)th data output byte

Nth data output byte

CS#

SCLK

1st byte (52h)

2nd byte (AD1)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit2

Bit1

Bit0

Bit3

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

CS#

SCLK

1st data output byte

2nd data output byte

9th byte (Dumm y)

CS#

SCLK

(N-1)th data output byte

Nth data output byte

CS#

SCLK

1st byte (52h)

2nd byte (AD1)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit2

Bit1

Bit0

Bit3

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

READ ARRAY TIMING WAVEFORM (Parallel)

NOTES:
1. 1st Byte='52h'
2. 2nd Byte=Address 1(AD1), A17=BIT 0, A18=BIT1, A19=BIT2, A20=BIT3, A21=BIT4, A22=BIT5.
3. 3rd Byte=Address 2(AD2), A9=BIT0, A10=BIT1,......A16=BIT7.
4. 4th Byte=Address 3(AD3), A7=BIT0, A8=BIT1.
5. 5th Byte=Byte Address(BA), A0=BIT0, A1=BIT1,......A6=BIT6.
6. 6th-9th Bytes for SI ==> Dummy Bytes (Don't care).
7. From Byte 10, SO Would Output Array Data.
8. Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.).
9. To read array in parallel mode requires a parallel mode command (55H) before the read command.
Once in the parallel mode, eLite Flash

Memory will not exit parallel mode until power-off.

CS#

SCLK

9th byte (Dumm y)

CS#

SCLK

CS#

SCLK

1st byte (52h)

2nd byte (AD1)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

Byte 1

SO7,SO6,
...SO0

Byte 2

.............

Byte N

.............

SO7,SO6,
...SO0

CS#

SCLK

9th byte (Dumm y)

CS#

SCLK

CS#

SCLK

1st byte (52h)

2nd byte (AD1)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

Byte 1

SO7,SO6,
...SO0

Byte 2

.............

Byte N

.............

SO7,SO6,
...SO0

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

READ STATUS REGISTER TIMING WAVEFORM (Serial)

NOTES:
1. BIT 7=0 ==> Program/Erase completed
2. BIT 4=1 ==>Erase Error
3. BIT 3=1 ==>Program Error
4. BIT 1,2,5==> Reserve for future use
5. BIT 0=1 ==> Device is in ready state
6. BIT 6=0 ==> Device is not in parallel mode

CS#

SCLK

1st status output byte

2nd status output byte

2nd byte (Dumm y)

CS#

SCLK

(N-1)th status output byte

Nth status output byte

CS#

SCLK

1st byte (83h)

2nd byte (Dumm y)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit2

Bit1

Bit0

Bit3

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

CS#

SCLK

1st status output byte

2nd status output byte

2nd byte (Dumm y)

CS#

SCLK

(N-1)th status output byte

Nth status output byte

CS#

SCLK

1st byte (83h)

2nd byte (Dumm y)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit2

Bit1

Bit0

Bit3

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

READ STATUS REGISTER TIMING WAVEFORM (Parallel)

NOTES:
1. BIT 7=0 ==> Program/Erase completed
2. BIT 6=0 ==> Device is not in parallel mode
2. BIT 4=1 ==>Erase Error
3. BIT 3=1 ==>Program Error
4. BIT 1,2,5 ==> Reserve for future use
5. Bit 0=1 ==> Device is in ready state
6. Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.).
7. To read status register in parallel mode, which requires a parallel mode command (55H) before the read status register

command.
Once in the parallel mode, eLite Flash

Memory will not exit parallel mode until power-off.

CS#

SCLK

2nd byte (Dumm y)

CS#

SCLK

CS#

SCLK

1st byte (83h)

2nd byte (Dumm y)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

SO7,SO6,
...SO0

Byte 1

Byte 2

.............

Byte N

CS#

SCLK

2nd byte (Dumm y)

CS#

SCLK

CS#

SCLK

1st byte (83h)

2nd byte (Dumm y)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

Bit1

Bit0

SO7,SO6,
...SO0

Byte 1

Byte 2

.............

Byte N

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

READ ID TIMING WAVEFORM (Serial)

NOTES:
1. 1st Byte:85h.
2. 2nd Byte:Dummy Byte.
3. 3rd Byte:Output Manufacture Code(C2h).
4. 4th Byte:Output Device Code(9CH).
5. The 2 bytes ID output will be wrap around.

CS#

SCLK

1st byte (85h)

1st ID byte (C2h)

Hi-Z

CS#

SCLK

(N-1) ID byte

N ID byte

Hi-Z

2nd byte (Dummy)

2nd ID byte (9CH)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit3

Bit2

Bit1

Bit0

CS#

SCLK

1st byte (85h)

1st ID byte (C2h)

Hi-Z

CS#

SCLK

(N-1) ID byte

N ID byte

Hi-Z

2nd byte (Dummy)

2nd ID byte (9CH)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit3

Bit2

Bit1

Bit0

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

READ ID TIMING WAVEFORM (Parallel)

NOTES:
1. 1st Byte:85h.
2. 2nd Byte:Dummy Byte.
3. 3rd Byte:Output Manufacture Code(C2h).
4. 4th Byte:Output Device Code(9CH).
5. The 2 bytes ID output will be wrap around.
6. Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.).
7. To read ID in parallel mode, which requires a parallel mode command (55H) before the read ID command. Once in the

parallel mode, eLite Flash

Memory will not exit parallel mode until power-off.

CS#

SCLK

1st byte (85h)

Hi-Z

CS#

SCLK

Hi-Z

2nd byte (Dummy)

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

SO7,SO6,
...SO0

Byte 1

Byte 2

..............

Byte N

CS#

SCLK

1st byte (85h)

Hi-Z

CS#

SCLK

Hi-Z

2nd byte (Dummy)

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

Bit7

Bit6

Bit0

SO7,SO6,
...SO0

Byte 1

Byte 2

..............

Byte N

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

AUTO PAGE PROGRAM TIMING WAVEFORM (Serial)

1st write data byte

2nd write data byte

5th byte (BA)

(N-1)th write data byte

Nth write data byte

CS#

SCLK

1st byte (F2h)

2nd byte (AD1)

Hi-Z

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 3

Bit 2

Bit 1

Bit 0

CS#

SCLK

CS#

SCLK

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

AUTO PAGE PROGRAM TIMING WAVEFORM (Parallel)

NOTES:
1. 1st Byte:F2h.
2. 2nd Byte:Address AD1.
3. 3rd Byte:Address AD2
4. 4th Byte:Address AD3
5. 5th Byte:Address BA.
6. 6th byte:1st write data byte.
7. When the last byte of the page will be written, the Byte Address will be wrap around to the first byte of the Page.
8. The 128-byte page address (A6~A0) must start from 0.
9. Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.).
10. To program in parallel mode, which requires a parallel mode command (55H) before the page program command. Once

in the parallel mode, eLite Flash

Memory will not exit parallel mode until power-off.

CS#

SCLK

1st byte (F2h)

2nd byte (AD1)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

SO7,SO6,
...SO0

CS#

SCLK

5th byte (BA)

Bit1

Bit0

Byte 1

Byte 2

.............

SO7,SO6,
...SO0

CS#

SCLK

Hi-Z

Byte N

.............

SO7,SO6,
...SO0

CS#

SCLK

1st byte (F2h)

2nd byte (AD1)

Bit7

Hi-Z

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit7

Bit6

Bit5

Bit4

SO7,SO6,
...SO0

CS#

SCLK

5th byte (BA)

Bit1

Bit0

Byte 1

Byte 2

.............

SO7,SO6,
...SO0

CS#

SCLK

Hi-Z

Byte N

.............

SO7,SO6,
...SO0

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

ACCELERATED PROGRAM TIMING DIAGRAM

ACC

12V

VHH

or V

VHH

Note: tVHH (VHH Rise and Fall Time) min. 250ns

AUTO SECTOR/CHIP ERASE TIMING WAVEFORM

NOTES:
1. 1st byte:F1h for Sector Erase.
2. 2nd byte:Address AD1 for Sector Erase, Dummy byte for chip erase.
3. 3rd byte:Address AD2 for Sector Erase, Dummy byte for chip erase.

SCLK

1st byte

- F1h for Sector Erase
- F4h for Chip Erase

Hi-Z

Bit 6

Bit 5

Bit 0

Bit 6

Bit 5

Bit 0

Bit 7

Bit 6

Bit 0

Bit 7

2nd byte

- AD1 for sector
- Dummy for chip

3rd byte

CS#

- AD2 for sector
- Dummy for chip

P/N: PM1040

REV. 1.0, SEP. 29, 2004

MX25L6402A

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

TYP. (1)

Max. (2)

UNIT

Comments

Chip Erase Time

160

512

Note (4)

Chip Erase Time (with ACC=12V)

128

410

Note (4)

Sector erase Time

Note (4)

Sector erase Time (with ACC=12V)

1.6

Note (4)

Page Programming Time

Excludes system level overhead(3)

Page Programming Time (with ACC=12V)

1.6

6.4

Chip Programming Time

240

480

Excludes system level overhead(3)

Chip Programming Time (with ACC=12V)

180

360

Note:
1. Typical program and erase time assumes the following conditions: 25

C, 3.0V, and all bits are programmed by checker-

board pattern.

2. Under worst conditions of 70

C and 3.0V. Maximum values are up to including 100 program/erase cycles.

3. System-level overhead is the time required to execute the command sequences for the page program command.
4. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits are

programmed to 00H before erasure)

MIN.

MAX.

Input Voltage with respect to GND on ACC

-1.0V

12.5V

Input Voltage with respect to GND on all power pins, SI, CS#

-1.0V

2 VCCmax

Input Voltage with respect to GND on SO

-1.0V

VCC + 1.0V

Current

-100mA

+100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

LATCH-UP CHARACTERISTICS

MX25L6402A

ACRONIX

NTERNATIONAL

O.,

TD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

ACRONIX

MERICA,

NC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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