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MX26F640J3

64M [x8/x16] SINGLE 3V PAGE MODE eLiteFlash

MEMORY

ADVANCED INFORMATION

FEATURES

· 3.0V to 3.6V operation voltage

· Block Structure

- 64 x 128Kbyte Erase Blocks

· Fast random / page mode access time

- 100/25 ns Read Access Time

· Page Depth: 8-word

· 128-bit Protection Register

- 64-bit Unique Device Identifier

- 64-bit User Programmable OTP Cells

· 32-Byte Write Buffer

- 6 us/byte Effective Programming Time

· Enhanced Data Protection Features Absolute Protec-

tion with VPEN = GND

- Flexible Block Locking

- Block Erase/Program Lockout during Power Transi-

tions

Performance

· Low power dissipation

- typical 15mA active current for page mode read

- 80uA/(max.) standby current

· High Performance

- Block erase time: 2s typ.

- Byte programming time: 210us typ.

- Block programming time: 0.8s typ. (using Write to

Buffer Command)

· Program/Erase Endurance cycles: 100 cycles

Software Feature

· Support Common Flash Interface (CFI)

- eLiteFlash

memory device parameters stored on

the device and provide the host system to access.

Hardware Feature

· A0 pin

- Select low byte address when device is in byte mode.

Not used in word mode.

· STS pin

- Indicates the status of the internal state machine.

· VPEN pin

- For Erase /Program/ Block Lock enable.

· VCCQ Pin

- The output buffer power supply, control the device 's

output voltage.

Packaging

- 56-Lead TSOP

- 64-ball CSP

Technology

- 0.25u Macronix NBit

Flash Technology

Macronix NBit

Memory Family

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MX26F640J3

GENERAL DESCRIPTION

The MXIC's MX26F640J3 series eLiteFlash

memory

use the most advance 2 bits/cell Nbit technology, double
the storage capacity of memory cell. The device provide

the high density eLiteFlash

memory memory solution

with reliable performance and most cost-effective.

The device organized as by 8 bits or by 16 bits of output

bus. The device is packaged in 56-Lead TSOP and 64-
ball CSP. It is designed to be reprogrammed and erased
in system or in standard EPROM programmers.

The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
To eliminate bus contention, the device has separate chip
enable (CE0, CE1, CE2) and output enable (OE) con-
trols. The device augment EPROM functionality with in-

circuit electrical erasure and programming. The device
uses a command register to manage this functionality.

The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.

The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

PIN CONFIGURATION

56 TSOP (14mm x 20mm)

A22

CE1

A21
A20
A19
A18
A17
A16

VCC

A15
A14
A13
A12

CE0

VPEN

RESET

A11
A10

A9
A8

GND

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

NC
WE
OE
STS
Q15
Q7
Q14
Q6
GND
Q13
Q5
Q12
Q4
VCCQ
GND
Q11
Q3
Q10
Q2
VCC
Q9
Q1
Q8
Q0
A0
BYTE
NC
CE2

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

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MX26F640J3

SYMBOL

PIN NAME

Byte Select Address

A1~A22

Address Input

Q0~Q15

Data Inputs/Outputs

CE0, CE1, CE2 Chip Enable Input

Write Enable Input

Output Enable Input

RESET

Reset/Power Down mode

PIN DESCRIPTION

64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch)

Notes:
1. Don't Use (DU) pins refer to pins that should not be connected.

SYMBOL

PIN NAME

STS

STATUS Pin

BYTE

Byte Mode Enable

VPEN

ERASE/PROGRAM/BLOCK Lock

Enable

VCCQ

Output Buffer Power Supply

VCC

Device Power Supply

GND

Device Ground

Pin Not Connected Internally

Don't Use

BYTE

GND

A10

A11

Q10

VPEN

CE0

A12

RESET

Q11

10mm

A13

A14

A15

Q12

VCC

A18

A19

A20

A16

Q15

A22

CE1

A21

13 mm

A17

STS

CE2

VCC

VCCQ

GND

Q13

GND

Q14

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MX26F640J3

Figure 1. Block Architecture

eLiteFlash

memory reads erases and writes in-system via the local CPU. All bus cycles to or from the eLiteFlash

memory conform to standard microprocessor bus cycles.

Table 1. Chip Enable Truth Table

CE2

CE1

CE0

DEVICE

VIL

Enabled

VIL

VIH

Disabled

VIL

VIH

VIL

Disabled

VIL

VIH

Disabled

VIH

VIL

Enabled

VIH

VIL

VIH

Enabled

VIH

VIL

Enabled

VIH

Disabled

NOTE: For Single-chip applications, CE2 and CE1 can
be strapped to GND.

01FFFF

010000

00FFFF

000000

64-Kword Block

.
.
.

1FFFFF

1F0000

64-Kword Block

.
.
.

3FFFFF

3F0000

64-Kword Block

Word Mode (x16)

03FFFF

020000

01FFFF

000000

.
.
.

3FFFFF

3E0000

.
.
.

7FFFFF

A[22-0]: 64Mbit

A[22-1]: 64Mbit

7E0000

128-Kbyte Block

Byte Mode (x8)

64 Mbit

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MX26F640J3

NOTES:
1. See Table 1 on page 7 for valid CE configurations.
2. OE and WE should never be enabled simultaneously.
3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high.
4. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered.
5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for

VPENLK and VPENH voltages.

6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration

algorithms. It is VOH when the WSM is not busy, or in reset/power-down mode.

7. High Z will be VOH with an external pull-up resistor.
8. See Section , "Read Identifier Codes" for read identifier code data.
9. See Section , "Read Query Mode Command" for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=

VPENH and VCC is within specification.

11.Refer to Table 3 on page 10 for valid DIN during a write operation.

Table 2. Bus Operations

Command

Read

Output

Standby RESET Read ID

Read

Write

Sequence

Array

Disable

Mode/

Query

Status

Power

(WSM off) (WSM on)

Down

Mode

Notes

4,5,6

6,10,11

RESET

VIH

VIL

VIH

CE0,CE1,CE2(1) Enabled Enabled Disabled X

Enabled

Enabled Enabled

Enabled

OE (2)

VIL

VIH

VIL

VIH

WE (2)

VIH

VIL

Address

See

Figure 2

Table 6

VPEN

VPENH

Q (3)

Data out High Z

High Z

High Z Note 8

Note 9

Data out

Q7=Data out

Data in

Q15-8=High Z

Q6-0=High Z

STS

High Z

High Z High Z

High Z

(default mode)

(7)

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MX26F640J3

FUNCTION

The device includes on-chip program/erase control cir-
cuitry. The Write State Machine (WSM) controls block
erase and byte/word/page program operations. Opera-
tional modes are selected by the commands written to
the Command User Interface (CUI). The Status Register
indicates the status of the WSM and when the WSM
successfully completes the desired program or block
erase operation.

READ

The device has three read modes, which accesses to
the memory array, the Device Identifier or the Status
Register independent of the VPEN voltage. The appro-
priate read command are required to be written to the
CUI. Upon initial device powerup or after exit from
powerdown, the device automatically resets to read ar-
ray mode. In the read array mode, low level input to CE0,
CE1, CE2 and OE, high level input to WE and RESET
and address signals to the address inputs (A22-A0) out-
put the data of the addressed location to the data input/
output (Q15~Q0).

When reading information in read array mode, the de-
vice defaults to asynchronous page mode. In this state,
data is internally read and stored in a high-speed page
buffer. A2:0 addresses data in the page buffer. The page
size is 4 words or 8 bytes. Asynchronous word/byte mode
is supported with no additional commands required.

WRITE

Writes to the CUI enables reading of memory array data,
device identifiers and reading and clearing of the Status
Register and when VPEN=VPENH block erasure pro-
gram and lock-bit configuration. The CUI is written when
the device is enable, WE is active and OE is at high
level. Address and data are latched on the earlier rising
edge of WE and CE. Standard micro-processor write tim-
ings are used.

OUTPUT DISABLE

When OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.

STANDBY

When CE0, CE1 and CE2 disable the device (see table1)
and place it in standby mode. The power consumption of
this device is reduced. Data input/output are in a high-
impedance(High-Z) state. If the memory is deselected
during block erase, program or lock-bit configuration, the
internal control circuits remain active and the device con-
sume normal active power until the operation completes.

POWER-DOWN

When RESET pin is at VIL the device is in the power-
down mode and its power consumption is substantially
low around 25uA. During read modes, the memory is
deselected and the data input/output are in a high-
impedance(High-Z) state. To return from power down
mode requires RESET pin at VIH. After return from
powerdown, the CUI is reset to Read Array , and the
Status Register is set to value 80H.

During block erase program or lock-bit configuration
modes, RESET pin at VIL will abort either operation.
Memory array data of the block being altered become
invalid.

In default mode, STS transitions low and remains low
for a maximum time of tPLPH+tPHRH until the reset
operation is complete. Memory contents being altered
are no longer valid; the data may be partially corrupted
after a program or partially altered after an erase or lock-
bit configuration. Time tPHWL is required after RESET
goes to logic-high (VIH) before another command can
be written.

READ QUERY

The read query operation outputs block status informa-
tion, CFI (Common Flash Interface) ID string, system
interface information, device geometry information and
MXIC extended query information.

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MX26F640J3

COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the CUI. Table 3 defines the valid
register command sequences.

When VPEN<VPENLK only read operations from the status register, query, indentifier code or blocks are enabled.
When VPEN=VPENH enables block erase program and lock-bit configuration operations.

Table 3. Command Definitions

Command

Read

Clear

Write to

Word/byte Sector

Sequence

Array

Query

Status

Buffer

Program

Erase

Register

Notes

7,8,9

10,11

9,10

Bus Write Cycles Req'd

> 2

First Bus

Operation(2)

Write

Write Cycles Address(3)

Data(4,5)

FFH

90H

98H

70H

50H

E8H

40H/10H

20H

Second Bus Operation(2)

Read

Write

Read Query

Address(3)

Data(4,5)

SRD

D0H

Command

Configur-

Set Sector

Clear

Protection

Sequence

ation

Lock-Bit

Sector

Program

Lock-Bit

Notes

Bus Write Cycles Req'd

First Bus

Operation(2)

Write

Write Cycle

Address(3)

Data(4,5)

B8H

60H

C0H

Second Bus Operation(2)

Write

Write Cycle

Address(3)

Data(4,5)

01H

D0H

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MX26F640J3

NOTES:
1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.

BA = Address within the block.

IA = Identifier Code Address: see Figure 2 and Table 14.

QA = Query database Address.

PA = Address of memory location to be programmed.

RCD = Data to be written to the read configuration register. This data is presented to the device on A 16-1 ; all other

address inputs are ignored.

3. ID = Data read from Identifier Codes.

QD = Data read from Query database.

SRD = Data read from status register. See Table 15 for a description of the status register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

CC = Configuration Code.

4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.

5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock

codes. See Section 4.3 for read identifier code data.

6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.

7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.

8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.

Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =000FH.

The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer.

The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the

sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional

information.

9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.

10.Attempts to issue a block erase or program to a locked block.

11.Either 40H or 10H are recognized by the WSM as the byte/word program setup.

12.The clear block lock-bits operation simultaneously clears all block lock-bits.

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MX26F640J3

Figure 2. Device Identifier Code Memory Map

NOTE: A0 is not used in either x8 or x16 mode when obtaining these identifier codes. Data is always given on the low
byte in x16 mode (upper byte contains 00h).

3FFFFF

3F0003

3F0002

3F0000

3EFFFF

Block 63

Reserved for Future

Implementation

Reserved for Future

Implementation

(Block 32 through 62)

Block 63 Lock Configuration

Word

Address

A[22-1]: 64 Mbit

1F0003

1F0002

1F0000

1EFFFF

01FFFF

Block 31

Reserved for Future

Implementation

Reserved for Future

Implementation

(Block 2 through 30)

Block 31 Lock Configuration

010003
010002

010000

000003

000002

000001

000000

Block 1

Reserved for Future

Implementation

00FFFF

000004

Block 0

Reserved for Future

Implementation

Reserved for Future

Implementation

Block 1 Lock Configuration

Block 0 Lock Configuration

Device Code

Manufacturer Code

64 Mbit

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MX26F640J3

Read Array Command

The device is in Read Array mode on initial device power
up and after exit from power down, or by writing FFH to
the Command User Interface. The read configuration reg-
ister defaults to asynchronous read page mode. The de-
vice remains enabled for reads until another command
is written. The Read Array command functions indepen-
dently of the VPEN voltage.

Read Query Mode Command

This section defines the data structure or "Database"
returned by the Common Flash Interface (CFI) Query
command. System software should parse this structure
to gain critical information such as block size, density,
x8/x16, and electrical specifications. Once this informa-
tion has been obtained, the software will know which

command sets to use to enable eLiteFlash

memory

writes, block erases, and otherwise control the

eLiteFlash

memory component.

Query Structure Output

The Query Database allows system software to gain in-

formation for controlling the eLiteFlash

memory com-

ponent. This section describes the device CFI-compliant
interface that allows the host system to access Query
data.

Query data are always presented on the lowest-order
data outputs (DQ 0-7) only. The numerical offset value is
the address relative to the maximum bus width supported
by the device. On this family of devices, the Query table
device starting address is a 10h, which is a word ad-
dress for x16 devices.

For a word-wide (x16) device, the first two bytes of the
Query structure, "Q" and "R" in ASCII, appear on the
low byte at word addresses 10h and 11h. This CFI-com-
pliant device outputs 00H data on upper bytes. Thus, the
device outputs ASCII "Q" in the low byte (DQ 0-7 ) and
00h in the high byte (DQ 8-15 ).

At Query addresses containing two or more bytes of in-
formation, the least significant data byte is presented at
the lower address, and the most significant data byte is
presented at the higher address.

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MX26F640J3

Word Addressing

Byte Addressing

Offset

Hex Code

Value

Offset

Hex Code

Value

A15-A0 D15 - D0

A7-A0

D7 - D0

0010h

0051

"Q"

20h

"Q"

0011h

0052

"R"

21h

"Q"

0012h

0059

"Y"

22h

"R"

0013h

P_ID

PrVendor

23h

"R"

0014h

P_ID

ID#

24h

"Y"

0015h

PLO

PrVendor

25h

"Y"

0016h

PHI

TblAdr

26h

P_ID

PrVendor

0017h

A_ID

AltVendor

27h

P_ID

ID#

0018h

A_ID

ID#

28h

P_ID

ID#

...

In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been
dropped. In addition, since the upper byte of word-wide devices is always "00h"," the leading "00" has been dropped
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.

NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is

configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is
"Not Applicable" for x8-configured devices.

Device

Query start location in

Query data with maximum

Query data with byte

Type/Mode

maximum device bus

device bus width addressing

addressing

width addresses

Hex

ASCII

Hex

ASCII

Offset

Code

Value

Offset

Code

Value

x16 device

10:

0051

"Q"

20:

"Q"

x16 mode

10h

11:

0052

"R"

21:

"Null"

12:

0059

"Y"

22:

"R"

x16 device

20:

"Q"

x8 mode

N/A (1)

21:

"Q"

22:

"R"

Table 4. Summary of Query Structure Output as a Function of Device and Mode

Table 5. Example of Query Structure Output of a x16- and x8-Capable Device

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MX26F640J3

Offset

Sub-Section

Name Description

00h

Manufacturer Code

01h

Device Code

(BA+2)h (2)

Block Status Register

Block-Specific Information

04-0Fh

Reserved

Reserved for Vendor-Specific Information

10h

CFI Query Identification String

Reserved for Vendor-Specific Information

1Bh

System Interface Information

Command Set ID and Vendor Data Offset

27h

Device Geometry Definition

eLiteFlash

memory Device Layout

P (3)

Primary MXIC-Specific Extended

Vendor-Defined Additional Information Specific to the

Query Table

Primary Vendor Algorithm

NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128

Kbyte).

3. Offset 15 defines "P" which points to the Primary MXIC-Specific Extended Query Table.

Table 6. Query Structure (1)

Block Status Register

The block status register indicates whether an erase operation completed successfully or whether a given block is

locked or can be accessed for eLiteFlash

memory program/erase operations.

Offset

Length

Description

Address

Value

(BA+2)h (1)

Block Lock Status Register

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked

BA+2:

(bit 0): 0 or 1

1 = Locked

BSR 1-7: Reserved for Future Use

BA+2:

(bit 1-7): 0

NOTE:
1. BA = The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word

mode).

Table 7. Block Status Register

Query Structure Overview

The Query command causes the eLiteFlash

memory component to display the Common Flash Interface (CFI)

Query structure or "database". The structure sub-sections and address locations are summarized below.

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MX26F640J3

Offset

Length

Description

Add.

Hex

Value

Code

10h

Query-unique ASCII string "QRY"

--51

"Q"

11:

--52

"R"

12:

--59

"Y"

13h

Primary vendor command set and control interface ID code.

13:

--01

16-bit ID code for vendor-specified algorithms

14:

--00

15h

Extended Query Table primary algorithm address

15:

--31

16:

--00

17h

Alternate vendor command set and control interface ID code.

17:

--00

0000h means no second vendor-specified algorithm exists

18:

--00

19h

Secondary algorithm Extended Query Table address.

19:

--00

0000h means none exists

1A:

--00

Table 8. CFI Identification

Offset Length

Description

Add.

Hex

Value

Code

1Bh

VCC logic supply minimum program/erase voltage

bits 0-3 BCD 100 mV

1B:

--30

3.0V

bits 4-7 BCD volts

1Ch

VCC logic supply maximum program/erase voltage

bits 0-3 BCD 100 mV

1C:

--36

3.6 V

bits 4-7 BCD volts

1Dh

VPP [programming] supply minimum program/erase voltage

bits 0-3 BCD 100 mV

1D:

--00

0.0V

bits 4-7 HEX volts

1Eh

VPP [programming] supply maximum program/erase voltage

bits 0-3 BCD 100 mV

1E:

--00

0.0V

bits 4-7 HEX volts

1Fh

"n" such that typical single word program time-out = 2

1F:

--07

128us

20h

"n" such that typical max. buffer write time-out = 2

20:

--07

128us

21h

"n" such that typical block erase time-out = 2

21:

--0A

22h

"n" such that typical full chip erase time-out = 2

22:

--00

23h

"n" such that maximum word program time-out = 2

times typical 23:

--04

2ms

24h

"n" such that maximum buffer write time-out = 2

times typical

24:

--04

2ms

25h

"n" such that maximum block erase time-out = 2

times typical

25:

--04

16s

26h

"n" such that maximum chip erase time-out = 2

times typical

26:

--00

System Interface Information

The following device information can optimize system interface software.

Table 9. System Interface Information

CFI Query Identification String

The CFI Query Identification String provides verification that the component supports the Common Flash Interface
specification. It also indicates the specification version and supported vendor-specified command set(s).

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MX26F640J3

Address

64M

27:

--17

28:

--02

29:

--00

2A:

--05

2B:

--00

2C:

--01

2D:

--3F

2E:

--00

2F:

--00

30:

--02

Device Geometry Definition

This field provides critical details of the eLiteFlash

memory device geometry.

Offset Length

Description

Code See Table

Below

27h

"n" such that device size = 2

in number of bytes

27:

28h

eLiteFlash

memory device interface: x8 async(28:00,29:00),

28:

--02

x8/x16

x16 async(28:01,29:00), x8/x16 async(28:02,29:00)

29:

--00

2Ah

"n" such that maximum number of bytes in write buffer = 2

2A:

--05

2B:

--00

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in "bulk"

2. x specifies the number of device or partition regions with one or

2Ch

more contiguous same-size erase blocks

2C:

--01

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

2Dh

Erase Block Region 1 Information

2D:

bits 0-15 = y, y+1 = number of identical-size erase blocks

2E:

bits 16-31 = z, region erase block(s) size are z x 256 bytes

2F:

30:

Table 10. Device Geometry Definition

Device Geometry Definition

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Offset(1) Length

Description

Add.

Hex

Value

P=31h

(Optional eLiteFlash

memory Features and Commands)

Code

(P+0)h

Primary extended query table

31:

--50

"P"

(P+1)h

Unique ASCII string "PRI"

32:

--52

"R"

(P+2)h

33:

--49

"I"

(P+3)h

Major version number, ASCII

34:

--31

"1"

(P+4)h

Minor version number, ASCII

35:

--32

"2"

(P+5)h

Optional feature and command support (1=yes, 0=no)

36:

--C8

(P+6)h

bits 9-31 are reserved; undefined bits are "0". If bit 31 is

37:

--00

(P+7)h

"1" then another 31 bit field of optional features follows at

38:

--00

(P+8)h

the end of the bit-30 field.

39:

--00

bit 0 Chip erase supported

bit 0 = 0

bit 1 Reserved

bit 1 = 0

bit 2 Reserved

bit 2 = 0

bit 3 Legacy lock/unlock supported

bit 3 = 1(1)

Yes(1)

bit 4 Queued erase supported

bit 4 = 0

bit 5 Instant Individual block locking supported

bit 5 = 0

bit 6 Protection bits supported

bit 6 = 1

Yes

bit 7 Page-mode read supported

bit 7 = 1

Yes

bit 8 Synchronous read supported

bit 8 = 0

(P+9)h

Reserved

3A:

--00

(P+A)h

Block status register mask

3B:

--01

(P+B)h

bits 2-15 are Reserved; undefined bits are "0"

3C:

--00

bit 0 Block Lock-Bit Status register active

bit 0 = 1

Yes

bit 1 Block Lock-Down Bit Status active

bit 1 = 0

(P+C)h

VCC logic supply highest performance program/erase voltage

bits 0-3 BCD value in 100 mV

3D:

--33

3.3V

bits 4-7 BCD value in volts

(P+D)h

VPP optimum program/erase supply voltage

bits 0-3 BCD value in 100 mV

3E:

--00

0.0V

bits 4-7 HEX value in volts

Primary-Vendor Specific Extended Query Table

Certain eLiteFlash

memory features and commands are optional. The Primary Vendor-Specific Extended Query

table specifies this and other similar information.

NOTE:
1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0".

Table 11. Primary Vendor-Specific Extended Query

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MX26F640J3

Offset(1) Length

Description

Add.

Hex

Value

P=31h

(Optional eLiteFlash

memory Features and Commands)

Code

(P+E)h

Number of Protection register fields in JEDEC ID space.

3F:

--01

"00h," indicates that 256 protection bytes are available

Protection Field 1: Protection Description

This field describes user-available One Time Programmable

(OTP) protection register bytes. Some are pre-programmed

(P+F)h

with device-unique serial numbers. Others are user-programmable.

(P+10)h

Bits 0-15 point to the protection register lock

40:

--00

00h

(P+11)h

byte, the section's first byte. The following bytes are factory

(P+12)h

pre-programmed and user-programmable.

bits 0-7 = Lock/bytes JEDEC-plane physical low address

bits 8-15 = Lock/bytes JEDEC-plane physical high address

bits 16-23 = "n" such that 2

= factory pre-programmed bytes

bits 24-31 = "n" such that 2

= user-programmable bytes

NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.

Table 12. Protection Register Information

Offset(1) Length Description

Add.

Hex

Value

P=31h

(Optional eLiteFlash

memory Features and Commands)

Code

Page Mode Read capability

bits 0-7 = "n" such that 2

HEX value represents the number

(P+13)h

of read-page bytes. See offset 28h for device word width to

44:

--04

16 byte

determine page-mode data output width. 00h indicates no

read page buffer.

(P+14)h

Number of synchronous mode read configuration fields that

45:

--00

follow. 00h indicates no burst capability.

(P+15)h

Reserved for future use

46:

NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.

Table 13. Page Read Information

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MX26F640J3

Notes:
1. The lowest order address line is A0.
2. X selects the specific blocks lock configuration code.

DEVICE OPERATION

SILICON ID READ

The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manu-
facturer and type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.

To activate this mode, the two cycle "Silicon ID Read"
command is requested. (The command sequence is il-
lustrated in Table 14.

During the "Silicon ID Read" Mode, manufacturer's code
(MXIC=C2H) can be read out by setting A0=VIL and
device identifier can be read out by setting A0=VIH.

To terminate the operation, it is necessary to write the
read command. The "Silicon ID Read" command func-
tions independently of the VPEN voltage. This command
is valid only when the WSM is off.

Table 14. MX26F640J3 Silicon ID Codes and Verify Sector Protect Code

Type

Address (1)

Code (HEX)

Manufacture Code

00000

C2H

Device Code

00001

(00) AEH

Block Lock Configuration

X0002 (2)

- Block is Unlocked

DQ0=0

- Block is Locked

DQ0=1

- Reserved for Future Use

DQ1-7

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MX26F640J3

High Z

Definition

Symbol When

Status

Notes

Busy?

"1"

"0"

SR.7

WRITE STATE MACHINE STATUS

Ready

Busy

SR.6

Yes

RESERVED

SR.5

Yes

ERASE AND CLEAR LOCK-BITS

Error in Block Erasure or

Successful Block

STATUS

Clear Lock-Bits

Erase or Clear

Lock-Bits

SR.4

Yes

PROGRAM AND SET LOCK-BIT

Error in Setting Lock-Bit

Successful Set Block

STATUS

Lock Bit

SR.3

Yes

PROGRAMMING VOLTAGE

Low Programming Voltage Programming Voltage

STATUS

Detected, Operation

Aborted

SR.2

Yes

RESERVED

SR.1

Yes

DEVICE PROTECT STATUS

Block Lock-Bit Detected,

Unlock

Operation Abort

SR.0

Yes

RESERVED

Table 15. Status Register Definitions

Notes
1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not

driven while SR.7 = 0

2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se-

quence was entered.

3. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the

programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits com-
mand sequences.

4. SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits

only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depend-
ing on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read
Identifier Codes command to determine block lock-bit status.

5. SR.0 is reserved for future use and should be masked when polling the status register.

High Z

Definition

Symbol When

Status

Notes

Busy?

"1"

"0"

XSR.7

WRITE BUFFER STATUS

Write buffer available

Write buffer not available

XSR.6-

Yes

RESERVED

XSR.0

Table 16 . Extended Status Register Definitions

Notes:
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available.
2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register.

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MX26F640J3

BLOCK ERASE COMMAND

Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm com-
mand of D0H. An address within the block to be erased
is required (erase changes all block data to FFH).

Block preconditioning, erase, and verify are handled in-
ternally by the WSM (invisible to the system). The CPU
can detect block erase completion by analyzing the out-
put of the STS pin or status register bit SR.7. Toggle OE,
CE0 , CE1 , or CE2 to update the status register. The
CUI remains in read status register mode until a new
command is issued. Also, reliable block erasure can only
occur when VCC is valid and VPEN = VPENH.

WRITE TO BUFFER COMMAND

To program the device, a Write to Buffer command is
issue first. A variable number of bytes, up to the buffer
size, can be loaded into the buffer and written to the

eLiteFlash

memory device. First, the Write to Buffer

Setup command is issued along with the Block Address
(see Figure 4 ,"Write to Buffer Flowchart" on page26).
After the command is issued, the extended Status Reg-
ister (XSR) can be read when CE is VIL. XSR.7 indi-
cates if the Write Buffer is available.

If the buffer is available, the number of words/bytes to
be program is written to the device. Next, the start ad-
dress is given along with the write buffer data. Subse-
quent writes provide additional device addresses and
data, depending on the count. After the last buffer data
is given, a Write Confirm command must be issued. The

WSM beginning copy the buffer data to the eLiteFlash

memory array.

If an error occurs while writing, the device will stop writ-
ing, and status register bit SR.4 will be set to a "1" to
indicate a program failure. The internal WSM verify only
detects errors for "1" that do not successfully program
to "0" . If a program error is detected, the status register
should be cleared. Any time SR.4 and/or SR.5 is set, the
device will not accept any more Write to Buffer com-
mands. Reliable buffered writes can only occur when VCC
is valid and VPEN = VPENH. Also, successful program-
ming requires that the corresponding block lock-bit be
reset.

BYTE/WORD PROGRAM COMMANDS

Byte/Word program is executed by a two-command se-
quence. The Byte/Word Program Setup command of 40H
is written to the Command Interface, followed by a sec-
ond write specifying the address and data to be written.
The WSM controls the program pulse application and
verify operation. The CPU can detect the completion of
the program event by analyzing the STS pin or status
register bit SR.7.

If a byte/word program is attempted while VPEN_V
PENLK, status register bits SR.4 and SR.3 will be set to
"1". Successful byte/word programs require that the cor-
responding block lock-bit be cleared. If a byte/ word pro-
gram is attempted when the corresponding block lock-
bit is set, SR.1 and SR.4 will be set to "1".

READ STATUS REGISTER COMMAND

The Status Register is read after writing the Read Status
Register command of 70H to the Command User Inter-
face. Also, after starting the internal operation the de-
vice is set to the Read Status Register mode automati-
cally.

The contents of Status Register are latched on the later
falling edge of OE or the first edge of CE0, CE1, CE2
that enables the device OE must be toggle to VIH or the
device must be disable before further reads to update
the status register latch. The Read Status Register com-
mand functions independently of the VPEN voltage.

CLEAR STATUS REGISTER COMMAND

The Erase Status, Program Status, Block Status bits
and protect status are set to "1" by the Write State Ma-
chine and can only be reset by the Clear Status Register
command of 50H. These bits indicates various failure
conditions.

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MX26F640J3

Read Configuration

The device will support both asynchronous page mode and standard word/byte reads. No configuration is required.
Status register and identifier only support standard word/byte single read operations.

Table 17. Read Configuration Register Definition

16(A16)

Notes

RCR.16 = READ MODE (RM)

Read mode configuration effects reads from the

0 = Standard Word/Byte Reads Enabled (Default)

eLiteFlash

memory array.

1 = Page-Mode Reads Enabled

Status register, query, and identifier reads support

standard word/byte read cycles.

RCR.15-1= RESERVED FOR FUTURE

These bits are reserved for future use. Set these

ENHANCEMENTS (R)

bits to "0".

Configuration Command

The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has
been configured, it remains in that configuration until another configuration command is issued or RP is asserted low.
Initially, the STS pin defaults to RY/BY operation where RY/BY low indicates that the state machine is busy. RY/BY
high indicates that the state machine is ready for a new operation. Table 19, "Configuration Coding Definitions" on
page 28 displays the possible STS configurations.

To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired
configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described
below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete
interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the
default RY/BY level mode. The possible configurations and their usage are described in Table 19, "Configuration
Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy. Check
SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set
to "1". When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.

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MX26F640J3

Q7 - Q2 = Reserved
Q1 - Q0 = STS Pin Configuration Codes
00 = default, level mode RY/BY
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high when
the operation indicated by the given configuration is
completed.
Configuration Command Sequences for STS pin
configuration (masking bits Q7- Q 2 to 00h) are as
follows:
Default RY/BY level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete

Table 18. Configuration Coding Definitions

NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse
width of 250 ns.

Reserved

Pulse on

Program

Erase

Complete (1)

Compete (1)

bits7-2

bit 1

bit 0

Q7 - Q2 are reserved for future use.
default (Q1-Q 0 = 00) RY/BY, level mode
- used to control HOLD to a memory controller to

prevent accessing a eLiteFlash

memory subsystem

while any eLiteFlash

memory device's WSM is busy.

configuration 01 ER INT, pulse mode
- used to generate a system interrupt pulse when any

eLiteFlash

memory device in an array has completed

a Block Erase.
Helpful for reformatting blocks after file system free
space reclamation or "cleanup"
configuration 10 PR INT, pulse mode
-used to generate a system interrupt pulse when any

eLiteFlash

memory device in an array has complete

a Program operation. Provides highest performance for
servicing continuous buffer write operations.
configuration 11 ER/PR INT, pulse mode
-used to generate system interrupts to trigger servic-

ing of eLiteFlash

memory arrays when either erase

or program operations are completed when a common
interrupt service routine is desired.

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MX26F640J3

Set Block Lock-Bit Commands

This device provided the block lock-bits, to lock and
unlock the individual block. To set the block lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while the WSM is running. Writ-
ing the set block lock-bit command of 60H followed by
confirm command and an appropriate block address.
After the command is written, the device automatically
outputs status register data when read. The CPU can
detect the completion of the set lock-bit event by ana-
lyzing the STS pin output or status register bit SR.7.
Also, reliable operations occur only when VCC and VPEN
are valid. With VPEN _VPENLK , lock-bit contents are
protected against alteration.

Clear Block Lock-Bits Command

All set block lock-bits can clear by the Clear Block Lock-
Bits command. This command is invalid while the WSM
is running. To Clear the block lock-bits, two cycle com-
mand is requested . The device automatically outputs
status register data when read. The CPU can detect
completion of the clear block lock-bits event by analyz-
ing the STS pin output or status register bit SR.7. If a
clear block lock-bits operation is aborted due to V PEN
or V CC transiting out of valid range, block lock-bit values
are left in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit contents to
known values.

Protection Register Program Command

The device offer a 128-bit protection register to increase
the security of a system design. The 128-bits protection
register are divided into two 64-bit segments. One is pro-
grammed in the factory with a unique 64-bit number,
which is unchangeable. The other one is left blank for
customer designers to program as desired. Once the
customer segment is programmed, it can be locked to
prevent reprogramming.

Reading the Protection Register

The protection register is read in the identification read
mode. The device is switched to this mode by writing the
Read Identifier command 90H. Once in this mode, read
cycles from addresses retrieve the specified informa-

tion. To return to read array mode, write the Read Array
command (FFH).

Programming the Protection Register

The protection register bits are programmed using the
two-cycle Protection Program command. The 64-bit num-
ber is programmed 16 bits at a time for word-wide parts
and eight bits at a time for byte-wide parts. First write
the Protection Program Setup command, C0H. The next
write to the device will latch in address and data and
program the specified location.

Any attempt to address Protection Program commands
outside the defined protection register address space will
result in a status register error. Attempting to program a
locked protection register segment will result in a status
register error.

Locking the Protection Register

The user-programmable segment of the protection regis-
ter is lockable by programming Bit 1 of the PR-LOCK
location to 0. Bit 0 of this location is programmed to 0 at
the MXIC factory to protect the unique device number.
Bit 1 is set using the Protection Program command to
program "FFFD" to the PR-LOCK location. After these
bits have been programmed, no further changes can be
made to the values stored in the protection register. Pro-
tection Program commands to a locked section will re-
sult in a status register error. Protection register lockout
state is not reversible.

VCC TRANSITIONS

Block erase, program, and lock-bit configuration are not
guaranteed if VCC falls outside of the specified operat-
ing ranges.

The CUI latches commands issued by system software
and is not altered by CE transitions, or WSM actions. Its
state is read array mode upon power-up, after exit from
power-down mode, or after VCC transitions below VLKO.

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Table 20. Word-Wide Protection Register Addressing

Word

Use

LOCK

Both

Factory

User

NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,

i.e., A22-A9 = 0.

Table 21. Byte-Wide Protection Register Addressing

Word

Use

LOCK

Both

LOCK

Both

Factory

User

NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,

i.e., A22-A9 = 0.

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Figure 4. Write to Buffer Flowchart

Start

End

Command Cycle
- Issue Write-to-Buffer Command
- Address=Any address in block
- Data=0xE8

Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7

Write Word Count
- Address=Any address in block
- Data=word count
- Valid range=0x0 thru 0x1F

Write Buffer Data
- Fill write buffer up to word count
- Address=Address(es) within buffer range
- Data=Data to be written

YES

Confirm Cycle
- Issue Confirm Command
- Address=Any address in block
- Data=0xD0

Read Status Register
See Status Register Flowchart

D7=1?

Write to Buffer

Time-Out ?

Any Errors?

Error-Handler
User-defined routine

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Figure 6. Byte/Word Programming Flowchart

Bus

Command

Comments

Operation
Write

Setup Byte/

Data=40H

Word Program Addr=Location to Be

Programmed

Write

Byte/Word

Data=Data to Be

Program

Programmed
Addr=Location to Be
Programmed

Read

Status Register Data

(Note 1)
Standby

Check SR.7

1=WSM Ready
0=WSM Busy

1. Toggling OE (low to high to low) updates the status
register. This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
SR full status check can be done after each program
operation, or after a sequence of programming opera-
tions.
Write FFH after the last program operation to place
device in read array mode.

Bus

Command

Comments

Operation

Standby

Check SR.3

1=Programming to Voltage

Error Detect

Standby

Check SR.1

1=Device Protect Detect

RP=VIH, Block Lock-Bit is

Set Only required for

systems

Standby

Check SR.4

1=Programming Error

Toggling OE (low to high to low) updates the status

Status Register command. Repeat for subsequent pro-

gramming operations.

SR.4, SR.3, and SR.1 are only cleared by the Clear

Status Register Command in cases where multiple lo-

cation are programmed before full status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

Start

Write 40H,

Address

Write Data

and Address

Full Status Check if Desired

Byte/Word Program Complete

Read

Status Register

SR.7=

Read Status Register

Data (See Above)

FULL STATUS CHECK PROCEDURE

Byte/Word Program Successful

SR.3=

VPP Range Error

Programming Error

Device Protect Error

SR.1=

SR.4=

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MX26F640J3

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . ..... -65

C to +150

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65

C to +125

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

OE, and RESET (Note 2) . . . . . . . .-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 7.

2. Minimum DC input voltage on pins OE and RESET is

-0.5 V. During voltage transitions OE and RESET may
overshoot VSS to -2.0 V for periods of up to 20 ns.
See Figure 6.

3. No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be
greater than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

). . . . . . . . . . . . 0

C to +70

Supply Voltages

for full voltage range. . . . . . . . . . . . .+3.0 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

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MX26F640J3

Symbol Parameter

Notes

Typ

Max

Unit

Test Conditions

ILI

Input and V PEN Load Current

VCC = VCC Max; VCCQ = VCCQ Max

VIN = VCCQ or GND

ILO

Output Leakage Current

VCC = VCC Max; VCCQ = VCCQ Max

VIN = VCCQ or GND

CMOS Inputs, VCC = VCC Max,

ICC1

VCC Standby Current

1,2,3

Device is disabled (see table 2)

RESET=VCCQ

0.2V

0.71

TTL Inputs, VCC=VCC max,

Device is disable (see table 2),

RESET=VIH

ICC2

VCC Power-Down Current

RESET=GND

0.2V

IOUT(STS)=0mA

CMOS Inputs, VCC=VCC Max,

VCCQ=VCCQ Max

Device is enabled (see Table 2)

ICC3

VCC Page Mode Read Current

1,3

f=5MHz, IOUT=0mA

CMOS Inputs, VCC=VCC Max,

VCCQ=VCCQ Max

Device is enabled (see Table 2)

f=33MHz, IOUT=0mA

ICC5

VCC Program or Set Lock-Bit

1,4

CMOS Inputs, VPEN=VCC

Current

TTL Inputs, VPEN=VCC

ICC6

VCC Block Erase or Clear

1,4

CMOS Inputs, VPEN=VCC

Block Lock-Bits Current

TTL Inputs, VPEN=VCC

DC Characteristics

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MX26F640J3

Symbol Parameter

Notes

Min

Max

Unit

Test Conditions

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VCCQ+0.5

0.4

VCCQ=VCCQ2/3 Min

IOL=2mA

VOL

Output Low Voltage

1,3

0.2

VCCQ=VCCQ2/3 Min

IOL=100uA

0.85 x

VCCQ=VCCQ Min

VCCQ

IOH=-2.5mA

VOH

Output High Voltage

1,3

VCCQ-0.2

VCCQ=VCCQ Min

IOH=-100uA

VPENLK VPEN Lockout during Program, 3,5,6

0.5 VCC

Erase and Lock-Bit Operations

VPENH VPEN during Block Erase,

5,6

3.0

3.6

Program, or Lock-Bit Operations

VLKO

VCC Lockout Voltage

2.2

DC Characteristics, Continued

NOTES:

1. Includes STS.

2. CMOS inputs are either VCC

0.2 V or GND

0.2 V. TTL inputs are either VIL or VIH .

3. Sampled, not 100% tested.

4. ICCWS and ICCES are specified with the device de-selected.

5. Block erases, programming, and lock-bit configurations are inhibited when V PEN ^ V PENLK , and not guaranteed

in the range between VPENLK (max) and VPENH (min), and above VPENH (max).

6. Typically, VPEN is connected to VCC (3.0 V - 3.6 V).

7. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed in the

range between VLKO (min) and VCC (min), and above VCC (max).

P/N:PM1114

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MX26F640J3

AC Characteristics --Read-Only Operations (1,2)

NOTES:CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at
the first edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE may be delayed up to t ELQV -t GLQV after the first edge of CE0, CE1, or CE2 that enables the device (see

Table 2) without impact on t ELQV .

3. See Figures 14-16, Transient Input/Output Reference Waveform for VCCQ = 3.0V - 3.6V, Transient Equivalent

Testing Load Circuit for testing characteristics. VCC = 3.0V - 3.6V.

4. When reading the eLiteFlash

memory array a faster tGLQV (R16) applies. Non-array reads refer to status register

reads, query reads, or device identifier reads.

5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).

Versions

VCC 3.0V-3.6V(3)

(All units in ns unless otherwise noted)

VCCQ 3.0V-3.6V(3)

Sym

Parameter

Notes

Min

Max

tAVAV

Read/Write Cycle Time

100

tAVQV

Address to Output Delay

100

tELQV

CEX to Output Delay

100

tGLQV

OE to Non-Array Output Delay

2, 4

tPHQV

RESET High to Output Delay

210

tELQX

CEX to Output in Low Z

tGLQX

OE to Output in Low Z

tEHQZ

CEX High to Output in High Z

tGHQZ

OE High to Output in High Z

tOH

Output Hold from Address, CEX, or OE

Change, Whichever Occurs First

tELFL/tELFH

CEX Low to BYTE High or Low

tFLQV/tFHQV BYTE to Output Delay

1000

tFLQZ

BYTE to Output in High Z

1000

tEHEL

CEx High to CEx Low

tAPA

Page Address Access Time

5, 6

tGLQV

OE to Array Output Delay

P/N:PM1114

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MX26F640J3

Figure 13. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations

NOTE:
1. CE

low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CE

high is defined at the first

edge of CE0, CE1, or CE2 that disables the device (see Table 2).

2. For standard word/byte read operations, tAPA will equal tAVQV.

3. When reading the eLiteFlash

memory array a faster tGLQV applies. Non-array reads refer to status register

reads, query reads, or device identifier reads.

tAVQV

tAVAV

tAPA

tGLQX

tELQX

tEHQZ

tEHEL

tGHQZ

tOH

tELFL/tELFH

tFLQV/tFHQV

tFLQZ

tELQV

tGLQV

High Z

tPHQV

Valid Address

Valid

Output

Valid

Output

Valid Address

Valid

Output

Valid

Output

High Z

Address

(A22-A3)

VIH

VIL

VIH

VIL

VIH

Disable

Enable VIL

VIH

VIL

Address

(A2-A0)

CEx[E]

OE [G]

VIH

VIL

WE [W]

VIH

VIL

VCC

VIH

VIL

RESET[P]

VIH

VIL

BYTE [F]

VOH

VOL

DATA[D/Q]

Q0- Q15

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MX26F640J3

AC Characteristics--Write Operations (1,2)

Versions

Valid for All

Speeds

Unit

Symbol

Parameter

Notes

Min

Max

tPHWL (tPHEL )

RESET High Recovery to WE(CEX) Going Low

210

tELWL (tWLEL )

CEX (WE) Low to WE(CEX) Going Low

tWP

Write Pulse Width

tDVWH (tDVEH )

Data Setup to WE(CEX) Going High

tAVWH (tAVEH )

Address Setup to WE(CEX) Going High

tWHEH (tEHWH)

CEX (WE) Hold from WE(CEX) High

tWHDX (tEHDX)

Data Hold from WE(CEX) High

tWHAX (tEHAX)

Address Hold from WE(CEX) High

tWPH

Write Pulse Width High

tVPWH (tVPEH)

VPEN Setup to WE(CEX) Going High

tWHGL (tEHGL)

Write Recovery before Read

tWHRL (tEHRL)

WE(CEX) High to STS Going Low

500

tQVVL

VPEN Hold from Valid SRD, STS Going High

3,8,9

tWHQV5 (tEHQV5) Set Lock-Bit Time

4,9

75/85

tWHQV6 (tEHQV6) Clear Block Lock-Bits Time

0.5

sec

NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as

during read-only operations. Refer to AC Characteristics-Read-Only Operations.

2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE going low (whichever goes low last) to CEX or WE going high

(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5. Refer to Table 4 for valid A IN and D IN for block erase, program, or lock-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE

going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .

7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY default mode.
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success

(SR.1/3/4/5=0).

P/N:PM1114

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MX26F640J3

Figure 14. AC Waveform for Write Operations

NOTES:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first

edge of CE0, CE1, or CE2 that disables the device (see Table 2).
STS is shown in its default mode (RY/BY).
a. VCC power-up and standby.
b. Write block erase, write buffer, or program setup.
c. Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.

tVPWH
(tVPEH)

tWHRL
(tEHRL)

tQVVL

tWHQZ/tWHRH

tWPH

tAVWH
(tAVEH)

tPHWL
(tPHEL)

tWP

tWHDX
(tEHDX)

tWHEH
(tEHWH)

tWHAX
(tEHAX)

tELWL
(tWLEL)

tOVWH
(tDVEH)

tWHGL
(tEHGL)

DIN

Address

(A)

VIH

VIL

VIH

VIL

VIH

Disable

Enable VIL

CEx,(WE)[E(W)]

VIH

Disable

Enable VIL

WE,(CEx)[W(E)]

VIH

VIL

DATA[D/Q]

VOH

VOL

STS[R]

VIH

VIL

VPENH

VPENLK

VIL

RESET [P]

VPEN[V]

DIN

AIN

DIN

Valid
SRD

P/N:PM1114

REV. 0.00, JUN. 30, 2004

MX26F640J3

Figure 15. AC Waveform for Reset Operation

NOTE:
1. STS is shown in its default mode (RY/BY).

Sym

Parameter

Notes

Min

Max

Unit

tPLPH

RESET Pulse Low Time

(If RESET is tied to VCC , this specification is not applicable)

tPHRH

RESET High to Reset during Block Erase, Program, or

100

Lock-Bit Configuration

NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the

minimum required RESET Pulse Low Time is 100ns.

3. A reset time, tPHQV, is required from the latter of STS (in RY/BY mode) or RESET going high until outputs are

valid.

Reset Specifications (1)

tPHRH

tPLPH

VIH

VIL

STS (R)

VIH

VIL

RESET (P)

P/N:PM1114

REV. 0.00, JUN. 30, 2004

MX26F640J3

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.

UNITS

Block Erase Time

2.0

15.0

sec

Write Buffer Byte Program Time

218

900

(Time to Program 32 bytes/16 words)

Byte Program Time (Using Word/Byte Program Command)

210

900

Block Program Time (Using Write to Buffer Command)

0.8

2.4

sec

Block Erase/Program Cycles

100

Cycles

ERASE AND PROGRAMMING PERFORMANCE(1)

Note:

1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25

C,3.3V. Additionally programming typically assume checkerboard pattern.

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

Years

125

Years

DATA RETENTION

MIN.

MAX.

Input Voltage with respect to GND on OE

-1.0V

12.5V

Input Voltage with respect to GND on all power pins, Address pins, CE and WE

-1.0V

2 VCCmax

Input Voltage with respect to GND on all I/O pins

-1.0V

VCC + 1.0V

Current

-100mA

+100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

LATCH-UP CHARACTERISTICS

Parameter Symbol

Parameter Description

Test Set

TYP

MAX

UNIT

CIN

Input Capacitance

VIN=0

7.5

COUT

Output Capacitance

VOUT=0

8.5

CIN2

Control Pin Capacitance

VIN=0

7.5

CAPACITANCE TA=0

°°
°°
°

C to 70

°°
°°
°

C, VCC=3.0V~3.6V

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA=25

C, f=1.0MHz

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