P/N:PM1123

REV. 1.1, NOV. 18, 2004

MX26LV160AT/AB

16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE

3V ONLY BOOT SECTOR HIGH SPEED eLiteFlash

MEMORY

- Provides a hardware method of detecting program or
erase operation completion

· Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors

· CFI (Common Flash Interface) compliant

- Flash device parameters stored on the device and
provide the host system to access

· 2K minimum erase/program cycles
· Latch-up protected to 100mA from -1V to VCC+1V
· Boot Sector Architecture

- T = Top Boot Sector
- B = Bottom Boot Sector

· Package type:

- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP

· Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

· 20 years data retention

FEATURES

· Extended single - supply voltage range 3.0V to 3.6V
· 2,097,152 x 8 / 1,048,576 x 16 switchable
· Single power supply operation

- 3.0V only operation for read, erase and program
operation

· Fast access time: 55/70ns
· Low power consumption

- 30mA maximum active current
- 30uA typical standby current

· Command register architecture

- Byte/word Programming (55us/70us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)

· Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
erase verify capability
- Automatically program and verify data at specified
address

· Status Reply

- Data# polling & Toggle bit for detection of program
and erase operation completion

· Ready/Busy# pin (RY/BY#)

GENERAL DESCRIPTION

The MX26LV160AT/AB is a 16-mega bit high speed Flash
memory organized as 2M bytes of 8 bits or 1M words of
16 bits. MXIC's high speed Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX26LV160AT/AB is pack-
aged in 44-pin SOP, 48-pin TSOP, and 48-ball CSP. It is
designed to be reprogrammed and erased in system or
in standard EPROM programmers.

The standard MX26LV160AT/AB offers access time as
fast as 55ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX26LV160AT/AB has separate chip enable
(CE#) and output enable (OE#) controls.

MXIC's high speed Flash memories augment EPROM
functionality with in-circuit electrical erasure and program-
ming. The MX26LV160AT/AB uses a command register
to manage this functionality. The command register al-

lows for 100% TTL level control inputs and fixed power
supply levels during erase and programming, while main-
taining maximum EPROM compatibility.

MXIC high speed Flash technology reliably stores
memory contents even after 2K erase and program
cycles. The MXIC cell is designed to optimize the erase
and programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low in-
ternal electric fields for erase and program operations
produces reliable cycling. The MX26LV160AT/AB uses
a 3.0V~3.6V VCC supply to perform the High Reliability
Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.

Macronix NBit

Memory Family

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

PIN CONFIGURATIONS

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A19

Address Input

Q0~Q14

Data Input/Output

Q15/A-1

Q15(Word mode)/LSB addr(Byte mode)

CE#

Chip Enable Input

WE#

Write Enable Input

BYTE#

Word/Byte Selection input

RESET#

Hardware Reset Pin

OE#

Output Enable Input

RY/BY#

Ready/Busy Output

VCC

Power Supply Pin (3.0V~3.6V)

GND

Ground Pin

44 SOP

48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down

A13

A12

A14

A15

A16

BYTE# Q15/A-1

GND

A10

A11

Q14

Q13

WE#

RESET#

A19

Q12

Vcc

RY/BY#

A18

Q10

Q11

A17

CE#

OE#

GND

A15
A14
A13
A12
A11
A10

A9
A8

A19

WE#

RESET#

NC
NC

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX26LV160AT/AB

48 TSOP (Standard Type) (12mm x 20mm)

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

GND

OE#

Q0
Q8
Q1
Q9
Q2

Q10

Q11

WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

MX26L

V160A

T/AB

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

BLOCK STRUCTURE

TABLE 1: MX26LV160AT SECTOR ARCHITECTURE

Sector Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode(x8)

Word Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12

SA0

64Kbytes

32Kwords

000000-00FFFF

00000-07FFF

SA1

64Kbytes

32Kwords

010000-01FFFF

08000-0FFFF

SA2

64Kbytes

32Kwords

020000-02FFFF

10000-17FFF

SA3

64Kbytes

32Kwords

030000-03FFFF

18000-1FFFF

SA4

64Kbytes

32Kwords

040000-04FFFF

20000-27FFF

SA5

64Kbytes

32Kwords

050000-05FFFF

28000-2FFFF

SA6

64Kbytes

32Kwords

060000-06FFFF

30000-37FFF

SA7

64Kbytes

32Kwords

070000-07FFFF

38000-3FFFF

SA8

64Kbytes

32Kwords

080000-08FFFF

40000-47FFF

SA9

64Kbytes

32Kwords

090000-09FFFF

48000-4FFFF

SA10

64Kbytes

32Kwords

0A0000-0AFFFF 50000-57FFF

SA11

64Kbytes

32Kwords

0B0000-0BFFFF 58000-5FFFF

SA12

64Kbytes

32Kwords

0C0000-0CFFFF 60000-67FFF

SA13

64Kbytes

32Kwords

0D0000-0DFFFF 68000-6FFFF

SA14

64Kbytes

32Kwords

0E0000-0EFFFF 70000-77FFF

SA15

64Kbytes

32Kwords

0F0000-0FFFFF 78000-7FFFF

SA16

64Kbytes

32Kwords

100000-10FFFF

80000-87FFF

SA17

64Kbytes

32Kwords

110000-11FFFF

88000-8FFFF

SA18

64Kbytes

32Kwords

120000-12FFFF

90000-97FFF

SA19

64Kbytes

32Kwords

130000-13FFFF

98000-9FFFF

SA20

64Kbytes

32Kwords

140000-14FFFF

A0000-A7FFF

SA21

64Kbytes

32Kwords

150000-15FFFF

A8000-AFFFF

SA22

64Kbytes

32Kwords

160000-16FFFF

B0000-B7FFF

SA23

64Kbytes

32Kwords

170000-17FFFF

B8000-BFFFF

SA24

64Kbytes

32Kwords

180000-18FFFF

C0000-C7FFF

SA25

64Kbytes

32Kwords

190000-19FFFF

C8000-CFFFF

SA26

64Kbytes

32Kwords

1A0000-1AFFFF D0000-D7FFF

SA27

64Kbytes

32Kwords

1B0000-1BFFFF D8000-DFFFF

SA28

64Kbytes

32Kwords

1C0000-1CFFFF E0000-E7FFF

SA29

64Kbytes

32Kwords

1D0000-1DFFFF E8000-EFFFF

SA30

64Kbytes

32Kwords

1E0000-1EFFFF F0000-F7FFF

SA31

32Kbytes

16Kwords

1F0000-1F7FFF

F8000-FBFFF

SA32

8Kbytes

4Kwords

1F8000-1F9FFF

FC000-FCFFF

SA33

8Kbytes

4Kwords

1FA000-1FBFFF FD000-FDFFF

SA34

16Kbytes

8Kwords

1FC000-1FFFFF FE000-FFFFF

Note: Byte mode: address range A19:A-1, word mode:address range A19:A0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

TABLE 2: MX26LV160AB SECTOR ARCHITECTURE

Sector Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode (x8) Word Mode (x16) A19 A18 A17 A16 A15 A14 A13 A12

SA0

16Kbytes

8Kwords

000000-003FFF

00000-01FFF

SA1

8Kbytes

4Kwords

004000-005FFF

02000-02FFF

SA2

8Kbytes

4Kwords

006000-007FFF

03000-03FFF

SA3

32Kbytes

16Kwords

008000-00FFFF

04000-07FFF

SA4

64Kbytes

32Kwords

010000-01FFFF

08000-0FFFF

SA5

64Kbytes

32Kwords

020000-02FFFF

10000-17FFF

SA6

64Kbytes

32Kwords

030000-03FFFF

18000-1FFFF

SA7

64Kbytes

32Kwords

040000-04FFFF

20000-27FFF

SA8

64Kbytes

32Kwords

050000-05FFFF

28000-2FFFF

SA9

64Kbytes

32Kwords

060000-06FFFF

30000-37FFF

SA10

64Kbytes

32Kwords

070000-07FFFF

38000-3FFFF

SA11

64Kbytes

32Kwords

080000-08FFFF

40000-47FFF

SA12

64Kbytes

32Kwords

090000-09FFFF

48000-4FFFF

SA13

64Kbytes

32Kwords

0A0000-0AFFFF 50000-57FFF

SA14

64Kbytes

32Kwords

0B0000-0BFFFF 58000-5FFFF

SA15

64Kbytes

32Kwords

0C0000-0CFFFF 60000-67FFF

SA16

64Kbytes

32Kwords

0D0000-0DFFFF 68000-6FFFF

SA17

64Kbytes

32Kwords

0E0000-0EFFFF 70000-77FFF

SA18

64Kbytes

32Kwords

0F0000-0FFFFF 78000-7FFFF

SA19

64Kbytes

32Kwords

100000-10FFFF

80000-87FFF

SA20

64Kbytes

32Kwords

110000-11FFFF

88000-8FFFF

SA21

64Kbytes

32Kwords

120000-12FFFF

90000-97FFF

SA22

64Kbytes

32Kwords

130000-13FFFF

98000-9FFFF

SA23

64Kbytes

32Kwords

140000-14FFFF

A0000-A7FFF

SA24

64Kbytes

32Kwords

150000-15FFFF

A8000-AFFFF

SA25

64Kbytes

32Kwords

160000-16FFFF

B0000-B7FFF

SA26

64Kbytes

32Kwords

170000-17FFFF

B8000-BFFFF

SA27

64Kbytes

32Kwords

180000-18FFFF

C0000-C7FFF

SA28

64Kbytes

32Kwords

190000-19FFFF

C8000-CFFFF

SA29

64Kbytes

32Kwords

1A0000-1AFFFF D0000-D7FFF

SA30

64Kbytes

32Kwords

1B0000-1BFFFF D8000-DFFFF

SA31

64Kbytes

32Kwords

1C0000-1CFFFF E0000-E7FFF

SA32

64Kbytes

32Kwords

1D0000-1DFFFF E8000-EFFFF

SA33

64Kbytes

32Kwords

1E0000-1EFFFF F0000-FFFFF

SA34

64Kbytes

32Kwords

1F0000-1FFFFF F8000-FFFFF

Note: Byte mode:address range A19:A-1, word mode:address range A19:A0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

AUTOMATIC PROGRAMMING

The MX26LV160AT/AB is word/byte programmable us-
ing the Automatic Programming algorithm. The Auto-
matic Programming algorithm makes the external sys-
tem do not need to have time out sequence nor to verify
the data programmed.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA# polling and a status bit
toggling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, table 7, for more
information on these status bits.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
The Automatic Erase algorithm automatically programs
the entire array prior to electrical erase. The timing and
verification of electrical erase are controlled internally
within the device.

AUTOMATIC SECTOR ERASE

The MX26LV160AT/AB is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,

provides the erase verification, and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the sta-
tus of the erasing operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.

MXIC's high speed Flash technology combines years of
EPROM experience to produce the highest levels of
quality, reliability, and cost effectiveness. The
MX26LV160AT/AB electrically erases all bits simulta-
neously using Fowler-Nordheim tunneling. The bytes are
programmed by using the EPROM programming mecha-
nism of hot electron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

AUTOMATIC SELECT

The auto select mode provides manufacturer and de-
vice identification, protection verification, through identi-
fier codes output on Q7~Q0. This mode is mainly adapted
for programming equipment on the device to be pro-
grammed with its programming algorithm. When program-
ming by high voltage method, automatic select mode re-
quires VID (11V to 12V) on address pin A9 and other
address pin A6, A1 and A0 as referring to Table 3. In
addition, to access the automatic select codes in-sys-
tem, the host can issue the automatic select command
through the command register without requiring VID, as
shown in table 4.

To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest order
address bit (see Table 1 and Table 2). The rest of address
bits, as shown in Table 3, are don't care. Once all neces-
sary bits have been set as required, the programming
equipment may read the corresponding identifier code on
Q7~Q0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

First Bus

Second Bus

Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Cycle Addr

Data Addr

Data

Addr

Data Addr

Data

Addr

Data Addr

Data

Reset

XXXH F0H

Read

Read Silicon ID

Word

555H AAH 2AAH

55H

555H

90H ADI

DDI

Byte

AAAH AAH 555H

55H

AAAH

90H ADI

DDI

Sector Protect

Word

555H AAH 2AAH

55H

555H

90H (SA)

XX00H

Verify

x02H XX01H

Byte

AAAH AAH 555H

55H

AAAH

90H (SA)

00H

x04H 01H

Program

Word

555H AAH 2AAH

55H

555H

A0H PA

Byte

AAAH AAH 555H

55H

AAAH

A0H PA

Chip Erase

Word

555H AAH 2AAH

55H

555H

80H 555H AAH

2AAH 55H

555H 10H

Byte

AAAH AAH 555H

55H

AAAH

80H AAAH AAH

555H

55H

AAAH 10H

Sector Erase

Word

555H AAH 2AAH

55H

555H

80H 555H AAH

2AAH 55H

30H

Byte

AAAH AAH 555H

55H

AAAH

80H AAAH AAH

555H

55H

30H

CFI Query

Word

555H 98

Byte

AAAH 98

TABLE 4. MX26LV160AT/AB COMMAND DEFINITIONS

Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care.

(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(Top), and 225B/5B(Bottom) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.
SA = Address of the sector.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.
Address bit A11~A19=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A19 in either state.

4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H, it

means the sector is still not being protected.

5. Any number of CFI data read cycles are permitted.

in the improper sequence will reset the device to the
read mode. Table 5 defines the valid register command
sequences.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

ADDRESS

Q8~Q15

DESCRIPTION

CE#

OE# WE#

RE-

A19 A11 A9 A8 A6 A5 A1 A0

Q0~Q7

BYTE

SET#

A12 A10

=VIH

=VIL

Read

AIN

Dout

Q8~Q14

=High Z

Q15=A-1

Write

AIN

DIN(3)

DIN

Reset

High Z

Output Disable

High Z

Standby

Vcc

High Z

0.3V

Sector Protect

VID

DIN

Chip Unprotect

VID

DIN

Sector Protection

X VID X

CODE(5)

Verify

TABLE 5. MX26LV160AT/AB BUS OPERATION

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2. VID is the Silicon-ID-Read high voltage, 11V to 12V.

3. Refer to Table 5 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

6. A19~A12=Sector address for sector protect.

7. The sector protect and chip unprotect functions may also be implemented via programming equipment.

COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Writing
incorrect address and data values or writing them in the improper sequence will reset the device to the read mode.
Table 5 defines the valid register command sequences.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

REQUIREMENTS FOR READING ARRAY
DATA

To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the de-
vice data outputs. The device remains enabled for read
access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory
, the system must drive WE# and CE# to VIL, and OE#
to VIH.

The "Word/byte Program Command Sequence" section
has details on programming data to the device.

An erase operation can erase one sector, multiple sec-
tors , or the entire device. Table indicates the address
space that each sector occupies. A "sector address"
consists of the address bits required to uniquely select a
sector. The "Writing specific address and data commands
or sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip.

After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The sys-
tem can then read autoselect codes from the internal
register (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.

ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC

Characteristics" section contains timing specification
table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE# and RESET#, the device
enter CMOS Standby with both pins held at VCC

0.3V.

If CE# and RESET# are held at VIH, but not within the
range of VCC

0.3V, the device will still be in the standby

mode, but the standby current will be larger. During Auto
Algorithm operation, Vcc active current (Icc2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output
from the devices are disabled. This will cause the output
pins to be in a high impedance state.

RESET# OPERATION

The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RESET#
pin is driven low for at least a period of tRP, the device
immediately terminates any operation in progress, tri-
states all output pins, and ignores all read/write com-
mands for the duration of the RESET# pulse. The de-
vice also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity

Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS±0.3V, the standby current will be
greater.

The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the high speed
Flash, enabling the system to read the boot-up firmware
from the high speed Flash.

If RESET# is asserted during a program or erase opera-
tion, the RY/BY# pin remains a "0" (busy) until the inter-

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

nal reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms). The system can
thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The sys-
tem can read data tRH after the RESET# pin returns to
VIH.

Refer to the AC Characteristics tables for RESET#
parameters and to Figure 21 for the timing diagram.

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.

SILICON-ID READ COMMAND

High speed Flash memories are intended for use in ap-
plications where the local CPU alters memory contents.
As such, manufacturer and device codes must be ac-
cessible while the device resides in the target system.
PROM programmers typically access signature codes
by raising A9 to a high voltage (VID). However, multi-
plexing high voltage onto address lines is not generally
desired system design practice.

The MX26LV160AT/AB contains a Silicon-ID-Read op-
eration to supple traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter.

SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H or
sector erase command 30H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1" (see Table 7), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE# or CE# pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" at which time the device returns to the Read
mode, or the data on Q6 stops toggling for two consecu-
tive read cycles at which time the device returns to the
Read mode.

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MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

READING ARRAY DATA

The device is automatically set to reading array data
after device power-up. No commands are required to re-
trieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.

The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the "read silicon-ID" and "sector protect verify"
mode. See the "Reset Command" section, next.

Pins

Q15~Q8 Q7

Q2 Q1

Code (Hex)

Manufacture code

Word VIL

VIL

00H

00C2H

Byte

VIL

C2H

Device code

Word

VIH

VIL

22H

22C4H

for MX26LV160AT

Byte

VIH

VIL

C4H

Device code

Word

VIH

VIL

22H

2249H

for MX26LV160AB

Byte

VIH

VIL

49H

Sector Protection

Word

VIH X

01H (Protected)

Verification

Byte X

VIH X

00H (Unprotected)

TABLE 6. SILICON ID CODE

RESET COMMAND

Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care for
this command.

The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.

The reset command may be written between the se-
quence cycles in a program command sequence before
programming begins. This resets the device to reading
array data Once programming begins, however, the de-
vice ignores reset commands until the operation is com-
plete.

The reset command may be written between the se-
quence cycles in an SILICON ID READ command se-
quence. Once in the SILICON ID READ mode, the reset
command must be written to return to reading array data.

If Q5 goes high during a program or erase operation, writ-
ing the reset command returns the device to read-ing
array data.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when either the data on Q7 is "1" at which time the de-
vice returns to the Read mode, or the data on Q6 stops
toggling for two consecutive read cycles at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of WE#
or CE#, whichever happens later, while the command
(data) is latched on the rising edge of WE# or CE#,
whichever happens first. Sector addresses selected are
loaded into internal register on the sixth falling edge of
WE# or CE#, whichever happens later. Each succes-
sive sector load cycle started by the falling edge of WE#
or CE#, whichever happens later must begin within 50us
from the rising edge of the preceding WE# or CE#, which-
ever happens first. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase (30H) during the time-out period re-
sets the device to read mode.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program

address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not re-
quired to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 1 shows the address
and data requirements for the word/byte program com-
mand sequence.

When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using Q7, Q6, or RY/
BY#. See "Write Operation Status" for information on these
status bits.

Any commands written to the device during the Embed-
ded Program Algorithm are ignored. Note that a hardware
reset immediately terminates the programming operation.
The word/byte Program command sequence should be
reinitiated once the device has reset to reading array
data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the op-
eration and set Q5 to "1", or cause the Data# Polling
algorithm to indicate the operation was successful. How-
ever, a succeeding read will show that the data is still
"0". Only erase operations can convert a "0" to a "1".

WRITE OPERATION STATUS

The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY#. Table 7 and the following subsections describe the
functions of these bits. Q7, RY/BY#, and Q6 each offer a
method for determining whether a program or erase op-
eration is complete or in progress. These three bits are
discussed first.

Q7: Data# Polling

The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command se-
quence.

During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed to

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MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Q7. When the Automatic Program algorithm is complete,
the device outputs the datum programmed to Q7. The
system must provide the program address to read valid
status information on Q7.

During the Automatic Erase algorithm, Data# Polling pro-
duces a "0" on Q7. When the Automatic Erase algorithm
is complete, Data# Polling produces a "1" on Q7. This is
analogous to the complement/true datum out-put de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement," or "0". The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output Enable
(OE#) is asserted low.

RY/BY# : Ready/Busy

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY# status is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied
together in parallel with a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing
or programming. If the output is high (Ready), the device
is ready to read array data, or is in the standby mode.

Table 7 shows the outputs for RY/BY# during write op-
eration.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete. Toggle
Bit I may be read at any address, and is valid after the
rising edge of the final WE# or CE#, whichever happens
first, in the command sequence (prior to the program or
erase operation), and during the sector time-out.

During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles. When the operation is complete,
Q6 stops toggling.

When the device is actively erasing (that is, the Auto-
matic Erase algorithm is in progress), Q6 toggling. How-
ever, the system must also use Q2 to determine which
sectors are erasing. Alternatively, the system can use
Q7.

Q6 stops toggling once the Automatic Program algorithm
is complete.

Table 7 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process). Toggle Bit
II is valid after the rising edge of the final WE# or CE#,
whichever happens first, in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish when the sector is
actively erasing or is in Erase Suspend. Q6, by com-
parison, indicates when the device is actively erasing
but cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sectors and
mode information. Refer to Table 7 to compare outputs
for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase opera-
tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the al-
gorithm when it returns to determine the status of the
operation.

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded
the specified limits (internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not suc-
cessfully completed. Data# Polling and Toggle Bit are
the only operating functions of the device under this con-
dition.

If this time-out condition occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.

If this time-out condition occurs during the word/byte pro-
gramming operation, it specifies that the entire sector
containing that byte is bad and this sector may not be
reused, (other sectors are still functional and can be re-
used).

The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please note
that this is not a device failure condition since the device
was incorrectly used.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.

POWER-UP SEQUENCE

The MX26LV160AT/AB powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously
protected sector to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET# pin to VID (11.5V-12.5V). During this mode,
formerly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET# pin. All the previously protected sectors are pro-
tected again.

SECTOR PROTECTION

The MX29LV160AT/AB features hardware sector protec-
tion. This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and OE# (suggest VID = 12V). Program-
ming of the protection circuitry begins on the falling edge
of the WE# pulse and is terminated on the rising edge.
Please refer to sector protect algorithm and waveform.

To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"
code at device output Q0 for a protected sector. Other-
wise the device will produce 00H for the unprotected sec-
tor. In this mode, the addresses, except for A1, are don't
care. Address locations with A1 = VIL are reserved to
read manufacturer and device codes. (Read Silicon ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.

If Data# Polling or the Toggle Bit indicates the device
has been written with a valid erase command, Q3 may
be used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

DATA PROTECTION

The MX26LV160AT/AB is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.

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MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

The system must write the reset command to exit the
"Silicon-ID Read Command" code.

CHIP UNPROTECT

The MX29LV160AT/AB also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
code. It is recommended to protect all sectors before
activating chip unprotect mode.

To activate this mode, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to VIH.
Refer to chip unprotect algorithm and waveform for the
chip unprotect algorithm. The unprotection mechanism
begins on the falling edge of the WE# pulse and is
terminated on the rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . ..... -65

C to +150

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65

C to +125

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . . . . . . -0.5 V to +12 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may over-
shoot to VCC +2.0 V for periods up to 20 ns.

2. Minimum DC input voltage on pins A9, OE#, and RE-

SET# is -0.5 V. During voltage transitions, A9, OE#,
and RESET# may overshoot VSS to -2.0 V for peri-
ods of up to 20 ns. Maximum DC input voltage on pin
A9 is +12 V which may overshoot to 13.5V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be
greater than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

). . . . . . . . . . . . 0

C to +70

Supply Voltages

for full voltage range. . . . . . . . . . . +3.0 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN1

Input Capacitance

VIN = 0V

CIN2

Control Pin Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

MX26LV160AT/AB

Symbol

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

VIN = VSS to VCC

ILIT

A9 Input Leakage Current

200

VCC=VCC max;

A9=12V

ILO

Output Leakage Current

VOUT = VSS to VCC,

VCC=VCC max

ICC1

VCC Active Read Current

CE#=VIL,

@5MHz

OE#=VIH

@1MHz

ICC2

VCC Active write Current

CE#=VIL, OE#=VIH

ICC3

VCC Standby Current

100

CE#; RESET#=VCC

0.3V

ICC4

VCC Standby Current

100

RESET#=VSS

0.3V

During Reset

VIL

Input Low Voltage (Note 1)

-0.5

0.8

VIH

Input High Voltage

0.7xVCC

VCC+0.3

VID

Voltage for Automatic Select

VCC=3.3V

and Temporary Sector Unprotect

VOL

Output Low Voltage

0.45

IOL = 4.0mA,

VCC= VCC min

VOH1

Output High Voltage (TTL)

0.85xVCC

IOH = -2mA,

VCC=VCC min

VOH2

Output High Voltage

VCC-0.4

IOH = -100uA, VCC min

(CMOS)

TABLE 8. DC CHARACTERISTICS

TA = 0

C to 70

C, VCC = 3.0V~3.6V

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

26LV160AT/AB-55

26LV160AT/AB-70

SYMBOLPARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

CONDITIONS

tRC

Read Cycle Time (Note 1)

tACC

Address to Output Delay

CE#=OE#=VIL

tCE

CE# to Output Delay

OE#=VIL

tOE

OE# to Output Delay

CE#=VIL

tDF

OE# High to Output Float (Note1)

CE#=VIL

tOEH

Output

Read

Enable

Toggle and

Hold Time

Data# Polling

tOH

Address to Output hold

CE#=OE#=VIL

NOTE:

1. Not 100% tested.
2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

· Input pulse levels: 0V/3.0V.
· Input rise and fall times is equal to or less than 5ns.
· Output load: 1 TTL gate + 100pF (Including scope and

jig), for 26LV160AT/AB-70. 1 TTL gate + 30pF (Includ-
ing scope and jig) for 26LV160AT/AB-55.

· Reference levels for measuring timing: 1.5V.

AC CHARACTERISTICS TA = 0

C to 70

C, VCC = 3.0V~3.6V

TABLE 9. READ OPERATIONS

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

AC CHARACTERISTICS TA = 0

C to 70

C, VCC = 3.0V~3.6V

TABLE 10. Erase/Program Operations

26LV160AT/AB-55

26LV160AT/AB-70

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tWC

Write Cycle Time (Note 1)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tOES

Output Enable Setup Time

tGHWL

Read Recovery Time Before Write

(OE# High to WE# Low)

tCS

CE# Setup Time

tCH

CE# Hold Time

tWP

Write Pulse Width

tWPH

Write Pulse Width High

tWHWH1

Programming Operation (Note 2)

55/70(TYP.)

(Byte/Word program time)

tWHWH2

Sector Erase Operation (Note 2)

2.4(TYP.)

sec

tVCS

VCC Setup Time (Note 1)

tRB

Recovery Time from RY/BY#

tBUSY

Program/Erase Valid to RY/BY# Delay

tWPP1

Write pulse width for sector

100ns

10us(typ.)

100ns

10us(typ.)

protect (A9, OE# Control)

tWPP2

Write pulse width for sector

100ns

12ms(typ.) 100ns

12ms(typ.)

unprotect (A9, OE# Control)

tVLHT

Voltage transition time

tOESP

OE# setup time to WE# active

tBAL

Sector Address Load Time

NOTES:

1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

26LV160AT/AB-55

26LV160AT/AB-70

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tWC

Write Cycle Time (Note 1)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tOES

Output Enable Setup Time

tGHEL

Read Recovery Time Before Write

tWS

WE# Setup Time

tWH

WE# Hold Time

tCP

CE# Pulse Width

tCPH

CE# Pulse Width High

tWHWH1

Programming

Byte

55(Typ.)

Operation(note2)

Word

70(Typ.)

tWHWH2

Sector Erase Operation (note2)

2.4(Typ.)

sec

NOTE:

1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

AC CHARACTERISTICS TA = 0

C to 70

C, VCC = 3.0V~3.6V

TABLE 11. Alternate CE# Controlled Erase/Program Operations

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

AUTOMATIC PROGRAMMING TIMING WAVEFORM

FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tion can be verified by DATA# polling and toggle bit check-

ing after automatic programming starts. Device outputs
DATA# during programming and DATA# after program-
ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA#
polling, timing waveform)

tWC

Address

OE#

CE#

A0h

555h

Status

DOUT

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

tAS

tAH

tGHWL

tCH

tWP

tDS

tDH

tWHWH1

Read Status Data (last two cycle)

Program Command Sequence(last two cycle)

tBUSY

tRB

tCS

tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector indicated by A12 to A19 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA# polling and toggle bit check-

ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7. (Q6 is for toggle
bit; see toggle bit, DATA# polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tWC

Address

OE#

CE#

55h

2AAh

Sector

Address 1

Sector

Address 0

30h

Progress Complete

30h

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Sector

Address n

tAS

tAH

tBAL

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data

Erase Command Sequence(last two cycle)

tBUSY

tRB

tCS

tWPH

tVCS

WE#

Data

RY/BY#

VCC

30h

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX26LV160AT/AB is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating param-
eters and configuration. Two commands are required in
CFI mode. Query command of CFI mode is placed first,
then the Reset command exits CFI mode. These are

described in Table 15.

The single cycle Query command is valid only when the
device is in the Read mode, Standby mode, and Auto-
matic Select mode; however, it is ignored otherwise.

The Reset command exits from the CFI mode to the
Read mode, or Automatic Select mode. The command is
valid only when the device is in the CFI mode.

Table 15-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Query-unique ASCII string "QRY"

0051

0052

0059

Primary vendor command set and control interface ID code

0002

0000

Address for primary algorithm extended query table

0040

0000

Alternate vendor command set and control interface ID code (none)

0000

Address for secondary algorithm extended query table (none)

0000

Table 15-2. CFI Mode: System Interface Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

VCC supply, minimum (3.0V)

0030

VCC supply, maximum (3.6V)

0036

VPP supply, minimum (none)

0000

VPP supply, maximum (none)

0000

Typical timeout for single word/byte write (2

us)

0004

Typical timeout for Minimum size buffer write (2

us) (not supported)

0000

Typical timeout for individual sector erase (2

ms)

000A

Typical timeout for full chip erase (2

ms)

0000

Maximum timeout for single word/byte write times (2

X Typ)

0005

Maximum timeout for buffer write times (2

X Typ)

0000

Maximum timeout for individual sector erase times (2

X Typ)

0004

Maximum timeout for full chip erase times (not supported)

0000

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Table 15-3. CFI Mode: Device Geometry Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Device size (2

bytes)

0015

Flash device interface code (x8/x16 async.)

0002

0000

Maximum number of bytes in multi-byte write (not supported)

0000

Number of erase sector regions

0004

Erase sector region 1 information (refer to the CFI publication 100)

0000

0040

0000

Erase sector region 2 information

0001

0000

0020

0000

Erase sector region 3 information

0000

0080

0000

Erase sector region 4 information

001E

0000

0001

Table 15-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Query-unique ASCII string "PRI"

0050

0052

0049

Major version number, ASCII

0031

Minor version number, ASCII

0030

Address sensitive unlock (0=required, 1= not required)

0000

Erase suspend (0=not supported)

0000

Sector protect (0=not supported)

0000

Temporary sector unprotect (0=not supported)

0000

Sector protect/chip unprotect scheme (0=not supported)

0004

Simultaneous R/W operation (0=not supported)

0000

Burst mode type (0=not supported)

0000

Page mode type (0=not supported)

0000

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

LIMITS

PARAMETER

MIN.

TYP. (2)

MAX. (3)

UNITS

Sector Erase Time

2.4

sec

Chip Erase Time

320

sec

Byte Programming Time

220

Word Programming Time

280

Chip Programming Time (Word/Byte Mode)

140

sec

Erase/Program Cycles

2K (6)

Cycles

TABLE 17. LATCH-UP CHARACTERISTICS

TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1)

Note:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions : 25

C, 3.3V VCC. Programming spec. assume

that all bits are programmed to checkerboard pattern.

3. Maximum values are measured at VCC=3.0V, worst case temperature. Maximum values are up to including 2K

program/erase cycles.

4. System-level overhead is the time required to execute the command sequences for the all program command.
5. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits

are programmed to 00H before erasure)

6. Min. erase/program cycles is under : 3.3V VCC, 25

C, checkerboard pattern conditions, and without baking process.

MIN.

MAX.

Input Voltage with respect to GND on ACC, OE#, RESET#, A9

-1.0V

12V

Input Voltage with respect to GND on all power pins, Address pins, CE# and WE#

-1.0V

VCC + 1.0V

Input Voltage with respect to GND on all I/O pins

-1.0V

VCC + 1.0V

Current

-100mA

+100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

ORDERING INFORMATION

PART NO.

ACCESS

OPERATING

STANDBY

PACKAGE

Remark

TIME (ns)

Current MAX. (mA)

Current MAX. (uA)

MX26LV160ATMC-55

100

44 Pin SOP

MX26LV160ATMC-70

100

44 Pin SOP

MX26LV160ABMC-55

100

44 Pin SOP

MX26LV160ABMC-70

100

44 Pin SOP

MX26LV160ATTC-55

100

48 Pin TSOP

(Normal Type)

MX26LV160ABTC-55

100

48 Pin TSOP

(Normal Type)

MX26LV160ATTC-70

100

48 Pin TSOP

(Normal Type)

MX26LV160ABTC-70

100

48 Pin TSOP

(Normal Type)

MX26LV160ATXBC-55

100

48 Ball CSP

(Ball size:0.3mm)

MX26LV160ABXBC-55

100

48 Ball CSP

(Ball size:0.3mm)

MX26LV160ATXBC-70

100

48 Ball CSP

(Ball size:0.3mm)

MX26LV160ABXBC-70

100

48 Ball CSP

(Ball size:0.3mm)

MX26LV160ATXEC-55

100

48 Ball CSP

(Ball size:0.4mm)

MX26LV160ABXEC-55

100

48 Ball CSP

(Ball size:0.4mm)

MX26LV160ATXEC-70

100

48 Ball CSP

(Ball size:0.4mm)

MX26LV160ABXEC-70

100

48 Ball CSP

(Ball size:0.4mm)

MX26LV160ATMC-55G

100

44 Pin SOP

Pb-free

MX26LV160ATMC-70G

100

44 Pin SOP

Pb-free

MX26LV160ABMC-55G

100

44 Pin SOP

Pb-free

MX26LV160ABMC-70G

100

44 Pin SOP

Pb-free

MX26LV160ATTC-55G

100

48 Pin TSOP

Pb-free

(Normal Type)

MX26LV160ABTC-55G

100

48 Pin TSOP

Pb-free

(Normal Type)

MX26LV160ATTC-70G

100

48 Pin TSOP

Pb-free

(Normal Type)

MX26LV160ABTC-70G

100

48 Pin TSOP

Pb-free

(Normal Type)

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