P/N:PM0593

REV. 1.4, NOV. 19, 2002

MX27C1610

16M-BIT [2M x 8/1M x 16] CMOS OTP ROM

GENERAL DESCRIPTION

The MX27C1610 is a 16M-bit, One Time Programmable
Read Only Memory. It is organized as 2M x 8 or 1M x
16 and has a static standby mode, and features fast
programming. For programming outside from the sys-
tem, existing EPROM programmers may be used. The
MX27C1610 supports a intelligent fast programming al-

gorithm which can result in programming time of less
than two minutes.

This One Time Programmable Read Only Memory is
packaged in industry standard 42 pin dual-in-line plas-
tic package.

PIN CONFIGURATIONS

PDIP

PIN DESCRIPTION

SYMBOL

PIN NAME

A0~A19

Address Input

Q0~Q14

Data Input/Output

Chip Enable Input

Output Enable Input

BYTE/VPP

Word/Byte Selection

/Program Supply Voltage

Q15/A-1

Q15(Word mode)/LSB addr. (Byte

mode)

VCC

Power Supply Pin (+5V)

GND

Ground Pin

BLOCK DIAGRAM

PRELIMINARY

FEATURES

2M x 8 or 1M x 16 organization

5V Vcc for Read operation

10V Vpp Programming operation

Fast access time: 100/120 ns

Totally static operation

Completely TTL compatible

Operating current: 60mA

Standby current: 100uA

Package type:
- 42 pin plastic DIP

CONTROL

LOGIC

OUTPUT

BUFFERS

Q0~Q14

Q15/A-1

BYTE/VPP

A0~A19

ADDRESS

INPUTS

Y-DECODER

X-DECODER

Y-DECODER

16M BIT

CELL

MAXTRIX

VCC

VSS

MX27C1610

A18

A17

GND

Q10

Q11

A19

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

Q15/A-1

Q14

Q13

Q12

VCC

P/N:PM0593

REV. 1.4, NOV. 19, 2002

MX27C1610

WORD MODE(BYTE = VCC)

Q15/A-1

MODE

Q0-Q7

SUPPLY CURRENT

High Z

Non selected

High Z

Standby(ICC2)

High Z

Non selected

High Z

Operating(ICC1)

DOUT

Selected

DOUT

Operating(ICC1)

NOTE : X = H or L

TRUTH TABLE OF BYTE FUNCTION

BYTE MODE(BYTE = GND)

Q15/A-1

MODE

Q0-Q7

SUPPLY CURRENT

Non selected

High Z

Standby(ICC2)

Non selected

High Z

Operating(ICC1)

A-1 input

Selected

DOUT

Operating(ICC1)

FUNCTIONAL DESCRIPTION

READ MODE

The MX27C1610 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and ad-
dresses have been stable for at least tACC - t OE.

WORD-WIDE MODE

With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.

BYTE-WIDE MODE

With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tri-
stated. If Q15/A-1 = VIH, outputs Q0-7 present data
bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data
bits Q0-7.

STANDBY MODE

The MX27C1610 has a CMOS standby mode which re-
duces the maximum VCC current to 100 uA. It is placed
in CMOS standby when CE is at VCC

0.2V. The

MX27C1610 also has a TTL-standby mode which re-
duces the maximum VCC current to 4 mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-
line control function is provided to allow for:

1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as
the primary device-selecting function, while OE be made
a common connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the out-
put pins are only active when data is desired from a
particular memory device.

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REV. 1.4, NOV. 19, 2002

MX27C1610

SYSTEM CONSIDERATIONS

During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on One Time
Programmable Read Only Memory arrays, a 4.7 uF
bulk electrolytic capacitor should be used between VCC
and GND for each eight devices. The location of the
capacitor should be close to where the power supply is
connected to the array.

WRITE OPERATIONS

Commands are written to the COMMAND INTERFACE
REGISTER (CIR) using standard microprocessor write
timings. The CIR serves as the interface between the
microprocessor and the internal chip operation. The
CIR can decipher Read Array, Read Silicon ID and Pro-
gram command. In the event of a read command, the
CIR simply points the read path at either the array or
the silicon ID, depending on the specific read command
given. For a program cycle, the CIR informs the write
state machine, and the write state machine and the write
state machine will control the program sequences and
the CIR will only respond to status reads. After the
write state machine has completed its task, it will allow
the CIR to respond to its full command set. The CIR
stays at read status register mode until the microproc-
essor issues another valid command sequence.

Device operations are selected by writing commands
into the CIR. See command definition table below.

MODE SELECT TABLE

BYTE/

MODE

Q15/A-1

VPP(5)

Q8-14

Q0-7

Read (Word) (2)

VIL

Q15 Out

VIH

Q8-14 Out

Q0-7 Out

Read (Upper Byte) (2)

VIL

VIH

VIL

High Z

Q8-15 Out

Read (Lower Byte) (2)

VIL

High Z

Q0-7 Out

Output Disable (2)

VIL

VIH

High Z

Standby (2)

VIH

High Z

Write Operation (2)

VIL

VIH

Q15 In

VPP

Q8-14 In

Q0-7 In

ManufacturerID(3)(1)

VIL

VIH

00H

C2H

Device ID(3)(1)

VIL

VIH

00H

6AH

NOTES:
1. VH = 10V ± 0.5V
2. X Either VIL or VIH.
3. A1= VIL, other address lines not specified are at "X" states
4. See DC Programming Characteristics for VPP voltages.
5. BYTE/VPP is intended for operation under DC Voltage conditions only. VPP=10V±

0.5V for write operation

P/N:PM0593

REV. 1.4, NOV. 19, 2002

MX27C1610

Command

Read/

Silicon

Page/Byte

Read

Clear

Sequence

Reset

ID Read

Program

Status Reg.

Bus Write

Cycles Req'd

First Bus

Addr

5555H

Write Cycle

Data

AAH

Second Bus

Addr

2AAAH

Write Cycle

Data

55H

Third Bus

Addr

5555H

Write Cycle

Data

F0H

90H

A0H

70H

50H

Fourth Bus

Addr

00H/01H

Read/Write Cycle Data

C2H/6AH

SRD

COMMAND DEFINITIONS OF WRITE OPERATION TABLE

NOTES:
1. In the write operation mode, BYTE/VPP should be set to 10V

±0

.5V.

2. 5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.
3. RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
PO=Data to be programmed at location PA.

DEVICE OPERATION

SILICON ID READ

The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manu-
facturer and type. This mode is intended for use by
programming equipment for the purpose of automati-
cally matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional over the entire temperature range of the de-
vice.

MX27C1610 Silion ID Codes

Type

Code(HEX) DQ

Manufacturer Code** X X

VIL

C2H*

Device Code**

X X

VIL

VIH

6AH*

* The high byte of the code will be 00H and low byte of the code will be C2H for Manufacturer code and 6AH of Device code.
** All other address lines not specified are also at "X" state. X=VIH or VIL.

To activate this mode, the programming equipment must
force VID (10V

o.5V) on address pin A9. Two identifier

bytes may then be sequenced from the device outputs
by toggling address A0 from VIL to VIH. All addresses
are don't cares except A0 and A1.

The manufacturer and device codes may also be read
via the command register, for instances when the
MX27C1610 is programmed in a system without access
to high voltage on the A9 pin.

P/N:PM0593

REV. 1.4, NOV. 19, 2002

MX27C1610

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the CIR contents are altered by a valid command
sequence.

The device will automatically power-up in the read/re-
set state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value en-
sures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing
parameters.

The MX27C1610 is accessed when CE and OE are low
the data stored at the memory location determined by
the address pins is asserted on the outputs. The out-
puts are put in the high impedance state whenever CE
or OE is high. This dual line control gives designers
flexibility in preventing bus contention.

Note that the read/reset command is not valid when pro-
gram is in progress.

PAGE PROGRAM

The device is set up in the programming mode when
the programming Voltage Vpp=10V is applied with
Vcc=5V, and OE=VIH.

Any attempt to write to the device without the three-
cycle command sequence will not start the internal Write
State Machine(WSM), no data will be written to the de-
vice.

After three-cycle command (see command table) se-
quence is given, a word load is performed by applying a
low pulse on the CE input with CE low and OE high.
The address is latched on the falling edge of CE The
data is latched by the rising edge of CE . Maximum of
128 bytes of data may be loaded into each page by the
same procedure as outlined in the page program sec-
tion below.

WORD-WIDE LOAD

Word loads are used to enter the 128 bytes(64 words)
of a page to be programmed or the software codes for
data protection. A word load is performed by applying a
low pulse on the CE input with CE and OE high. The
address is latched on the falling edge of CE. The data is
latched by the rising edge of CE.

PROGRAM

The device is programmed on a page basis. Once the
bytes of a page are loaded into the device, they are
simultaneously programmed during the internal pro-
gramming period. After the first data word has been
loaded into the device, successive words are entered in
the same manner. The time between word loads must
be less than 30us otherwise the load period could be
teminated. A6 to A19 specify the page address, i.e.,
the device is page-aligned on 128 bytes(64
words)boundary. The page address must be valid dur-
ing each high to low transition of CE. A0 to A5 specify
the word address withih the page. The word may be
loaded in any order; sequential loading is not required.
If a high to low transition of CE is not detected whithin
100us of the last low to high transition, the load period
will end and the internal programming period will start.
The Auto page program terminates when status on Q7
is "1" at which time the device stays at read status reg-
ister mode until the CIR contents are altered by a valid
command sequence.

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