1
P/N: PM0515
FEATURES
5.0V
10% for read, erase and write operation
131072x8 only organization
Fast access time: 55/70/90/120ns
Low power consumption
- 30mA maximum active current(5MHz)
- 1u
A
typical standby current
Command register architecture
- Byte Programming (7us typical)
- Sector Erase (8K-Byte x 1, 4K-Byte x 2, 8K Byte
x 2, 32K-Byte x 1, and 64K-Byte x 1)
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically programs and verifies data at
specified address
Erase Suspend/Erase Resume
Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.
Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/12V
system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP
Boot Code Sector Architecture
- T=Top Boot Sector
- B=Bottom Boot Sector
20 years data retention
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's
Flash memories offer the most cost-effective and
reliable read/write non-volatile random access
memory. The MX29F001T/B is packaged in 32-pin
PLCC, TSOP, PDIP. It is designed to be repro-
grammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F001T/B offers access time as
fast as 55ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX29F001T/B has separate
chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM function-
a l i t y w i t h i n - c i r c u i t e l e c t r i c a l e r a s u r e a n d
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs
and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
o p e r a t i o n s p r o d u c e s r e l i a b l e c y c l i n g . T h e
MX29F001T/B uses a 5.0V
10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
MX29F001T/B
1M-BIT [128K x 8] CMOS FLASH MEMORY
REV. 2.5, NOV. 20, 2002
2
REV. 2.5,NOV. 20, 2002
P/N: PM0515
MX29F001T/B
PIN CONFIGURATIONS
32 TSOP (TYPE 1)
PIN DESCRIPTION:
(NORMAL TYPE)
SECTOR STRUCTURE
MX29F001T Sector Architecture
MX29F001B Sector Architecture
SYMBOL
PIN NAME
A0~A16
Address Input
Q0~Q7
Data Input/Output
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
VCC
Power Supply Pin (+5V)
GND
Ground Pin
MX29F001T/B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
1
4
5
9
13
14
17
20
21
25
29
32
30
A14
A13
A8
A9
A11
OE
A10
CE
Q7
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
Q3
Q4
Q5
Q6
A12
A15
A16
NC
VCC
WE
NC
MX29F001T/B
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F001T/B
8 K - B Y T E
0 0 0 0 0 H
6 4 K - B Y T E
3 2 K - B Y T E
8 K - B Y T E
8 K - B Y T E
4 K - B Y T E
4 K - B Y T E
1 F F F F H
0 F F F F H
0 5 F F F H
0 2 F F F H
0 1 F F F H
0 3 F F F H
A 1 6 ~ A 0
0 7 F F F H
6 4 K - B Y T E
0 0 0 0 0 H
8 K - B Y T E
4 K - B Y T E
4 K - B Y T E
8 K - B Y T E
8 K - B Y T E
3 2 K - B Y T E
1 F F F F H
1 D F F F H
1 C F F F H
1 9 F F F H
1 7 F F F H
0 F F F F H
1 B F F F H
A 1 6 ~ A 0
32 PLCC
32 PDIP
3
REV. 2.5,NOV. 20, 2002
P/N: PM0515
MX29F001T/B
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
MX29F001T/B
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y
-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q7
A0-A16
CE
OE
WE
4
REV. 2.5,NOV. 20, 2002
P/N: PM0515
MX29F001T/B
AUTOMATIC PROGRAMMING
The MX29F001T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Program-
ming algorithm does not require the system to time out
or verify the data programmed. The typical chip pro-
gramming time of the MX29F001T/B at room tempera-
ture is less than 3.5 seconds.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 3 second. The Automatic Erase algorithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
internally controlled within the device.
AUTOMATIC SECTOR ERASE
The MX29F001T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally con trolled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provides feed-
back to the user as to the status of the programming
operation.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches addresses and data needed for the pro-
gramming and erase operations. During a system write
cycle, addresses are latched on the falling edge, and
data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F001T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
5
REV. 2.5,NOV. 20, 2002
P/N: PM0515
MX29F001T/B
First Bus
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Command
Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr Data
Addr
Data
Reset
1
XXXH
F0H
Read
1
RD
RD
Read Silicon ID
4
555H
AAH
2AAH
55H
555H
90H
ADI
DDI
Chip Protect Verify
4
555H
AAH
2AAH
55H
555H
90H
(SA)
00H
X02H
01H
Program
4
555H
AAH
2AAH
55H
555H A0H
PA
PD
Chip Erase
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH 55H 555H 10H
Sector Erase
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH 55H
SA 30H
Sector Erase Suspend 1
XXXH
B0H
Sector Erase Resume
1
XXXH
30H
Unlock for chip
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH 55H
555H 20H
protect/unprotect
TABLE 1. SOFTWARE COMMAND DEFINITIONS
Note:
1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to
Table 3)
DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A16 in either state.
4. For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data
is 00H, it means the chip is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register
command sequences. Note that the Erase Suspend
(B0H) and Erase Resume (30H) commands are valid
only while the Sector Erase operation is in progress.
Either of the two reset command sequences will reset
the device(when applicable).
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