FEATURES

· Single power supply 5V operation for read, erase and

program

· Fast access time: 90/120ns
· Low power consumption

- 30mA maximum active current
- 0.2uA typical standby current

· Command register architecture

- Byte Programming (7us typical)
- Sector Erase:32 equal sector with of 64KByte each

· Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically program and verify data at specified
address

· Erase suspend/Erase Resume

- Suspends an erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.

during erase and programming, while maintaining
maximum EPROM compatibility.

MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F016 uses a 5.0V

10% VCC supply to

perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to
100 milliamps on address and data pin from -1V to
VCC + 1V.

GENERAL DESCRIPTION

The MX29F016 is a 16-mega bit Flash memory organized
as 2M bytes of 8 bits. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F016 is packaged in
40-pin TSOP or 44-pin SOP, 48-pin TSOP. It is designed
to be reprogrammed and erased in system or in standard
EPROM programmers.

The standard MX29F016 offers access time as fast as
90ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F016 has separate chip enable (CE) and output
enable (OE ) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F016 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels

· Status Reply

- Data polling & Toggle bit for detection of program
and erase cycle completion.

· Group Sector protect/unprotect for 5V/12V system.
· Group Sector protection

- Hardware sector protect/unprotect method for each
group which consists of two adjacent sectors
- Temporary group sector unprotect allows code
changes in previously locked sectors

· 100,000 minimum erase/program cycles
· Latch-up protected to 100mA from -1V to VCC+1V
· Low VCC write inhibit is equal to or less than 3.2V
· Package type:

- 40-pin TSOP, 44-pin SOP, 48-pin TSOP

· Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

P/N:PM0590

REV. 1.4, NOV. 21, 2002

MX29F016

16M-BIT [2M X 8] CMOS EQUAL SECTOR FLASH MEMORY

P/N:PM0590

REV. 1.4, NOV. 21, 2002

MX29F016

PIN CONFIGURATIONS

40 TSOP (Standard Type) (10mm x 20mm)

SYMBOL

PIN NAME

A0~A20

Address Input

Q0~Q7

8 Data Inputs/Outputs

Chip Enable Input

Write Enable Input

Output Enable Input

RESET

Hardware Reset Pin, Active Low

RY/BY

Read/Busy Output

VCC

+5.0V single power supply

VSS

Device Ground

Pin Not Connected Internally

PIN DESCRIPTION

44 SOP

48 TSOP (Standard Type) (12mm x 20mm)

A19
A18
A17
A16
A15
A14
A13
A12

VCC

RESET

A11
A10

A9
A8
A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

A20
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC
VSS
VSS
Q3
Q2
Q1
Q0
A0
A1
A2
A3

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

MX29F016

NC
NC

A19
A18
A17
A16
A15
A14
A13
A12

VCC

RESET

A11
A10

A9
A8
A7
A6
A5
A4

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

NC
NC
A20
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC
VSS
VSS
Q3
Q2
Q1
Q0
A0
A1
A2
A3
NC
NC

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29F016

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET

A11
A10

A9
A8
A7
A6
A5
A4

NC
NC

A3
A2
A1
A0

Q0
Q1
Q2
Q3

VSS
VSS

VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC

MX29F016

P/N:PM0590

REV. 1.4, NOV. 21, 2002

MX29F016

Group Sector A20 A19 A18 A17 A16 Address Range

Sector

SGA0 SA0

000000h-00FFFFh

SGA0 SA1

010000h-01FFFFh

SGA0 SA2

020000h-02FFFFh

SGA0 SA3

030000h-03FFFFh

SGA1 SA4

040000h-04FFFFh

SGA1 SA5

050000h-05FFFFh

SGA1 SA6

060000h-06FFFFh

SGA1 SA7

070000h-07FFFFh

SGA2 SA8

080000h-08FFFFh

SGA2 SA9

090000h-09FFFFh

SGA2 SA10

0A0000h-0AFFFFh

SGA2 SA11

0B0000h-0BFFFFh

SGA3 SA12

0C0000h-0CFFFFh

SGA3 SA13

0D0000h-0DFFFFh

SGA3 SA14

0E0000h-0EFFFFh

SGA3 SA15

0F0000h-0FFFFFh

SGA4 SA16

100000h-10FFFFh

SGA4 SA17

110000h-11FFFFh

SGA4 SA18

120000h-12FFFFh

SGA4 SA19

130000h-13FFFFh

SGA5 SA20

140000h-14FFFFh

SGA5 SA21

150000h-15FFFFh

SGA5 SA22

160000h-16FFFFh

SGA5 SA23

170000h-17FFFFh

SGA6 SA24

180000h-18FFFFh

SGA6 SA25

190000h-19FFFFh

SGA6 SA26

1A0000h-1AFFFFh

SGA6 SA27

1B0000h-1BFFFFh

SGA7 SA28

1C0000h-1CFFFFh

SGA7 SA29

1D0000h-1DFFFFh

SGA7 SA30

1E0000h-1EFFFFh

SGA7 SA31

1F0000h-1FFFFFh

Legend:SA=Sector Address ; SGA=Sector Group Address
Note:All sectors are 64 Kbytes in size.

MX29F016 SECTOR ADDRESS TABLE

LOGIC SYMBOL

Q0-Q7

RY/BY

A0-A20

RESET

P/N:PM0590

REV. 1.4, NOV. 21, 2002

MX29F016

AUTOMATIC PROGRAMMING

The MX29F016 is byte programmable using the Automatic
Programming algorithm. The Automatic Programming
algorithm makes the external system do not need to have
time out sequence nor to verify the data programmed.
The typical chip programming time at room temperature
of the MX29F016 is less than 15 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 19 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F016 is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the program
verification, and counts the number of sequences. A
status bit similar to DATA polling and a status bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard
microprocessor write timings. The device will

automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, provides the erase verification, and counts the
number of sequences. A status bit toggling between
consecutive read cycles provides feedback to the user
as to the status of the programming operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F016
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX29F016TC-90