1
P/N:PM0578
REV. 2.3,MAR. 26, 2003
MX29F800T/B
8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY
PRELIMINARY
erase operation completion.
Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program
or erase operation completion.
Sector protection
- Sector protect/chip unprotect for 5V/12V system.
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 44-pin SOP
- 48-pin TSOP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
FEATURES
1,048,576 x 8/524,288 x 16 switchable
Single power supply operation
- 5.0V only operation for read, erase and program
operation
Fast access time: 70/90/120ns
Low power consumption
- 50mA maximum active current
- 0.2uA typical standby current
Command register architecture
- Byte/word Programming (7us/12us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
Status Reply
- Data polling & Toggle bit for detection of program and
GENERAL DESCRIPTION
The MX29F800T/B is a 8-mega bit Flash memory or-
ganized as 1M bytes of 8 bits or 512K words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29F800T/B is packaged in 44-pin SOP, 48-pin
TSOP. It is designed to be reprogrammed and erased
in system or in standard EPROM programmers.
The standard MX29F800T/B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29F800T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F800T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29F800T/B uses a 5.0V
10% VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
2
P/N:PM0578
MX29F800T/B
REV. 2.3, MAR. 26, 2003
PIN CONFIGURATIONS
44 SOP(500 mil)
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18
Address Input
Q0~Q14
Data Input/Output
Q15/A-1
Q15(Word mode)/LSB addr(Byte mode)
CE
Chip Enable Input
WE
Write Enable Input
BYTE
Word/Byte Selection input
RESET
Hardware Reset Pin/Sector Protect
Unlock
OE
Output Enable Input
RY/BY
Ready/Busy Output
VCC
Power Supply Pin (+5V)
GND
Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
MX29F800T/B
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29F800T/B
5
P/N:PM0578
MX29F800T/B
REV. 2.3, MAR. 26, 2003
AUTOMATIC PROGRAMMING
The MX29F800T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at
room temperature of the MX29F800T/B is less than 8
seconds.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished
in less than 8 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F800T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes al-
low sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically
programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will au-
tomatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F800T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
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