FEATURES
Regulated voltage range 3.0 to 3.6V write, erase and
read(MX29L1611-75/10/12)
Fast random access/page mode access time: 75/
30ns, 100/30ns, 120/30ns.
Full voltage range 2.7 to 3.6V write, erase and read
(MX29L1611-90)
Fast random access/page mode access time: 90/
35ns
Endurance: 10,000 cycles
Page access depth: 16 bytes/8 words, page address
A0, A1, A2
Sector erase architecture
- 32 equal sectors of 64k bytes each
- Sector erase time: 200ms typical
Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
whole chip with Erase Suspend capability
- Automatically programs and verifies data at specified
addresses
Status Register feature for detection of program or
erase cycle completion
Low VCC write inhibit < 1.8V
Software and hardware data protection
Page program operation
- Internal address and data latches for 128 bytes/64
words per page
- Page programming time: 5ms typical
Low power dissipation
- 50mA active current
- 20uA standby current
Two independently Protected sectors
Industry standard surface mount packaging
- 44 lead SOP, 48 TSOP(I)
GENERAL DESCRIPTION
The MX29L1611 is a 16-mega bit pagemode Flash
memory organized as either 1M wordx16 or 2M bytex8.
The MX29L1611 includes 32 sectors of 64KB(65,536
Bytes or 32,768 words). MXIC's Flash memories offer
the most cost-effective and reliable read/write non-
volatile random access memory and fast page mode
access. The MX29L1611 is packaged 44-pin SOP and
48-TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
The standard MX29L1611 offers access times as fast as
100ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the MX29L1611
has separate chip enable CE, output enable (OE), and
write enable (WE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29L1611 uses a command register to manage this
functionality.
To allow for simple in-system reprogrammability, the
MX29L1611 does not require high input voltages for
programming. Three-volt-only commands determine
the operation of the device. Reading data out of the
device is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 10,000 cycles. The MXIC's cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29L1611 uses a 2.7V~3.6V VCC supply to perform
the Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
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MX29L1611
16M-BIT [2M x 8/1M x 16] CMOS
SINGLE VOLTAGE PAGEMODE FLASH EEPROM
PRELIMINARY
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MX29L1611
PIN CONFIGURATIONS
44 SOP(500mil)
PIN DESCRIPTION
SYMBOL
PIN NAME
A0 - A19
Address Input
Q0 - Q14
Data Input/Output
Q15/A-1
Q15(Word mode)/LSB addr.(Byte
mode)
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
WP*
Sector Write Protect Input
BYTE
Word/Byte Selection Input
VCC
Power Supply
GND
Ground Pin
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
WP
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
MX29L1611
48 TSOP (NORMAL TYPE)
*Only for 44-SOP
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
GND
WE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
NC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29L1611
(Normal Type)
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REV. 2.4, NOV. 06, 2001
MX29L1611
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
COMMAND
INTERFACE
REGISTER
(CIR)
MX29L1611
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y
-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Y-select
Q0-Q15/A-1
Q15/A-1
A0-A19
WE
OE
WP
BYTE
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REV. 2.4, NOV. 06, 2001
MX29L1611
Table1.PIN DESCRIPTIONS
SYMBOL
TYPE
NAME AND FUNCTION
A0 - A19
INPUT
ADDRESS INPUTS: for memory addresses. Addresses are internally
latched during a write cycle.
Q0 - Q7
INPUT/OUTPUT
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs
are disabled.
Q8 - Q14
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.
Outputs array, identifier data in the appropriate read mode; not used for status
register reads. Floated when the chip is de-selected or the outputs are
disabled
Q15/A -1
INPUT/OUTPUT
Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW)
CE
INPUT
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With CE high, the device is deselected and
power consumption reduces to Standby level upon completion of any current
program or erase operations. CE must be low to select the device.
OE
INPUT
OUTPUT ENABLES: Gates the device's data through the output buffers
during a read cycle OE is active low.
WE
INPUT
WRITE ENABLE: Controls writes to the Command Interface Register(CIR).
WE is active low.
WP
INPUT
WRITE PROTECT: Top or Bottom sector can be protected by writing a non-
volatile protect-bit for each sector. When WP is high, all sectors can be
programmed or erased regardless of the state of the protect-bits.
BYTE
INPUT
BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input
or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high
and low byte. BYTE high places the device in x16 mode, and turns off the Q15/
A-1 input buffer. Address A0, then becomes the lowest order address.
VCC
DEVICE POWER SUPPLY(3.0V~3.6V for MX29L1611-75/10/12 ; 2.7V~3.6V
for MX29L1611-90)
GND
GROUND
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MX29L1611
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Notes
CE
OE
WE
A0
A1
A9
Q0-Q7
Q8-Q14
Q15/A-1
Read
1
VIL
VIL
VIH
X
X
X
DOUT
HighZ
VIL/VIH
Output Disable
1
VIL
VIH
VIH
X
X
X
High Z
High Z
X
Standby
1
VIH
X
X
X
X
X
High Z
HIgh Z
X
Manufacturer ID
2,4
VIL
VIL
VIH
VIL
VIL
VID
C2H
High Z
VIL
Device ID
2,4
VIL
VIL
VIH
VIH
VIL
VID
F8H
High Z
VIL
Write
1,3
VIL
VIH
VIL
X
X
X
DIN
High Z
VIL/VIH
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Notes
CE
OE
WE
A0
A1
A9
Q0-Q7
Q8-Q14
Q15/A-1
Read
1
VIL
VIL
VIH
X
X
X
DOUT
DOUT
DOUT
Output Disable
1
VIL
VIH
VIH
X
X
X
High Z
High Z
HighZ
Standby
1
VIH
X
X
X
X
X
High Z
HIgh Z
HighZ
Manufacturer ID
2,4
VIL
VIL
VIH
VIL
VIL
VID
C2H
00H
0B
Device ID
2,4
VIL
VIL
VIH
VIH
VIL
VID
F8H
00H
0B
Write
1,3
VIL
VIH
VIL
X
X
X
DIN
DIN
DIN
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and
with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4)
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully
completed through proper command sequence.
4. VID = 11.5V- 12.5V.
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