P/N:PM0866

REV. 3.7, APR. 23, 2003

MX29LV160T/B & MX29LV160AT/AB

16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY

· Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or
erase operation completion.

· Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.

· CFI (Common Flash Interface) compliant (for

MX29LV160AT/AB)
- Flash device parameters stored on the device and
provide the host system to access

· 100,000 minimum erase/program cycles
· Latch-up protected to 100mA from -1V to VCC+1V
· Boot Sector Architecture

- T = Top Boot Sector
- B = Bottom Boot Sector

· Low VCC write inhibit is equal to or less than 1.4V
· Package type:

- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP (8x13mm:for MX29LV160T/B; 6x8mm:
for MX29LV160AT/AB)

· Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

FEATURES

· Extended single - supply voltage range 2.7V to 3.6V
· 2,097,152 x 8/1,048,576 x 16 switchable
· Single power supply operation

- 3.0V only operation for read, erase and program
operation

· Fast access time: 70/90ns
· Low power consumption

- 30mA maximum active current
- 0.2uA typical standby current

· Command register architecture

- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)

· Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address

· Erase Suspend/Erase Resume

- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.

· Status Reply

- Data polling & Toggle bit for detection of program and
erase operation completion.

GENERAL DESCRIPTION

The MX29LV160T/B & MX29LV160AT/AB is a 16-mega
bit Flash memory organized as 2M bytes of 8 bits or 1M
words of 16 bits. MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX29LV160T/B & MX29LV160AT/
AB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball
CSP. It is designed to be reprogrammed and erased in
system or in standard EPROM programmers.

The standard MX29LV160T/B & MX29LV160AT/AB of-
fers access time as fast as 70ns, allowing operation of
high-speed microprocessors without wait states. To elimi-
nate bus contention, the MX29LV160T/B &
MX29LV160AT/AB has separate chip enable (CE) and
output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV160T/B & MX29LV160AT/AB uses a command
register to manage this functionality. The command reg-
ister allows for 100% TTL level control inputs and fixed

power supply levels during erase and programming, while
maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV160T/B & MX29LV160AT/AB uses a
2.7V~3.6V VCC supply to perform the High Reliability
Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

Part Name

Difference

MX29LV160T/B

1) Without CFI compliant
2)CSP dimension:8x13mm

MX29LV160AT/AB

1) With CFI compliant
2)CSP dimension:6x8mm

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

PIN CONFIGURATIONS

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A19

Address Input

Q0~Q14

Data Input/Output

Q15/A-1

Q15(Word mode)/LSB addr(Byte mode)

Chip Enable Input

Write Enable Input

BYTE

Word/Byte Selection input

RESET

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

RY/BY

Ready/Busy Output

VCC

Power Supply Pin (2.7V~3.6V)

GND

Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

44 SOP(500 mil)

A13

A12

A14

A15

A16

BYTE

Q15/A-1 GND

A10

A11

Q14

Q13

RESET

A19

Q12

VCC

RY/BY

A18

Q10

Q11

A17

GND

48-Ball CSP (Ball Pitch=0.8mm) Top View, Balls Facing Down (8x13mm for MX29LV160T/B; 6x8mm for
MX29LV160AT/AB)

A15
A14
A13
A12
A11
A10

A9
A8

A19

RESET

NC
NC

RY/BY

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29LV160T/B, MX29LV160AT/AB

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

GND

Q0
Q8
Q1
Q9
Q2

Q10

Q11

WE
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

MX29L

V160T/B

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

BLOCK STRUCTURE

Sector Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode(x8)

Word Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12

SA0

64Kbytes

32Kwords

000000-00FFFF

00000-07FFF

SA1

64Kbytes

32Kwords

010000-01FFFF

08000-0FFFF

SA2

64Kbytes

32Kwords

020000-02FFFF

10000-17FFF

SA3

64Kbytes

32Kwords

030000-03FFFF

18000-1FFFF

SA4

64Kbytes

32Kwords

040000-04FFFF

20000-27FFF

SA5

64Kbytes

32Kwords

050000-05FFFF

28000-2FFFF

SA6

64Kbytes

32Kwords

060000-06FFFF

30000-37FFF

SA7

64Kbytes

32Kwords

070000-07FFFF

38000-3FFFF

SA8

64Kbytes

32Kwords

080000-08FFFF

40000-47FFF

SA9

64Kbytes

32Kwords

090000-09FFFF

48000-4FFFF

SA10

64Kbytes

32Kwords

0A0000-0AFFFF 50000-57FFF

SA11

64Kbytes

32Kwords

0B0000-0BFFFF 58000-5FFFF

SA12

64Kbytes

32Kwords

0C0000-0CFFFF 60000-67FFF

SA13

64Kbytes

32Kwords

0D0000-0DFFFF 68000-6FFFF

SA14

64Kbytes

32Kwords

0E0000-0EFFFF 70000-77FFF

SA15

64Kbytes

32Kwords

0F0000-0FFFFF 78000-7FFFF

SA16

64Kbytes

32Kwords

100000-10FFFF

80000-87FFF

SA17

64Kbytes

32Kwords

110000-11FFFF

88000-8FFFF

SA18

64Kbytes

32Kwords

120000-12FFFF

90000-97FFF

SA19

64Kbytes

32Kwords

130000-13FFFF

98000-9FFFF

SA20

64Kbytes

32Kwords

140000-14FFFF

A0000-A7FFF

SA21

64Kbytes

32Kwords

150000-15FFFF

A8000-AFFFF

SA22

64Kbytes

32Kwords

160000-16FFFF

B0000-B7FFF

SA23

64Kbytes

32Kwords

170000-17FFFF

B8000-BFFFF

SA24

64Kbytes

32Kwords

180000-18FFFF

C0000-C7FFF

SA25

64Kbytes

32Kwords

190000-19FFFF

C8000-CFFFF

SA26

64Kbytes

32Kwords

1A0000-1AFFFF D0000-D7FFF

SA27

64Kbytes

32Kwords

1B0000-1BFFFF D8000-DFFFF

SA28

64Kbytes

32Kwords

1C0000-1CFFFF E0000-E7FFF

SA29

64Kbytes

32Kwords

1D0000-1DFFFF E8000-EFFFF

SA30

64Kbytes

32Kwords

1E0000-1EFFFF F0000-F7FFF

SA31

32Kbytes

16Kwords

1F0000-1F7FFF

F8000-FBFFF

SA32

8Kbytes

4Kwords

1F8000-1F9FFF

FC000-FCFFF

SA33

8Kbytes

4Kwords

1FA000-1FBFFF FD000-FDFFF

SA34

16Kbytes

8Kwords

1FC000-1FFFFF FE000-FFFFF

Table 1: MX29LV160T & MX29LV160AT SECTOR ARCHITECTURE

Note: Byte mode: address range A19:A-1, word mode:address range A19:A0.

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

Sector Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode (x8) Word Mode (x16) A19 A18 A17 A16 A15 A14 A13 A12

SA0

16Kbytes

8Kwords

000000-003FFF

00000-01FFF

SA1

8Kbytes

4Kwords

004000-005FFF

02000-02FFF

SA2

8Kbytes

4Kwords

006000-007FFF

03000-03FFF

SA3

32Kbytes

16Kwords

008000-00FFFF

04000-07FFF

SA4

64Kbytes

32Kwords

010000-01FFFF

08000-0FFFF

SA5

64Kbytes

32Kwords

020000-02FFFF

10000-17FFF

SA6

64Kbytes

32Kwords

030000-03FFFF

18000-1FFFF

SA7

64Kbytes

32Kwords

040000-04FFFF

20000-27FFF

SA8

64Kbytes

32Kwords

050000-05FFFF

28000-2FFFF

SA9

64Kbytes

32Kwords

060000-06FFFF

30000-37FFF

SA10

64Kbytes

32Kwords

070000-07FFFF

38000-3FFFF

SA11

64Kbytes

32Kwords

080000-08FFFF

40000-47FFF

SA12

64Kbytes

32Kwords

090000-09FFFF

48000-4FFFF

SA13

64Kbytes

32Kwords

0A0000-0AFFFF 50000-57FFF

SA14

64Kbytes

32Kwords

0B0000-0BFFFF 58000-5FFFF

SA15

64Kbytes

32Kwords

0C0000-0CFFFF 60000-67FFF

SA16

64Kbytes

32Kwords

0D0000-0DFFFF 68000-6FFFF

SA17

64Kbytes

32Kwords

0E0000-0EFFFF 70000-77FFF

SA18

64Kbytes

32Kwords

0F0000-0FFFFF 78000-7FFFF

SA19

64Kbytes

32Kwords

100000-10FFFF

80000-87FFF

SA20

64Kbytes

32Kwords

110000-11FFFF

88000-8FFFF

SA21

64Kbytes

32Kwords

120000-12FFFF

90000-97FFF

SA22

64Kbytes

32Kwords

130000-13FFFF

98000-9FFFF

SA23

64Kbytes

32Kwords

140000-14FFFF

A0000-A7FFF

SA24

64Kbytes

32Kwords

150000-15FFFF

A8000-AFFFF

SA25

64Kbytes

32Kwords

160000-16FFFF

B0000-B7FFF

SA26

64Kbytes

32Kwords

170000-17FFFF

B8000-BFFFF

SA27

64Kbytes

32Kwords

180000-18FFFF

C0000-C7FFF

SA28

64Kbytes

32Kwords

190000-19FFFF

C8000-CFFFF

SA29

64Kbytes

32Kwords

1A0000-1AFFFF D0000-D7FFF

SA30

64Kbytes

32Kwords

1B0000-1BFFFF D8000-DFFFF

SA31

64Kbytes

32Kwords

1C0000-1CFFFF E0000-E7FFF

SA32

64Kbytes

32Kwords

1D0000-1DFFFF E8000-EFFFF

SA33

64Kbytes

32Kwords

1E0000-1EFFFF F0000-FFFFF

SA34

64Kbytes

32Kwords

1F0000-1FFFFF F8000-FFFFF

Table 2: MX29LV160B & MX29LV160AB SECTOR ARCHITECTURE

Note: Byte mode:address range A19:A-1, word mode:address range A19:A0.

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

AUTOMATIC PROGRAMMING

The MX29LV160T/B & MX29LV160AT/AB is byte/word
programmable using the Automatic Programming algo-
rithm. The Automatic Programming algorithm makes
the external system do not need to have time out se-
quence nor to verify the data programmed. The typical
chip programming time at room temperature of the
MX29LV160T/B & MX29LV160AT/AB is less than 18 sec
(byte)/12 sec (word).

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, table 7, for
more information on these status bits.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29LV160T/B & MX29LV160AT/AB is sector(s)
erasable using MXIC's Auto Sector Erase algorithm. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device. An erase operation
can erase one sector, multiple sectors, or the entire de-
vice.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV160T/B &
MX29LV160AT/AB electrically erases all bits simulta-
neously using Fowler-Nordheim tunneling. The bytes are
programmed by using the EPROM programming mecha-
nism of hot electron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

AUTOMATIC SELECT

The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0. This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9. Other address pin A6, A1 and A0 as referring to
Table 3. In addition, to access the automatic select codes
in-system, the host can issue the automatic select com-

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

A19

A11

Description

Mode

WE RESET

Q15~Q0

A12

A10

Read Silicon ID

VID

C2H

Manufacture Code

Device ID

Word

VID

22C4H

(Top Boot Block)

Byte

VID

XXC4H

Device ID

Word

VID

2249H

(Bottom Boot Block) Byte

VID

XX49H

XX01H

Sector Protection

VID

(protected)

Verification

XX00H
(unprotected)

TABLE 3. MX29LV160T/B & MX29LV160AT/AB AUTO SELECT MODE BUS OPERATION (A9=VID)

NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High

mand through the command register without requiring
VID, as shown in table 5.

To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in Table 3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE ( for MX29LV160AT/
AB)

MX29LV160AT/AB is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating param-
eters and configuration. Two commands are required in
CFI mode. Query command of CFI mode is placed first,
then the Reset command exits CFI mode. These are

described in Table 4.

The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Automatic Select mode; however, it
is ignored otherwise.

The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, or Automatic Se-
lect mode. The command is valid only when the device
is in the CFI mode.

Table 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Query-unique ASCII string "QRY"

0051

0052

0059

Primary vendor command set and control interface ID code

0002

0000

Address for primary algorithm extended query table

0040

0000

Alternate vendor command set and control interface ID code (none)

0000

Address for secondary algorithm extended query table (none)

0000

Table 4-2. CFI Mode: System Interface Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

VCC supply, minimum (2.7V)

0027

VCC supply, maximum (3.6V)

0036

VPP supply, minimum (none)

0000

VPP supply, maximum (none)

0000

Typical timeout for single word/byte write (2

us)

0004

Typical timeout for Minimum size buffer write (2

us) (not supported)

0000

Typical timeout for individual sector erase (2

ms)

000A

Typical timeout for full chip erase (2

ms)

0000

Maximum timeout for single word/byte write times (2

X Typ)

0005

Maximum timeout for buffer write times (2

X Typ)

0000

Maximum timeout for individual sector erase times (2

X Typ)

0004

Maximum timeout for full chip erase times (not supported)

0000

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

Table 4-3. CFI Mode: Device Geometry Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Device size (2

bytes)

0015

Flash device interface code (x8/x16 async.)

0002

0000

Maximum number of bytes in multi-byte write (not supported)

0000

Number of erase sector regions

0004

Erase sector region 1 information (refer to the CFI publication 100)

0000

0040

0000

Erase sector region 2 information

0001

0000

0020

0000

Erase sector region 3 information

0000

0080

0000

Erase sector region 4 information

001E

0000

0001

Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

(All values in these tables are in hexadecimal)

Description

Address

Data

(Byte Mode)

(Word Mode)

Query-unique ASCII string "PRI"

0050

0052

0049

Major version number, ASCII

0031

Minor version number, ASCII

0030

Address sensitive unlock (0=required, 1= not required)

0000

Erase suspend (2= to read and write)

0002

Sector protect (N= # of sectors/group)

0001

Temporary sector unprotect (1=supported)

0001

Sector protect/chip unprotect scheme

0004

Simultaneous R/W operation (0=not supported)

0000

Burst mode type (0=not supported)

0000

Page mode type (0=not supported)

0000

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

in the improper sequence will reset the device to the
read mode. Table 5 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them

First Bus

Second Bus

Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Cycle Addr

Data Addr

Data

Addr

Data Addr

Data

Addr

Data Addr

Data

Reset

XXXH F0H

Read

Read Silicon ID

Word

555H AAH 2AAH

55H

555H

90H ADI

DDI

Byte

AAAH AAH 555H

55H

AAAH

90H ADI

DDI

Sector Protect

Word

555H AAH 2AAH

55H

555H

90H (SA)

XX00H

Verify

x02H

XX01H

Byte

AAAH AAH 555H

55H

AAAH

90H (SA)

00H

x04H

01H

Program

Word

555H AAH 2AAH

55H

555H

A0H PA

Byte

AAAH AAH 555H

55H

AAAH

A0H PA

Chip Erase

Word

555H AAH 2AAH

55H

555H

80H 555H

AAH

2AAH 55H

555H 10H

Byte

AAAH AAH 555H

55H

AAAH

80H AAAH AAH

555H

55H

AAAH 10H

Sector Erase

Word

555H AAH 2AAH

55H

555H

80H 555H

AAH

2AAH 55H

30H

Byte

AAAH AAH 555H

55H

AAAH

80H AAAH AAH

555H

55H

30H

Sector Erase Suspend

XXXH B0H

Sector Erase Resume

XXXH 30H

CFI Query (for

Word

555H 98

29LV160AT/AB) Byte

AAAH

TABLE 5. MX29LV160T/B & MX29LV160AT/AB COMMAND DEFINITIONS

Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read. RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A19=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A19 in either state.
4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

5. Any number of CFI data read cycles are permitted.

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

ADDRESS

Q8~Q15

DESCRIPTION

WE RESET A19 A11 A9 A8

A6 A5 A1

Q0~Q7

BYTE

A12 A10

=VIH

=VIL

Read

AIN

Dout

=High Z

DQ15=A-1

Write

AIN

DIN(3)

DIN

Reset

High Z

Temporary sector unlock

VID

AIN

DIN

High Z

Output Disable

High Z

Standby

Vcc

High Z

0.3V

Sector Protect

VID

DIN

Chip Unprotect

VID

DIN

Sector Protection Verify

VID

CODE(5)

TABLE 6. MX29LV160T/B & MX29LV160AT/AB BUS OPERATION

NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. VID is the high voltage, 11.5V to 12.5V.
3. Refer to Table 5 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

6. A19~A12=Sector address for sector protect.
7.The sector protect and chip unprotect functions may also be implemented via programming equipment.

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REV. 3.7, APR. 23, 2003

REQUIREMENTS FOR READING ARRAY
DATA

To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power control
and selects the device. OE is the output control and
gates array data to the output pins. WE should remain at
VIH.

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read
access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of
memory, the system must drive WE and CE to VIL, and
OE to VIH.

An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 1 and Table 2 indicate the
address space that each sector occupies. A "sector ad-
dress" consists of the address bits required to uniquely
select a sector. The Writing specific address and data
commands or sequences into the command register ini-
tiates device operations. Table 5 defines the valid regis-
ter command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data. Section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.

After the system writes the "read silicon-ID" and "sector
protect verify" command sequence, the device enters
the "read silicon-ID" and "sector protect verify" mode.
The system can then read "read silicon-ID" and "sector
protect verify" codes from the internal register (which is
separate from the memory array) on Q7-Q0. Standard
read cycle timings apply in this mode. Refer to the "read
silicon-ID" and "sector protect verify" Mode and "read
silicon-ID" and "sector protect verify" Command Se-
quence section for more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE and RESET, the device
enter CMOS Standby with both pins held at Vcc

0.3V.

If CE and RESET are held at VIH, but not within the
range of VCC

0.3V, the device will still be in the standby

mode, but the standby current will be larger. During Auto
Algorithm operation, Vcc active current (ICC2) is required
even CE = "H" until the operation is completed. The de-
vice can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from
the devices are disabled. This will cause the output pins
to be in a high impedance state.

RESET OPERATION

The RESET pin provides a hardware method of reset-
ting the device to reading array data. When the RESET
pin is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write com-
mands for the duration of the RESET pulse. The device
also resets the internal state machine to reading array
data. The operation that was interrupted should be re-
initiated once the device is ready to accept another com-
mand sequence, to ensure data integrity.

Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS±0.3V, the standby current will be
greater.

The RESET pin may be tied to system reset circuitry. A
system reset would that also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.

If RESET is asserted during a program or erase opera-

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REV. 3.7, APR. 23, 2003

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.

The MX29LV160T/B & MX29LV160AT/AB contains a Sili-
con-ID-Read operation to supple traditional PROM pro-
gramming methodology. The operation is initiated by
writing the read silicon ID command sequence into the
command register. Following the command write, a read
cycle with A1=VIL, A0=VIL retrieves the manufacturer
code of C2H/00C2H. A read cycle with A1=VIL, A0=VIH
returns the device code of C4H/22C4H for MX29LV160T/
AT, 49H/2249H for MX29LV160B/AB.

The system must write the reset command to exit the
"Silicon-ID Read Command" code.

AUTOMATIC CHIP ERASE COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.

The device does not require the system to entirely pre-
program prior to executing the Automatic Chip Erase.
Upon executing the Automatic Chip Erase, the device
will automatically program and verify the entire memory
for an all-zero data pattern. When the device is auto-
matically verified to contain an all-zero pattern, a self-
timed chip erase and verify begin. The erase and verify
operations are completed when the data on Q7 is "1" at
which time the device returns to the Read mode. The
system is not required to provide any control or timing
during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1" (see Table 8), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when either the data
on Q7 is "1" at which time the device returns to the
Read mode or the data on Q6 stops toggling for two
consecutive read cycles at which time the device re-
turns to the Read mode.

tion, the RY/BY pin remains a "0" (busy) until the inter-
nal reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms). The system can
thus monitor RY/BY to determine whether the reset op-
eration is complete. If RESET is asserted when a pro-
gram or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The sys-
tem can read data tRH after the RESET pin returns to
VIH.

Refer to the AC Characteristics tables for RESET
parameters and to Figure 22 for the timing diagram.

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REV. 3.7, APR. 23, 2003

READING ARRAY DATA

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system
can read array data using the standard read timings,
except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See erase Suspend/Erase
Resume Commands" for more information on this mode.
The system

must

issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or
while in the "read silicon-ID" and "sector protect verify"
mode. See the "Reset Command" section, next.

RESET COMMAND

Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.

The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.

The reset command may be written between the
sequence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase
Suspend mode). Once programming begins, however,
the device ignores reset commands until the operation
is complete.

The reset command may be written between the
sequence cycles in an Automatic Select command
sequence. Once in the Automatic Select mode, the reset
command

must

be written to return to reading array data

(also applies to Automatic Select during Erase Suspend).

If Q5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).

Pins

Q15~Q8 Q7

Q2 Q1

Code(Hex)

Manufacturer code

Word

VIL

00H

00C2H

Byte

VIL

C2H

Device code

Word

VIH

VIL

22H

22C4H

for MX29LV160(A)T

Byte

VIH

VIL

C4H

Device code

Word

VIH

VIL

22H

2249H

for MX29LV160(A)B

Byte

VIH

VIL

49H

Sector Protection

Word

VIH

01H (Protected)

Verification

Byte

VIH

00H (Unprotected)

TABLE 7. SILICON ID CODE

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REV. 3.7, APR. 23, 2003

SECTOR ERASE COMMANDS

The device does not require the system to entirely pre-
program prior to executing the Automatic Sector Erase
Set-up command and Automatic Sector Erase com-
mand. Upon executing the Automatic Sector Erase com-
mand, the device will automatically program and verify
the sector(s) memory for an all-zero data pattern. The
system is not required to provide any control or timing
during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when either the data on Q7 is "1" at which time the de-
vice returns to the Read mode or the data on Q6 stops
toggling for two consecutive read cycles at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of WE
or CE, whichever happens later, while the command
(data) is latched on the rising edge of WE or CE, which-
ever happens first. Sector addresses selected are
loaded into internal register on the sixth falling edge of
WE or CE, whichever happens later. Each successive
sector load cycle started by the falling edge of WE or
CE, whichever happens later must begin within 50us
from the rising edge of the preceding WE or CE, which-
ever happens first. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase (30H) or Erase Suspend (B0H) during
the time-out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend Com-

mand is issued during the sector erase operation, the
device requires a maximum 20us to suspend the sector
erase operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to re-
spond to Erase Resume, program data to , or read data
from any sector not selected for erasure. The system
can use Q7 or Q6 and Q2 together, to determine if a
sector is actively erasing or is erase-suspend.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing. However,
for MX29LV160T/B, a 10ms time delay must be required
after the erase resume command, if the system imple-
ments a endless erase suspend/resume loop, or the
number of erase suspend/resume is exceeded 1024
times. The erase times will be expended if the erase
behavior always be suspended. (Please refer to MXIC
Flash Application Note for details.) Please note that the
above 10ms time delay is not necessary for
MX29LV160AT/AB.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is

not

required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 5 shows the address

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REV. 3.7, APR. 23, 2003

and data requirements for the byte program command
sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, Q6, or RY/BY. See "Write Operation Status" for
information on these status bits.

Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte/Word Program command sequence
should be reinitiated once the device has reset to reading
array data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may cause the
device to set Q5 to "1", or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".

WRITE OPERATION STATUS

The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY. Table 8 and the following subsections describe the
functions of these bits. Q7, RY/BY, and Q6 each offer a
method for determining whether a program or erase op-
eration is complete or in progress. These three bits are
discussed first.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend. Data
Polling is valid after the rising edge of the final WE pulse
in the program or erase command sequence.

During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to programming dur-
ing Erase Suspend. When the Automatic Program algo-
rithm is complete, the device outputs the datum pro-
grammed to Q7. The system must provide the program

address to read valid status information on Q7. If a pro-
gram address falls within a protected sector, Data Poll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.

During the Automatic Erase algorithm, Data Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, or if the device enters the Erase Sus-
pend mode, Data Polling produces a "1" on Q7. This is
analogous to the complement/true datum output de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement," or "0"." The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
able (OE) is asserted low.

RY/BY : Ready/Busy

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence. Since RY/BY
is an open-drain output, several RY/BY pins can be tied
together in parallel with a pull-up resistor to Vcc.

If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the de-
vice is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.

Table 8 shows the outputs for RY/BY during write opera-
tion.

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During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con-
trol the read cycles. When the operation is complete, Q6
stops toggling.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.

Table 8 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE or CE, whichever

happens first, in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 7 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.

Q5 : Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence (prior to the
program or erase operation), and during the sector time-
out.

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REV. 3.7, APR. 23, 2003

ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data Polling and Toggle Bit
are the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

Status

RY/BY

(Note1)

(Note2)

Byte/Word Program in Auto Program Algorithm

Toggle

N/A

Toggle

Auto Erase Algorithm

Toggle

Erase Suspend Read

N/A Toggle

(Erase Suspended Sector)

Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

N/A

Byte/Word Program in Auto Program Algorithm

Toggle

N/A

Toggle

Exceeded
Time Limits Auto Erase Algorithm

Toggle

Erase Suspend Program

Toggle

N/A

Table 8. WRITE OPERATION STATUS

Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5: Exceeded Timing Limits " for more information.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.

If this time-out condition occurs during the byte/word
programming operation, it specifies that the entire sec-
tor containing that byte/word is bad and this sector may
not be reused, (other sectors are still functional and can
be reused).

The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.

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REV. 3.7, APR. 23, 2003

POW

ER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.

POWER-UP SEQUENCE

The MX29LV160T/B & MX29LV160AT/AB powers up in
the Read only mode. In addition, the memory contents
may only be altered after successful completion of the
predefined command sequences.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously
protected sector to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET pin to VID (11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin. All the previously protected sectors are pro-
tected again.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

DATA PROTECTION

The MX29LV160T/B & MX29LV160AT/AB is designed
to offer protection against accidental erasure or program-
ming caused by spurious system level signals that may
exist during power transition. During power up the de-
vice automatically resets the state machine in the Read
mode. In addition, with its control register architecture,
alteration of the memory contents only occurs after suc-
cessful completion of specific command sequences. The
device also incorporates several features to prevent in-
advertent write cycles resulting from VCC power-up and
power-down transition or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on OE, CE or WE
will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

SECTOR PROTECTION

The MX29LV160T/B & MX29LV160AT/AB features hard-
ware sector protection. This feature will disable both
program and erase operations for these sectors pro-
tected. To activate this mode, the programming equip-
ment must force VID on address pin A9 and OE (sug-
gest VID = 12V). Programming of the protection cir-
cuitry begins on the falling edge of the WE pulse and is
terminated on the rising edge. Please refer to sector pro-
tect algorithm and waveform.

To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE and OE at VIL and WE at VIH). When A1=VIH,
A0=VIL, A6=VIL, it will produce a logical "1" code at
device output Q0 for a protected sector. Otherwise the
device will produce 00H for the unprotected sector. In
this mode, the addresses, except for A1, are don't care.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes. (Read Silicon ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

CHIP UNPROTECT

The MX29LV160T/B & MX29LV160AT/AB also features
the chip unprotect mode, so that all sectors are unprotected
after chip unprotect is completed to incorporate any
changes in the code. It is recommended to protect all
sectors before activating chip unprotect mode.

To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.
Refer to chip unprotect algorithm and waveform for the
chip unprotect algorithm. The unprotection mechanism
begins on the falling edge of the WE pulse and is
terminated on the rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

a logical "1" at Q0 for the protected sector.

The system must write the reset command to exit the
"Silicon-ID Read Command" code.

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . ..... -65

C to +150

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65

C to +125

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE, and

RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may over-
shoot to VCC +2.0 V for periods up to 20 ns.

2. Minimum DC input voltage on pins A9, OE, and

RESET is -0.5 V. During voltage transitions, A9, OE,
and RESET may overshoot VSS to -2.0 V for periods
of up to 20 ns. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be
greater than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (T

). . . . . . . . . . . . 0

C to +70

Industrial (I) Devices

Ambient Temperature (T

). . . . . . . . . . -40

C to +85

Supply Voltages

for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN1

Input Capacitance

7.5

VIN = 0V

CIN2

Control Pin Capacitance

7.5

VIN = 0V

COUT

Output Capacitance

8.5

VOUT = 0V

NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

Symbol

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

VIN = VSS to VCC, VCC=VCC max

ILIT

A9 Input Leakage Current

VCC=VCC max; A9=12.5V

ILO

Output Leakage Current

VOUT = VSS to VCC, VCC=VCC max

ICC1

VCC Active Read Current

CE=VIL, OE=VIH

@5MHz

(Byte Mode)

@1MHz

CE=VIL, OE=VIH

@5MHz

(Word Mode)

@1MHz

ICC2

VCC Active write Current

CE=VIL, OE=VIH, WE=VIL

ICC3

VCC Standby Current

0.2

CE; RESET=VCC

0.3V

ICC4

VCC Standby Current

0.2

RESET=VSS

0.3V

During Reset (See Conditions)

ICC5

Automatic sleep mode

0.2

VIH=VCC

0.3V;VIL=VSS

0.3V

VIL

Input Low Voltage (Note 1)

-0.5

0.8

VIH

Input High Voltage

0.7xVCC

VCC+ 0.3

VID

Voltage for Automatic

Select and Temporary

11.5

12.5

VCC=3.3V

Sector Unprotect

VOL

Output Low Voltage

0.45

IOL = 4.0mA, VCC= VCC min

VOH1

Output High Voltage (TTL)

0.85xVCC

IOH = -2mA, VCC=VCC min

VOH2

Output High Voltage

VCC-0.4

IOH = -100uA, VCC min

(CMOS)

VLKO

Low VCC Lock-out

1.4

2.1

Voltage

Table 9. DC CHARACTERISTICS

TA = -40

C TO 85

C, VCC = 2.7V~3.6V

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

29LV160(A)T/B-70

29LV160(A)T/B-90

Symbol PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT CONDITIONS

tRC

Read Cycle Time (Note 1)

tACC

Address to Output Delay

CE=OE=VIL

tCE

CE to Output Delay

OE=VIL

tOE

OE to Output Delay

CE=VIL

tDF

OE High to Output Float (Note2)

CE=VIL

tOEH

Output Enable Read

Hold Time

Toggle and Data Polling 10

tOH

Address to Output hold

CE=OE=VIL

NOTE:

1. Not 100% tested.
2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

· Input pulse levels: 0V/3.0V.
· Input rise and fall times is equal to or less than 5ns.
· Output load: 1 TTL gate + 100pF (Including scope and

jig), for 29LV160(A)T/B-90. 1 TTL gate + 30pF (Includ-
ing scope and jig) for 29LV160(A)T/B-70 .

· Reference levels for measuring timing: 1.5V.

AC CHARACTERISTICS

TA = -40

C to 85

C, VCC = 2.7V~3.6V

Table 10. READ OPERATIONS

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

29LV160(A)T/B-70

29LV160(A)T/B-90

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tWC

Write Cycle Time (Note 1)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tOES

Output Enable Setup Time

tGHWL

Read Recovery Time Before Write

(OE High to WE Low)

tCS

CE Setup Time

tCH

CE Hold Time

tWP

Write Pulse Width

tWPH

Write Pulse Width High

tWHWH1

Programming Operation (Note 2)

9/11(typ.)

(Byte/Word program time)

tWHWH2

Sector Erase Operation (Note 2)

0.7(typ.)

sec

tVCS

VCC Setup Time (Note 1)

tRB

Recovery Time from RY/BY

tBUSY

Sector Erase Valid to RY/BY Delay

Chip Erase Valid to RY/BY Delay

Program Valid to RY/BY Delay

tWPP1

Write pulse width for sector

100ns

10us(typ.) 100ns

10us(typ.)

protect (A9, OE Control)

tWPP2

Write pulse width for sector

100ns

12ms(typ.) 100ns

12ms(typ.)

unprotect (A9, OE Control)

tVLHT

Voltage transition time

tOESP

OE setup time to WE active

NOTES:

1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

Table 11. Erase/Program Operations

AC CHARACTERISTICS

TA = -40

C to 85

C, VCC = 2.7V~3.6V

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

29LV160(A)T/B-70

29LV160(A)T/B-90

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tWC

Write Cycle Time (Note 1)

tAS

Address Setup Time

tAH

Address Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tOES

Output Enable Setup Time

tGHEL

Read Recovery Time Before Write

tWS

WE Setup Time

tWH

WE Hold Time

tCP

CE Pulse Width

tCPH

CE Pulse Width High

tWHWH1

Programming

Byte

9(Typ.)

Operation(note2)

Word

11(Typ.)

tWHWH2

Sector Erase Operation (note2)

0.7(Typ.)

sec

NOTE:

1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

AC CHARACTERISTICS

TA = -40

C to 85

C, VCC = 2.7V~3.6V

Table 12. Alternate CE Controlled Erase/Program Operations

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

AUTOMATIC PROGRAMMING TIMING WAVEFORM

Figure 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tion can be verified by DATA polling or toggle bit check-

ing after automatic programming starts. Device outputs
DATA during programming and DATA after programming
on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,
timing waveform)

tWC

Address

A0h

555h

Status

DOUT

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

tAS

tAH

tGHWL

tCH

tWP

tDS

tDH

tWHWH1

Read Status Data (last two cycle)

Program Command Sequence(last two cycle)

tBUSY

tRB

tCS

tWPH

tVCS

Data

RY/BY

VCC

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT

PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX29LV160TMC-70

44 Pin SOP

MX29LV160BMC-70

44 Pin SOP

MX29LV160TMC-90

44 Pin SOP

MX29LV160BMC-90

44 Pin SOP

MX29LV160TTC-70

48 Pin TSOP

(Normal Type)

MX29LV160BTC-70

48 Pin TSOP

(Normal Type)

MX29LV160TTC-90

48 Pin TSOP

(Normal Type)

MX29LV160BTC-90

48 Pin TSOP

(Normal Type)

MX29LV160TTI-70

48 Pin TSOP

(Normal Type)

MX29LV160BTI-70

48 Pin TSOP

(Normal Type)

MX29LV160TTI-90

48 Pin TSOP

(Normal Type)

MX29LV160BTI-90

48 Pin TSOP

(Normal Type)

MX29LV160TXBC-70

48 Ball CSP

MX29LV160BXBC-70

48 Ball CSP

MX29LV160TXBC-90

48 Ball CSP

MX29LV160BXBC-90

48 Ball CSP

MX29LV160TXBI-70

48 Ball CSP

MX29LV160BXBI-70

48 Ball CSP

MX29LV160TXBI-90

48 Ball CSP

MX29LV160BXBI-90

48 Ball CSP

MX29LV160ATTC-70

48 Pin TSOP

(Normal Type)

MX29LV160ABTC-70

48 Pin TSOP

(Normal Type)

MX29LV160ATTC-90

48 Pin TSOP

(Normal Type)

MX29LV160ABTC-90

48 Pin TSOP

(Normal Type)

ORDERING INFORMATION

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT

PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX29LV160ATTI-70

48 Pin TSOP

(Normal Type)

MX29LV160ABTI-70

48 Pin TSOP

(Normal Type)

MX29LV160ATTI-90

48 Pin TSOP

(Normal Type)

MX29LV160ABTI-90

48 Pin TSOP

(Normal Type)

MX29LV160ATXBC-70

48 Ball CSP

(ball size:0.3mm)

MX29LV160ABXBC-70

48 Ball CSP

(ball size:0.3mm)

MX29LV160ATXEC-70

48 Ball CSP

(ball size:0.4mm)

MX29LV160ABXEC-70

48 Ball CSP

(ball size:0.4mm)

MX29LV160ATXBC-90

48 Ball CSP

(ball size:0.3mm)

MX29LV160ABXBC-90

48 Ball CSP

(ball size:0.3mm)

MX29LV160ATXEC-90

48 Ball CSP

(ball size:0.4mm)

MX29LV160ABXEC-90

48 Ball CSP

(ball size:0.4mm)

MX29LV160ATXBI-70

48 Ball CSP

(ball size:0.3mm)

MX29LV160ABXBI-70

48 Ball CSP

(ball size:0.3mm)

MX29LV160ATXEI-70

48 Ball CSP

(ball size:0.4mm)

MX29LV160ABXEI-70

48 Ball CSP

(ball size:0.4mm)

MX29LV160ATXBI-90

48 Ball CSP

(ball size:0.3mm)

MX29LV160ABXBI-90

48 Ball CSP

(ball size:0.3mm)

MX29LV160ATXEI-90

48 Ball CSP

(ball size:0.4mm)

MX29LV160ABXEI-90

48 Ball CSP

(ball size:0.4mm)

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

PART NO.

Access Time Operating Current Standby Current

Package

Remark

(ns)

MAX.(mA)

MAX.(uA)

MX29LV160ATTC-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ABTC-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ATTC-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ABTC-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ATTI-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ABTI-70G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ATTI-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ABTI-90G

48 Pin TSOP

PB free

(Normal Type)

MX29LV160ATXBC-70G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ABXBC-70G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ATXEC-70G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ABXEC-70G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ATXBC-90G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ABXBC-90G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ATXEC-90G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ABXEC-90G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ATXBI-70G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ABXBI-70G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ATXEI-70G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ABXEI-70G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ATXBI-90G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ABXBI-90G

48 Ball CSP

PB free

(ball size:0.3mm)

MX29LV160ATXEI-90G

48 Ball CSP

PB free

(ball size:0.4mm)

MX29LV160ABXEI-90G

48 Ball CSP

PB free

(ball size:0.4mm)

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

REVISION HISTORY

Revision No. Description

Page

Date

(MX29LV160AT/AB)
0.1

Mis-typing:Table 4-3 Device Gemetry Data Values

NOV/15/2001

1) Device size: Data=0015h
2) Erase block region 1 information:
Data=0000h for byte address=5A, Word address=2D
Data=0040h for byte address=5E, Word address=2F
Data=0000h for byte address=60, Word address=30

0.2

Added 48-Ball CSP Package

P1,2,56,59 DEC/11/2001

0.3

1.Modify Ordering Information

P56

DEC/28/2001

2.Add 48-ball CSP Package Information for MX29LV160ATXEC/TXEI

P60

DEC/28/2001

/BXEC/BXBI)

(MX29LV160T/B)
1.1

Changed DQ-->Q

P2,6,7,9,21,22 APR/05/2000

Modify Toggle Bit I-->II

P13

Modify Ambient Operating Temperature 0

C to 70

P15

1.2

Correct Type Error

APR/17/2000

Modify DC Characteristics VCC=5V

10%-->VCC=3V

10%

P16

1.3

Modify Timing Waveform for Chip Unprotection 5V-->3V

P33

MAY/08/2000

1.4

1.Add "Table 8" for Read Operation, DC Characteristics

P19

JUN/05/2000

2.Add "Table 9" for Read Operation, AC Characteristics

P20

3.Add & Modify "Table 10" for Erase/Program Operation,

P23

AC Characteristics
4.Add "Table 11" for Alternate CE Controlled Erase/Program

P24

Operations
5.Modify Automatic Programming Timing Waveform, Automatic

P26,27

Programming Algorithm Flowchart
6.Add CE Controlled Programming Timing Waveform

P28

8.Add Write Operation Status for DATA polling & Toggle Bit

P39,40,41

Algorithm and Timing Waveform
9.Add Q6 vs Q2 for Erase and Erase Suspend Operation

P44

1.5

Modify Feature--10,000 minimum erase/program cycles-->100,000-- P1

JUN/28/2000

Modify General Description--even after 10,000 --->100,000 erase--

1.6

Modify Erase/Program Cycles(MIN.) 10,000-->100,000

P47

AUG/25/2000

1.7

Correct content error

P13,14,19,30 SEP/14/2000

Add Title Description

P34,37

Add Sector Protect Timing waveform

P35

Add Sector Protection Algorithm

P36

1.8

Add AC Characteristics-- 29LV160T/B-70R

P20

NOV/09/2000

Add Ordering Information

P50

1.9

Add AC Characteristics Table10 & Table11-- 29LV160T/B-70R

P23,24

NOV/16/2000

2.0

Delete Unlock Bypass Command Definitions

JAN/04/2001

Delete Unlock Bypass Command Sequence

P14

2.1

Add Ordering Information--48 Ball CSP

P50

JAN/16/2001

2.2

To corrected the naming of reset pin from RP to RESET

JAN/30/2001

2.3

Modify Timing Waveform

P27,29,30,32 FEB/07/2001

Modify Automatic Programming Algorithm Flowchart

P28

Delete Figure 21. Toggle Bit Timings(During Embedded Algorithms) P45
Add Figure 19. Toggle Bit Algorithm

P43

Modify Absolute Maximum Ratings

P19

P/N:PM0866

MX29LV160T/B & MX29LV160AT/AB

REV. 3.7, APR. 23, 2003

Rev. No. Description

Page

Date

2.4

Change tBUSY spec. from 90ns to 90us

P24

MAR/07/2001

2.5

Correct typing error

P23,2

JUL/03/2001

tWPP1/tWPP2 was changed to 100ns

P40

To modify Package Information

P52~54

2.6

Separate the tBUSY spec: tBUSY:90us for sector erase

P24

JUL/05/2001

tBUSY:90ns for chip erase ; tBUSY:90ns for program

2.7

Correct typing error

P24

JUL/10/2001

2.8

Add MX29LV161T/B part number

All

JUL/24/2001

MX29LV160T/B tBUSY=90ns at sector erase mode

P24

MX29LV161T/B tBUSY=90us at sector erase mode

P24

2.9

1.Separate data sheet into two files:MX29LV160T/B & MX29LV161T/B

All

SEP/24/2001

2.tBUSY spec was changed from 90ns min. to 90ns max.

P24

3.Add tWPP1/tWPP2 typical spec

P24

4.Add word/byte switching spec and waveform

P47,48

5.Add 90R speed grade

P21,24,51

6.The expression of 48-ball CSP pin configuration was changed from

"Top view, ball facing up" to "Top view, ball facing down"
(The physical pin out is not changed, just a different expression.)
7.Correct mistyping
- byte/word program:7us/12us-->9us/11us

P1,24

- sector size of word mode 16K words/8K words/32K words/64K words P4
--->8K words/4K words/16K words/32K words
- TA of Extended Devices was removed

P19

- ICC4 condition: RESET=VCC

0.3V --> RESET=VSS

0.3V

P20

- TA=0

C to 70

C -->TA=-40

C to 85

P20,21,24

- Add A19~A12 into figure

P35,41

3.0

Wording change of sector erase commands

P11,13,27,30 OCT/17/2001
P32

(MX29LV160T/B & MX29LV160AT/AB)
3.1

1. Combinded MX29LV160AT/AB & MX29LV160T/B datasheet to be

All

JAN/11/2001

together
2. The system must write "Reset" command to exit "silicon-ID read

P12-14,19

mode" & "sector protection verification" mode

3.2

1. Add 10ms time delay for erase suspend/resume

P15,36

MAR/01/2002

3.3

1. Correct typing error

P1,2,7,10,11

MAR/08/2002

13,14,16,17,51

3.4

1. Modified content error

All

OCT/01/2002

2. Updated Spec :

P1,21,48

VLKO value : 2.3V/2.5V-->1.4V/2.1V ;
min. of tRH/tRB : 50ns/0ns-->70ns/70ns
3. Removed 44SOP package information of "A" version

P2, 55

4. Removed -R grade information

P21,23,26,27,49,55-56

5. Updated Capacitance

P22

6. Added note at Switching Test Circuit

P22

CL=100pF for MX29LV160(A)T/B-90

CL=30pF for MX29LV160(A)T/B-70

7. To added the tVLHT & tOESP timing in AC Characteristics table

P26

8. Redefined Erase and Programming Performance : maximum values

P54

measued from 25

C, 2.7V to 85

C, 2.7V, 100,000 cycles

3.5

1. To modify Package Information

P57~61

NOV/21/2002

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX29LV160T

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX29LV160T