SCAN50C400
1.25/2.5/5.0 Gbps Quad Multi-rate Backplane Transceiver
General Description
The SCAN50C400 is a four-channel high-speed backplane
transceiver (SERDES) designed to support multiple line data
rates at 1.25, 2.5 or 5.0 Gbps over a printed circuit board
backplane. It provides a data link of up to 20 Gbps total
through-put in each direction.
Each transmit section of the SCAN50C400 takes a 4-bit
differential LVDS source synchronous data bus, serializing it
to a differential high-speed serial bit stream and output from
a CML driver. The receive section of the SCAN50C400
consists of a differential input stage, a clock/data recovery
PLL, a serial-to-parallel converter, and a LVDS output bus.
De-emphasis at the high-speed driver outputs and a limiting
amplifier circuit at the receiver inputs are used to reduce ISI
distortions to enable error-free data transmission over more
than 26 inches point-to-point link with a low cost FR4 back-
plane.
Internal low jitter PLLs are used to derive the high-speed
serial clock from a differential reference clock source. Two
channels share common transmit and receive LVDS clocks.
The SCAN50C400 has built-in self-test (BIST) circuitry and
also loopback test modes to support at-speed self-testing.
Features
n
Quad Backplane SERDES transceiver
n
Multiple data rates at 1.25, 2.5 or 5 Gbps
n
40 Gbps total full duplex throughput
n
Better than 10
-15
bit error rate
n
Test Modes: On-chip at-speed BIST circuitry, Loopbacks
n
On-chip LVDS and CML terminations
n
High-speed CML driver with optional signal conditioning
n
4-bit differential source synchronous LVDS parallel I/O
n
Low-jitter PLL reference to external differential HSTL
clock at 125 MHz
n
Designed for use with low cost FR4 backplane
n
TIA/EIA 644-A compatible LVDS IO
n
IEEE Draft P802.3ae D4.0 - MDIO management
interface protocol compatible
n
IEEE 1149.1 (JTAG) compliant test mode
n
1.35V for core, high-speed circuitry and MDIO
n
3.3V
5% for LVDS IO, Control and JTAG interface
n
Low power, 4.5W (TYP)
n
23 mm x 23 mm thermally enhanced BGA package
Typical Application
20046101
PRELIMINARY
January 2004
SCAN50C400
1.25/2.5/5.0
Gbps
Quad
Multi-rate
Backplane
T
ransceiver
2004 National Semiconductor Corporation
DS200461
www.national.com
Pin Descriptions
Pin Name
Ball
Number
I/O, Type
Description
HIGH-SPEED DIFFERENTIAL I/O
HT1+
HT1-
L22
L21
O, CML
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 1. Data is sourced from T1_1
, T1_2
, T1_3
and T1_4
. On-chip 50
termination resistors connect from HT1+ and HT1- to V
DDHS
.
HT2+
HT2-
J22
J21
O, CML
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 2. Data is sourced from T1_5
, T1_6
, T1_7
and T1_8
. On-chip 50
termination resistors connect from HT2+ and HT2- to V
DDHS
.
HT3+
HT3-
G22
G21
O, CML
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 3. Data is sourced from T2_1
, T2_2
, T2_3
and T2_4
. On-chip 50
termination resistors connect from HT3+ and HT3- to V
DDHS
.
HT4+
HT4-
E22
E21
O, CML
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 4. Data is sourced from T2_5
, T2_6
, T2_7
and T2_8
. On-chip 50
termination resistors connect from HT4+ and HT4- to V
DDHS
.
HR1+
HR1-
N22
N21
I, CML
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 1.
Data is de-serialized and output at R1_1
, R1_2
, R1_3
and R1_4
. On-chip 50
termination resistors connect from HR1+ and HR1- to an internal bias.
HR2+
HR2-
R22
R21
I, CML
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 2.
Data is de-serialized and output at R1_5
, R1_6
, R1_7
and R1_8
. On-chip 50
termination resistors connect from HR2+ and HR2- to an internal bias.
HR3+
HR3-
U22
U21
I, CML
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 3.
Data is de-serialized and output at R2_1
, R2_2
, R2_3
and R2_4
. On-chip 50
termination resistors connect from HR3+ and HR3- to an internal bias.
HR4+
HR4-
W22
W21
I, CML
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 4.
Data is de-serialized and output at R2_5
, R2_6
, R2_7
and R2_8
. On-chip 50
termination resistors connect from HR4+ and HR4- to an internal bias.
REFERENCE CLOCK
SCLK+
SCLK-
A16
B16
I, HSTL
Inverting and non-inverting differential reference clock to the PLL for generating internal
high-speed clocks. A low jitter 125 MHz
100 ppm clock should be connected to SCLK
.
All four serializers and deserializers are frequency-locked to SCLK
. A 50
termination
to Ground is present on each input pin.
TRANSMIT INPUT DATA
T1_1+
T1_1-
T1_2+
T1_2-
T1_3+
T1_3-
T1_4+
T1_4-
K3
K4
J3
J4
H1
H2
G1
G2
I, LVDS
Differential transmit input data for channel 1. An on-chip 100
resistor is connected
between each pair of complimentary inputs.
T1[14]
are synchronous to clock T1_CLK
. Data at T1[14]
are serialized and
output at HT1
. T1_1 is shifted out first, see Figure 2. Data is strobed on both rising and
falling edges of T1_CLK
.
T1_5+
T1_5-
T1_6+
T1_6-
T1_7+
T1_7-
T1_8+
T1_8-
F3
F4
E3
E4
D1
D2
C1
C2
I, LVDS
Differential transmit input data for channel 2. An on-chip 100
resistor is connected
between each pair of complimentary inputs.
T1[58]
are synchronous to clock T1_CLK
. Data at T1[58]
are serialized and
output at HT2
. T1_5 is shifted out first, see Figure 2. Data is strobed on both rising and
falling edges of T1_CLK
.
T1_CLK+
T1_CLK-
K1
K2
I, LVDS
Differential 625 MHz transmit nibble clock for channels 1 and 2. Data at T1[14]
and
T1[58]
are strobed-in at both rising and falling edges of T1_CLK
, forming an 8-bit
input data bus at 1.25 Gbps. T1_CLK
should be frequency-locked to reference clock
SCLK
. An on-chip 100
resistor is connected between each pair of complimentary
inputs.
SCAN50C400
www.national.com
4
Pin Descriptions
(Continued)
Pin Name
Ball
Number
I/O, Type
Description
TRANSMIT INPUT DATA
T2_1+
T2_1-
T2_2+
T2_2-
T2_3+
T2_3-
T2_4+
T2_4-
A7
B7
C8
D8
A9
B9
A10
B10
I, LVDS
Differential transmit input data for channel 3. An on-chip 100
resistor is connected
between each pair of complimentary inputs.
T2[14]
are synchronous to clock T2_CLK
. Data at T2[14]
are serialized and
output at HT3
. T2_1 is shifted out first, see Figure 2. Data is strobed on both rising and
falling edges of T2_CLK
.
T2_5+
T2_5-
T2_6+
T2_6-
T2_7+
T2_7-
T2_8+
T2_8-
C11
D11
C12
D12
A13
B13
A14
B14
I, LVDS
Differential transmit input data for channel 4. An on-chip 100
resistor is connected
between each pair of complimentary inputs.
T2[58]
are synchronous to clock T2_CLK
. Data at T2[58]
are serialized and
output at HT4
. T2_5 is shifted out first, see Figure 2. Data is strobed on both rising and
falling edges of T2_CLK
.
T2_CLK+
T2_CLK-
C6
D6
I, LVDS
Differential 625 MHz transmit nibble clock for channels 3 and 4. Data at T2[14]
and
T2[58]
are strobed-in at both rising and falling edges of T2_CLK
, forming an 8-bit
input data bus at 1.25 Gbps. T2_CLK
should be frequency-locked to reference clock
SCLK
. An on-chip 100
resistor is connected between each pair of complimentary
inputs.
RECEIVE OUTPUT DATA
R1_1+
R1_1-
R1_2+
R1_2-
R1_3+
R1_3-
R1_4+
R1_4-
N3
N4
P3
P4
R1
R2
T1
T2
O, LVDS
Channel 1 deserialized recovered data. Data at HR1
is de-serialized and output at
R1[14]
, clocked by both rising and falling edges of R1_CLK
.
R1_5+
R1_5-
R1_6+
R1_6-
R1_7+
R1_7-
R1_8+
R1_8-
U3
U4
V3
V4
W1
W2
Y1
Y2
O, LVDS
Channel 2 deserialized recovered data. Data at HR2
is de-serialized and output at
R1[58]
, clocked by both rising and falling edges of R1_CLK
.
R1_CLK+
R1_CLK-
N1
N2
O, LVDS
Differential recovered nibble clock for channel 1 and 2. R1_CLK
is a 625 MHz clock
sourced from the clock recovery PLL. R1_CLK
, together with R1[14]
and R1[58]
,
form a source synchronous 8-bit output data bus at 1.25 Gbps.
R2_1+
R2_1-
R2_2+
R2_2-
R2_3+
R2_3-
R2_4+
R2_4-
AB7
AA7
Y8
W8
AB9
AA9
AB10
AA10
O, LVDS
Channel 3 deserialized recovered data. Data at HR3
is de-serialized and output at
R2[14]
, clocked by both rising and falling edges of R2_CLK
.
SCAN50C400
www.national.com
5
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