Pin
Function
B
0
B
7
Check Bit Inputs
BPAR
Check Bit Parity Input
EV/OD
Even/Odd Parity Select
EN
Parity Enable
HOLD
Syndrome Hold Input
S-IN
Syndrome Bit Input
SHIFT
Syndrome Bit Shift
CLK
Clock Input
P
1
P
5
Parity Output
PGEN
Parity Generate Output
PARERR/PARERR
Parity Error Output
V
CCO
V
CC
to Output
s
Hamming code generation
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
8-bit wide
s
Expandable for more width
s
Provides parity register
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E193
s
Available in 28-pin PLCC package
FEATURES
The SY10/100E193 are error detection and correction
(EDAC) circuits designed for use in new, high- performance
ECL systems. The E193 generates hamming parity codes
on an 8-bit word as shown in the block diagram. The P
5
output gives the parity of the whole word. PGEN provides
word parity after Odd/Even parity control and gating with
the BPAR input. PGEN also feeds into a 1-bit shiftable
register for use as part of a scan ring.
The combinatorial part of the device generates the same
code pattern as the Motorola MC10193.
Used in conjunction with 12-bit parity generators, such
as the E160, a SECDED (single error correction, double
error detection) error system can be designed for a multiple
of an 8-bit word.
DESCRIPTION
ERROR DETECTION/
CORRECTION CIRCUIT
PIN CONFIGURATION
PIN NAMES
Rev.: C
Amendment: /1
Issue Date:
February, 1998
SY10E193
SY100E193
TOP VIEW
PLCC
J28-1
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
B
5
B
4
P
2
V
CCO
B
6
B
7
P
1
V
CC
PARERR
P
3
P
5
PARERR
V
CCO
P
4
V
EE
B
3
BPAR
B
2
B
1
B
0
EV/OD
S-IN
EN
V
CCO
SHIFT
CLK
PGEN
HOLD
1
3
SY10E193
SY100E193
Micrel
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
A
--
I
EE
Power Supply Current
mA
--
10E
--
112
134
--
112
134
--
112
134
100E
--
112
134
--
112
134
--
129
155
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ps
--
t
PHL
B to P
1
, P
2
, P
3
, P
4
350
700
1000
350
700
1000
350
700
1000
B to P5
400
775
1150
400
775
1150
400
775
1150
EV/OD, BPAR to PGEN
350
650
850
350
650
850
350
650
850
B to PGEN
600
1000 1450
600
1000
1450
600
1000
1450
CLK to PARERR
300
550
850
300
550
850
300
550
850
t
S
Set-up Time
ps
--
SHIFT
400
150
--
400
150
--
400
150
--
S-IN
300
50
--
300
50
--
300
50
--
HOLD
750
350
--
750
350
--
750
350
--
EN
500
250
--
500
250
--
500
250
--
EV/OD
1300
850
--
1300
850
--
1300
850
--
BPAR
1300
850
--
1300
850
--
1300
850
--
B
1700 1100
--
1700 1100
--
1700 1100
--
t
H
Hold Time
ps
--
SHIFT
200
150
--
200
150
--
200
150
--
S-IN
300
50
--
300
50
--
300
50
--
HOLD
100
350
--
100
350
--
100
350
--
EN
100
250
--
100
250
--
100
250
--
EV/OD
200 850
--
200 850
--
200 850
--
BPAR
200 850
--
200 850
--
200 850
--
B
300 1100
--
300 1100
--
300 1100
--
t
r
Rise/Fall Time
300
700
1100
300
700
1100
300
700
1100
ps
--
t
f
20% to 80%
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E193JC
J28-1
Commercial
SY10E193JCTR
J28-1
Commercial
SY100E193JC
J28-1
Commercial
SY100E193JCTR
J28-1
Commercial
4
SY10E193
SY100E193
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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