DESCRIPTION
FEATURES
s
Scannable version E112 driver
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
1025ps max. CLK to Output
s
Dual differential outputs
s
Master Reset
s
Internal 75K
input pull-down resistors
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Fully compatible with Motorola MC10E/100E212
s
Available in 28-pin PLCC package
The SY10/100E212 are scannable registered ECL
drivers typically used as fan-out memory address drivers
for ECL cache driving. In a VLSI array-based CPU design,
use of the E212 allows the user to conserve array output
cell functionality and also output pins.
The input shift register is designed with control logic
which greatly facilitates its use in boundary scan
applications.
3-BIT SCANNABLE
REGISTER
SY10E212
SY100E212
Rev.: C
Amendment: /1
Issue Date: February, 1998
BLOCK DIAGRAM
Q
2b
Q
2a
Q
2a
Q
2b
D
Q
D
2
Q
1b
Q
1a
Q
1a
Q
1b
D
Q
D
1
Q
0b
Q
0a
Q
0a
Q
0b
D
Q
D
0
S-OUT
S-IN
LOAD
SHIFT
CLK
MR
PIN CONFIGURATION
18
17
16
15
14
13
12
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23 22 21 20 19
CLK
D
2
V
EE
D
1
D
0
S-IN
LOAD
NC
V
CCO
Q
0a
Q
0b
V
CCO
Q
0a
Q
0b
Q
2b
Q
2a
V
CC
Q
1b
Q
1a
Q
1b
Q
1a
NC
S-OUT
V
CCO
SHIFT
MR
Q
2b
Q
2a
Pin
Function
D
0
D
2
Data Inputs
S-IN
Scan Input
LOAD
LOAD/HOLD Control
SHIFT
Scan Control
CLK
Clock
MR
Master Reset
S-OUT
Scan Output
Q[0:2]a, Q[0:2]b
True Outputs
Q[0:2]a, Q[0:2]b
Inverting Outputs
V
CCO
V
CC
to Output
PIN NAMES
1
2
SY10E212
SY100E212
Micrel
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
A
--
I
EE
Power Supply Current
mA
--
10E
--
80
96
--
80
96
--
80
96
100E
--
80
96
--
80
96
--
92
110
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E212JC
J28-1
Commercial
SY10E212JCTR
J28-1
Commercial
SY100E212JC
J28-1
Commercial
SY100E212JCTR
J28-1
Commercial
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ps
--
t
PHL
CLK
575
800
1025
575
800
1025
575
800
1025
MR
575
800
1025
575
800
1025
575
800
1025
CLK to S-OUT
575
800
1025
575
800
1025
575
800
1025
t
S
Set-up Time
ps
--
D
175
25
--
175
25
--
175
25
--
SHIFT
150
50
--
150
50
--
150
50
--
LOAD
225
50
--
225
50
--
225
50
--
S-IN
150
50
--
150
50
--
150
50
--
t
H
Hold Time
ps
--
D
250
25
--
250
25
--
250
25
--
SHIFT
300
100
--
300
100
--
300
100
--
LOAD
225
0
--
225
0
--
225
0
--
S-IN
300
100
--
300
100
--
300
100
--
t
RR
Reset Recovery
600
350
--
600
350
--
600
350
--
ps
--
t
skew
Within-Device Skew
--
100
--
--
100
--
--
100
--
ps
1
t
skew
Within-Gate Skew
--
50
--
--
50
--
--
50
--
ps
2
t
r
Rise/Fall Times
275
425
650
275
425
650
275
425
650
ps
--
t
f
20% to 80%
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
TRUTH TABLE
LOAD
SHIFT
MR
Mode
L
L
L
Load
H
L
L
Hold
X
H
L
Shift
X
X
H
Reset
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
NOTES:
1. Within-device skew is defined as identical transitions on similar paths
through a device.
2. Within-gate skew is defined as the difference in delays between various
outputs of a gate when driven from the same input.
4
SY10E212
SY100E212
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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