TRIPLE D
FLIP-FLOP
SY100S331
s
Max. toggle frequency of 800MHz
s
Differential outputs
s
I
EE
min. of 80mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 4.2V to 5.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
input pull-down resistors
s
150% faster than Fairchild
s
40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
FEATURES
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CP
c
), as well as
its own clock pulse (CP
n
). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CP
c
and CP
n
are LOW and enters the slave on the rising edge
of either CP
c
or CP
n
(or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SD
n
) and Direct Clear (CD
n
) signals. The MR,
MS, SD
n
and DC
n
signals override the clock signals. The
inputs on this device have 75K
pull-down resistors.
Rev.: G
Amendment: /0
Issue Date:
July, 1999
BLOCK DIAGRAM
CP
C
CP
D
S
D
C
D
CP
2
CD
2
D
2
SD
2
Q
2
Q
2
CP
D
S
D
C
D
CP
1
CD
1
D
1
SD
1
Q
1
Q
1
CP
D
S
D
C
D
CP
0
CD
0
D
0
SD
0
Q
0
Q
0
MS MR
D
1
SD
1
MR
V
EE
CP
C
MS
SD
0
CD
0
CP
0
D
0
Q
0
Q
0
CP
1
SD
2
CP
2
CD
1
D
2
CD
2
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
V
CC
V
CCA
Q
2
Q
1
Q
2
Q
1
PIN CONFIGURATIONS
Q
1
Q
1
V
CCA
V
CC
Q
2
V
CC
MS
V
EE
MR
CP
C
SD
1
V
EES
4
3
2
1
28
27
12
13
14
15
16
17
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
Q
2
D
1
26
18
25
5
SD
0
CD
0
CP
0
V
EES
D
0
Q
0
Q
0
SD
2
V
EES
CD
1
CD
2
CP
1
CP
2
D
2
1
2
SY100S331
Micrel
Synchronous Operation
(1)
Inputs
Outputs
MS
MR
D
n
CP
n
CP
c
SD
n
DC
n
Q
n
L
u
L
L
L
L
H
u
L
L
L
H
L
L
u
L
L
L
H
L
u
L
L
H
X
L
L
L
L
Q
n
(t)
X
H
X
L
L
Q
n
(t)
X
X
H
L
L
Q
n
(t)
Asynchronous Operation
(1)
Inputs
Outputs
MS
MR
D
n
CP
n
CP
c
SD
n
DC
n
Q
n
(t+1)
X
X
X
H
L
H
X
X
X
L
H
L
X
X
X
H
H
U
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
DC ELECTRICAL CHARACTERISTICS
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
TRUTH TABLES
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current, All Inputs
--
--
200
A
V
IN
= V
IH
(Max.)
I
EE
Power Supply Current
80
65
35
mA
Inputs Open
Pin
Function
CP
0
CP
2
Individual Clock Inputs
CP
c
Common Clock Input
D
0
D
2
Data Inputs
CD
0
CD
2
Individual Direct Clear Inputs
SD
n
Individual Direct Set Inputs
MR
Master Reset Input
MS
Master Set Input
Q
0
Q
2
Data Outputs
Q
0
Q
2
Complementary Data Outputs
V
EES
V
EE
Substrate
V
CCA
V
CCO
for ECL Outputs
PIN NAMES
3
SY100S331
Micrel
AC ELECTRICAL CHARACTERISTICS
CERPACK
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
f
max
Toggle Frequency
800
--
800
--
800
--
MHz
t
PLH
Propagation Delay
300
800
300
800
300
800
ps
t
PHL
CP
c
to Output
t
PLH
Propagation Delay
300
800
300
800
300
800
ps
t
PHL
CP
n
to Output
t
PLH
Propagation Delay
300
900
300
900
300
900
ps
t
PHL
CD
n
, SD
n
to Output
t
PLH
Propagation Delay
300
1000
300
1000
300
1000
ps
t
PHL
MS, MR to Output
t
TLH
Transition Time
300
900
300
900
300
900
ps
t
THL
20% to 80%, 80% to 20%
t
S
Set-up Time
ps
D
n
400
--
400
--
400
--
CD
n
, SD
n
(Release Time)
500
--
500
--
500
--
MS, MR (Release Time)
800
--
800
--
800
--
t
H
Hold Time D
n
300
--
300
--
300
--
ps
t
pw
(H)
Pulse Width HIGH
800
--
800
--
800
--
ps
CP
n
, CP
c
, DC
n
SD
n
, MR, MS
PLCC
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
f
max
Toggle Frequency
800
--
800
--
800
--
MHz
t
PLH
Propagation Delay
300
700
300
700
300
700
ps
t
PHL
CP
c
to Output
t
PLH
Propagation Delay
300
700
300
700
300
700
ps
t
PHL
CP
n
to Output
t
PLH
Propagation Delay
300
800
300
800
300
800
ps
t
PHL
CD
n
, SD
n
to Output
t
PLH
Propagation Delay
300
900
300
900
300
900
ps
t
PHL
MS, MR to Output
t
TLH
Transition Time
300
900
300
900
300
900
ps
t
THL
20% to 80%, 80% to 20%
t
S
Set-up Time
ps
D
n
400
--
400
--
400
--
CD
n
, SD
n
(Release Time)
500
--
500
--
500
--
MS, MR (Release Time)
800
--
800
--
800
--
t
H
Hold Time D
n
300
--
300
--
300
--
ps
t
pw
(H)
Pulse Width HIGH
800
--
800
--
800
--
ps
CP
n
, CP
c
, DC
n
SD
n
, MR, MS
4
SY100S331
Micrel
TIMING DIAGRAMS
Propagation Delay (Clock) and Transition Times
OUTPUT
DATA
20%
80%
50%
t
PLH
t
PHL
t
TLH
t
THL
0.7
0.1 ns
0.7
0.1 ns
0.95V
1.69V
CLOCK
OUTPUT
t
PHL
t
PLH
50%
1/fmax
tpw (H)
NOTE:
V
EE
= 4.2V to 5.5V unless otherwise specified, V
CC
= V
CCA
= GND
OUTPUT
SD
n
, CD
n
MS, MR
50%
t
PLH
t
PHL
+0.31V
CLOCK
OUTPUT
t
PHL
t
PLH
50%
t
pw
(H)
20%
80%
50%
0.7
0.1 ns
0.7
0.1 ns
+1.05V
t
S
(RELEASE TIME)
20%
80%
50%
Propagation Delay (Sets and Resets)
5
SY100S331
Micrel
TIMING DIAGRAMS
CLOCK
50%
+0.31V
DATA
t
S
50%
t
h
+1.05V
+0.31V
+1.05V
Data Setup and Hold Time
NOTES:
t
s
is the minimum time before the transition of the clock that information must be present at the data input.
t
h
is the minimum time after the transition of the clock that information must remain unchanged at the data input.
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY100S331FC
F24-1
Commercial
SY100S331JC
J28-1
Commercial
SY100S331JCTR
J28-1
Commercial
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