The SY100S838/L is a low skew (
1,
2/3) or (
2,
4/
6) clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the CLK
input and bypassed to ground via a 0.01
F capacitor.
The V
BB
output is designed to act as the switching
reference for the input of the SY100S838/L under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The Function Select (F
SEL
) input is used to determine
what clock generation chip function is. When FS
EL
input
is LOW, SY100S838/L functions as a divide by 2 and by
4/6 clock generation chip. However, if FS
EL
input is HIGH,
it functions as a divide by 1 and by 2/3 clock chip.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S838/Ls in a system.
s
3.3V and 5V power supply options
s
50ps output-to-output skew
s
Synchronous enable/disable
s
Master Reset for synchronization
s
Internal 75K
input pull-down resistors
s
Available in 20-pin SOIC package
DESCRIPTION
FEATURES
Rev.: E
Amendment: /1
Issue Date:
August, 1998
(
1,
2/3) OR (
2,
4/6)
CLOCK GENERATION CHIP
ClockWorksTM
SY100S838
SY100S838L
Pin
Function
CLK
Differential Clock Inputs
F
SEL
Function Select Input
EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0,
Q
1
Differential
1 or
2 Outputs
Q
2,
Q
3
Differential
2/3 or
4/6 Outputs
DIVSEL
Frequency Select Input
PIN NAMES
F
SEL
DIVSEL
Q
0,
Q
1
OUTPUTS
Q
2,
Q
3
OUTPUTS
L
L
Divide by 2
Divide by 4
L
H
Divide by 2
Divide by 6
H
L
Divide by 1
Divide by 2
H
H
Divide by 1
Divide by 3
CLK
EN
MR
Function
Z
L
L
Divide
ZZ
H
L
Hold Q
03
X
X
H
Reset Q
03
TRUTH TABLE
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
PIN CONFIGURATION
V
CC
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
V
CC
EN
DIVSEL CLK
CLK
V
BB
MR
V
CC
NC
F
SEL
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
SOIC
Z20-1
1
3
ClockWorksTM
SY100S838
SY100S838L
Micrel
Ordering
Package
Operating
V
EE
Range
Code
Type
Range
(V)
SY100S838ZC
Z20-1
Commercial
-4.2 to -5.5
SY100S838ZCTR
Z20-1
Commercial
-4.2 to -5.5
SY100S838LZC
Z20-1
Commercial
-3.0 to -3.8
SY100S838LZCTR
Z20-1
Commercial
-3.0 to -3.8
PRODUCT ORDERING CODE
TIMING DIAGRAM
Q (
1)
Q (
2)
Q (
3)
CLK
Q (
4)
Q (
6)
T
A
= 40
C
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ. Max.
Min. Typ. Max. Min.
Typ. Max.
Unit
f
MAX
Maximum Toggle Frequency
1000
--
--
1000
--
--
1000
--
--
1000
--
--
MHz
t
PLH
Propagation Delay to Output
ps
t
PHL
CLK
Output (Diff.)
950
--
1150
950
--
1150
970
--
1170 1050
--
1250
CLK
Output (S.E.)
900
--
1200
900
--
1200
920
--
1220 1000
--
1300
MR
Q
600
--
900
600
--
900
600
--
900
600
--
900
t
skew
Within-Device Skew
(2)
Q0 -- Q3
--
--
50
--
--
50
--
--
50
--
--
50
ps
Part-to-Part
Q0 -- Q3 (Diff.)
--
--
200
--
--
200
--
--
200
--
--
200
t
S
Set-up Time
EN
CLK
300
150
--
300
150
--
300
150
--
300
150
--
ps
DIVSEL
CLK
300
--
--
300
--
--
300
--
--
300
--
--
t
H
Hold Time
CLK
EN
400
150
--
400
150
--
400
150
--
400
150
--
ps
CLK
DIVSEL
400
200
--
400
200
--
400
200
--
400
200
--
V
PP
Minimum Input Swing
(3)
CLK
250
--
--
250
--
--
250
--
--
250
--
--
mV
V
CMR
Common Mode Range
(4)
CLK
(4)
--
-0.55
(4)
--
-0.55
(4)
--
-0.55
(4)
--
-0.55
V
t
RR
Reset Recovery Time
--
--
100
--
--
100
--
--
100
--
--
100
ps
t
PW
Minimum Pulse Width
CLK
800
--
--
800
--
--
800
--
--
800
--
--
ps
MR
700
--
--
700
--
--
700
--
--
700
--
--
tr
Output Rise/Fall Times
Q
280
--
550
280
--
550
280
--
550
280
--
550
ps
tf
(20% --80%)
AC ELECTRICAL CHARACTERISTICS
(1)
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= GND
NOTES:
1. Parametric values specified at:
5 volt Power Supply Range
100S838 Series:
-4.2V to -5.5V.
3 volt Power Supply Range
100S838L Series
-3.0V to -3.8V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between V
PP
(min) and 1.0V. The lower end of the CMR range is dependent on V
EE
and is equal to V
EE
+1.65V.
Ordering
Package
Operating
V
EE
Range
Code
Type
Range
(V)
SY100S838ZI
Z20-1
Industrial
-4.2 to -5.5
SY100S838ZITR
Z20-1
Industrial
-4.2 to -5.5
SY100S838LZI
Z20-1
Industrial
-3.0 to -3.8
SY100S838LZITR
Z20-1
Industrial
-3.0 to -3.8
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