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Электронный компонент: SY10E016JCTR

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Pin
Function
P
0
-P
7
Parallel Data (Preset) Inputs
Q
0
-Q
7
Data outputs
CE
Count Enable Control Input
PE
Parallel Load Enable Control Input
MR
Master Reset
CLK
Clock
TC
Terminal Count Output
TCLD
TC-Load Control Input
V
CCO
V
CC
to Output
s
700MHz min. count frequency
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
1000ps CLK to Q, TC
s
Internal, gated TC feedback
s
8 bits wide
s
Fully synchronous counting and TC generation
s
Asynchronous Master Reset
s
Fully compatible with industry standard 10KH,
100K I/O levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E016
s
Available in 28-pin PLCC package
The SY10/100E016 are high-speed synchronous,
presettable and cascadable 8-bit binary counters designed
for use in new, high-performance ECL systems. Architecture
and operation are the same as the Motorola MC10H016 in
the MECL 10KH family, extended to 8 bits, as shown in the
logic diagram.
The counters feature internal feedback of TC, gated by
the TCLD (terminal count load) pin. When TCLD is LOW,
the TC feedback is disabled and counting proceeds
continuously, with TC going LOW to indicate an all-HlGH
state. When TCLD is HIGH, the TC feedback causes the
counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter.
8-BIT SYNCHRONOUS
BINARY UP COUNTER
SY10E016
SY100E016
FINAL
FEATURES
DESCRIPTION
PIN CONFIGURATION
PIN NAMES
Rev.: D
Amendment: /2
Issue Date:
May, 1998
V
EE
MR
CLK
P
0
NC
V
CCO
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
P
1
TCLD
Q
2
Q
1
Q
7
P
5
PLCC
TOP VIEW
J28-1
TC
CE
PE
P
6
P
7
Q
6
V
CC
Q
5
V
CCO
Q
4
Q
3
Q
0
V
CCO
P
4
P
3
P
2
1
2
SY10E016
SY100E016
Micrel
BLOCK DIAGRAM
BIT 7
BIT 2 BIT 6
BIT 1
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
CE
P
7
P
1
CE
SLAVE
MASTER
Q
0
M
Q
0
M
Q
0
BIT 0
5
5
5
5
5
5
P
0
TC
Q
7
Q
0
Q
1
Q
2
Q
6
TCLD
MR CLK
PE
CE
3
SY10E016
SY100E016
Micrel
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 40
C
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ. Max. Min.
Typ. Max.
Unit
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
--
--
150
A
I
EE
Power Supply Current
mA
10E
--
151
181
--
151
181
--
151
181
--
151
181
100E
--
151
181
--
151
181
--
151
181
--
174
208
TRUTH TABLE
(1)
CE
PE
TCLD
MR
CLK
Function
X
L
X
L
Z
Load Parallel (P
n
to Q
n
)
L
H
L
L
Z
Continuous Count
L
H
H
L
Z
Count; Load Parallel on TC = LOW
H
H
X
L
Z
Hold
X
X
X
L
ZZ
Master respond, Slaves Hold
X
X
X
H
Z
Reset (Q
n
: = LOW, TC : = HIGH)
NOTE:
1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW)
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 40
C
T
A
= 0
C
T
A
= 25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max.
Min.
Typ.
Max.
Min.
Typ. Max. Min.
Typ. Max.
Unit
f
COUNT
Max. Count Frequency
700
900
--
700
900
--
700
900
--
700
900
--
MHz
t
PLH
Propagation Delay to Output
ps
t
PHL
CLK to Q
600
725
1000
600
725
1000
600
725
1000
600
725
1000
MR to Q
600
775
1000
600
775
1000
600
775
1000
600
775
1000
CLK to TC (Qs loaded)
(1)
550
775
1050
550
775
1050
550
775
1050
550
775
1050
CLK to TC (Qs unloaded)
(1)
550
700
900
550
700
900
550
700
900
550
700
900
MR to TC
625
775
1000
625
775
1000
625
775
1000
625
775
1000
t
S
Set-up Time
ps
Pn
150
30
--
150
30
--
150
30
--
150
30
--
CE
600
400
--
600
400
--
600
400
--
600
400
--
PE
600
400
--
600
400
--
600
400
--
600
400
--
TCLD
500
300
--
500
300
--
500
300
--
500
300
--
t
H
Hold Time
ps
Pn
250
30
--
250
30
--
250
30
--
250
30
--
CE
0
400
--
0
400
--
0
400
--
0
400
--
PE
0
400
--
0
400
--
0
400
--
0
400
--
TCLD
100
300
--
100
300
--
100
300
--
100
300
--
t
RR
Reset Recovery Time
900
700
--
900
700
--
900
700
--
900
700
--
ps
t
WP
Minimum Pulse Width
400
--
--
400
--
--
400
--
--
400
--
--
ps
CLK, MR
t
r
Rise/Fall Times
300
510
800
300
510
800
300
510
800
300
510
800
ps
t
f
20% to 80%
NOTE:
1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII
state to a 0000 0000 state causes the CLk to TC+ delay to increase.
AC ELECTRICAL CHARACTERISTICS
4
SY10E016
SY100E016
Micrel
FUNCTION TABLE
Function
PE
CE
MR
TCLD
CLK
P
7
P
4
P
3
P
2
P
1
P
0
Q
7
Q
4
Q
3
Q
2
Q
1
Q
0
TC
Load
L
X
L
X
Z
H
H
H
L
L
H
H
H
L
L
H
Count
H
L
L
L
Z
X
X
X
X
X
H
H
H
L
H
H
H
L
L
L
Z
X
X
X
X
X
H
H
H
H
L
H
H
L
L
L
Z
X
X
X
X
X
H
H
H
H
H
L
H
L
L
L
Z
X
X
X
X
X
L
L
L
L
L
H
Load
L
X
L
X
Z
H
H
H
L
L
H
H
H
L
L
H
Hold
H
H
L
X
Z
X
X
X
X
X
H
H
H
L
L
H
H
H
L
X
Z
X
X
X
X
X
H
H
H
L
L
H
Load On
H
L
L
H
Z
H
L
H
H
L
H
H
H
L
H
H
Terminal
H
L
L
H
Z
H
L
H
H
L
H
H
H
H
L
H
Count
H
L
L
H
Z
H
L
H
H
L
H
H
H
H
H
L
H
L
L
H
Z
H
L
H
H
L
H
L
H
H
L
H
H
L
L
H
Z
H
L
H
H
L
H
L
H
H
H
H
H
L
L
H
Z
H
L
H
H
L
H
H
L
L
L
H
Reset
X
X
H
X
X
X
X
X
X
X
L
L
L
L
L
H
5
SY10E016
SY100E016
Micrel
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output and
count enable input (CE) greatly facilitate the cascading of
E016 devices. Two E016s can be cascaded without the need
for external gating; however, for counters wider than 16 bits,
external OR gates are necessary for cascade implementations.
Figure 1, below, pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the E101
gates used to OR the terminal count outputs of the lower order
E016s to control the counting operation of the higher order
bits. When the terminal count of the preceding device (or
devices) goes low (the counter reaches an all 1s state), the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition. In
addition, the preceding devices will also count one bit, thus
sending their terminal count outputs back to a high state,
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
E016 in the chain to count all of the lower order terminal count
outputs, it must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or subtracting
E016 devices from Figure 1 and maintaining the logic pattern
illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary set-up time of the CE input and the
propagation delay through the OR gate controlling it (for 16-
bit counters the limitation is only the TC propagation delay and
the CE set-up time). Figure 1 shows E101 gates used to
control the count enable inputs; however, if the frequency of
operation is lower, a slower ECL OR gate can be used. Using
the worst case guarantees for these parameters from the
ECLinPS data book, the maximum count frequency for a
greater than 16-bit counter is 475MHz and that for a 16-bit
counter is 625MHz. Note that this assumes the trace delay
between the TC outputs and the CE inputs are negligible. If
this is not the case, estimates of these delays need to be
added to the calculations.
Figure 1. 32-Bit Cascaded E016 Counter
Q
0
Q
7
P
0
P
7
CE
PE
TC
CLK
E016
LSB
TC
CLK
E016
TC
CLK
E016
TC
CLK
E016
MSB
LOAD
"LO"
CLOCK
E101
Q
0
Q
7
Q
0
Q
7
Q
0
Q
7
P
0
P
7
P
0
P
7
P
0
P
7
CE
PE
CE
PE
CE
PE
E101