1
Pin
Function
GND
TTL Ground (0V)
V
CCE
ECL V
CC
(0V)
V
CCO
ECL V
CC
(0V) -- Outputs
V
CCT
TTL Supply (+5.0V)
V
EE
ECL Supply (5.2/4.5V)
D
0
D
8
Data Inputs (TTL)
Q
0
Q
8
Data Outputs (ECL)
ENECL
Enable Control (ECL)
LEN
Latch Enable (ECL)
MR
Master Reset (ECL)
DESCRIPTION
FEATURES
s
9-bit ideal for byte-parity applications
s
Flow-through configuration
s
Extra TTL and ECL power/ground pins to minimize
switching noise
s
Dual supply
s
3.5ns max. D to Q
s
PNP TTL inputs for low loading
s
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s
Fully compatible with Motorola MC10H/100H602
s
Available in 28-pin PLCC package
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL
translators with latches. Devices in the Micrel-Synergy
9-bit translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The H602 features D-type latches. Latching is
controlled by Latch Enable (LEN), while the Master Reset
input resets the latches. A post-latch logic enable is also
provided (ENECL), allowing control of the output state
without destroying latch data. All control inputs are ECL
level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
SY10H602
SY100H602
9-BIT LATCHED
TTL-TO-ECL
Rev.: D
Amendment: /0
Issue Date:
March, 1998
BLOCK DIAGRAM
PIN CONFIGURATION
18
17
16
15
14
13
12
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
25 24 23 22 21 20 19
V
CCT
D
3
D
2
D
1
D
5
D
4
D
0
D
6
D
7
D
8
GND
MR
LEN
ENECL
Q
0
Q
1
V
CCE
V
CCO
Q
2
V
CCO
Q
3
Q
7
Q
6
V
EE
Q
5
Q
4
Q
8
V
CCO
Q
0
D
0
TTL
LEN
MR
ECL
Q
D
EN
Q
1
D
1
Q
D
EN
Q
2
D
2
Q
D
EN
Q
3
D
3
Q
D
EN
Q
4
D
4
Q
D
EN
Q
5
D
5
Q
D
EN
Q
6
D
6
Q
D
EN
Q
7
D
7
Q
D
EN
Q
8
D
8
Q
D
EN
ENECL
PIN NAMES
2
SY10H602
SY100H602
Micrel
LOGIC DIAGRAM
TRUTH TABLE
D
LEN
MR
ENECL
Q
L
L
L
H
L
H
L
L
H
H
X
H
L
H
Q
0
X
X
H
H
L
X
X
X
L
L
DC ELECTRICAL CHARACTERISTICS
V
CCT
= 5.0V
10%; V
EE
= 4.75V to 5.5V (10H Version); V
EE
= 4.2V to 5.5V (100H Version)
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
I
EE
Power Supply Current, ECL
mA
--
10H
--
125
--
125
--
125
100H
--
122
--
123
--
132
I
CCH
Power Supply Current, TTL
--
48
--
48
--
48
mA
--
I
CCL
--
50
--
50
--
50
LOGIC DIAGRAM
AC ELECTRICAL CHARACTERISTICS
V
CCT
= 5.0V
10%; V
EE
= 4.75V to 5.5V (10H Version); V
EE
= 4.2V to 5.5V (100H Version)
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ns
--
t
PHL
D
1.4
3.0
1.5
3.2
1.7
3.5
LEN
2.0
3.4
2.1
3.5
2.4
3.7
MR
2.0
3.4
2.1
3.5
2.5
3.9
ENECL
1.6
3.2
1.7
3.3
1.8
3.7
t
S
Set-up Time, D to LEN
2.0
--
2.0
--
2.0
--
ns
--
t
H
Hold Time, D to LEN
1.0
--
1.0
--
1.0
--
ns
--
t
w
(L)
LEN Pulse Width, LOW
2.0
--
2.0
--
2.0
--
ns
--
t
r
Output Rise/Fall Time
0.5
1.5
0.5
1.5
0.5
1.5
ns
--
t
f
20% to 80%, 80% to 20%
Ordering
Package
Operating
Code
Type
Range
SY10H602JC
J28-1
Commercial
SY10H602JCTR
J28-1
Commercial
SY100H602JC
J28-1
Commercial
SY100H602JCTR
J28-1
Commercial
PRODUCT ORDERING CODE
4
SY10H602
SY100H602
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
PDF 
ZIP