s
700MHz min. shift frequency
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
8 bits wide
s
Bi-directional
s
Four selectable modes for full functionality
s
Asynchronous Master Reset
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E141
s
Pin-compatible with E241
s
Available in 28-pin PLCC package
FEATURES
The SY10/100E141 are 8-bit, full-function shift registers
designed for use in new, high-performance ECL systems.
The E141 performs serial/parallel in and serial/parallel out,
shifting in either direction. The eight inputs D
0
D
7
accept
parallel input data, while DL/DR accept serial input data for
left/right shifting.
The two select pins, SEL
0
and SEL
1
permit four modes
of operation: Load, Hold, Shift Left and Shift Right, as
shown in the Truth Table. Input data is clocked into the
register on the rising clock edge after meeting the minimum
set-up time. A logic HIGH on the Master Reset (MR) pin
asynchronously resets all the registers to zero.
DESCRIPTION
Rev.: C
Amendment: /1
Issue Date: February, 1998
BLOCK DIAGRAM
D
Q
R
D
Q
D
Q
R
D
7
Q
7
D
Q
R
D
0
Q
0
DL
DR
BITS 1-6
SEL1
SEL0
CLK
MR
SY10E141
SY100E141
8-BIT SHIFT
REGISTER
1
3
SY10E141
SY100E141
Micrel
Ordering
Package
Operating
Code
Type
Range
SY10E141JC
J28-1
Commercial
SY10E141JCTR
J28-1
Commercial
SY100E141JC
J28-1
Commercial
SY100E141JCTR
J28-1
Commercial
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
f
SHIFT
Max. Shift Frequency
700
900
--
700
900
--
700
900
--
MHz
--
t
PLH
Propagation Delay to Output
ps
--
t
PHL
CLK
625
750
975
625
750
975
625
750
975
MR
600
725
975
600
725
975
600
725
975
t
S
Set-up Time
ps
--
D
175
25
--
175
25
--
175
25
--
SEL
0
350
200
--
350
200
--
350
200
--
SEL
1
300
150
--
300
150
--
300
150
--
t
H
Hold Time
ps
--
D
200
25
--
200
25
--
200
25
--
SEL
0
100
200
--
100
200
--
100
200
--
SEL
1
100
150
--
100
150
--
100
150
--
t
RR
Reset Recovery Time
900
700
--
900
700
--
900
700
--
ps
--
t
PW
Minimum Pulse Width
400
--
--
400
--
--
400
--
--
ps
--
CLK, MR
t
skew
Within-Device Skew
--
60
--
--
60
--
--
60
--
ps
1
t
r
Rise/Fall Time
300
525
800
300
525
800
300
525
800
ps
--
t
f
20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
4
SY10E141
SY100E141
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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