s
750ps max. LEN to output
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
700ps max. D to output
s
Differential outputs
s
Asynchronous Master Reset
s
Dual latch-enables
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E154
s
Available in 28-pin PLCC package
FEATURES
5-BIT 2:1
MUX-LATCH
The SY10/100E154 offer five 2:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
Latch-Enable signals (LEN
1
, LEN
2
) are gated through a
logical OR operation before use as control for the five
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL(Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
DESCRIPTION
Rev.: C
Amendment: /1
Issue Date: February, 1998
SY10E154
SY100E154
BLOCK DIAGRAM
Pin
Function
D
0a
D
4a
Input Data a
D
0b
D
4b
Input Data b
SEL
Data Select Input
LEN
1
, LEN
2
Latch Enables
MR
Master Reset
Q
0
Q
4
True Outputs
Q
0
Q
4
Inverted Outputs
V
CCO
V
CC
to Output
PIN CONFIGURATION
PIN NAMES
V
EE
SEL
LEN
1
D
0a
MR
Q
4
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
D
0b
LEN
2
Q
0
Q
0
Q
3
V
CCO
PLCC
TOP VIEW
J28-1
D
4b
D
3a
D
3b
Q
3
V
CC
Q
2
Q
2
Q
1
Q
1
V
CCO
D
2b
D
2a
D
1b
D
1a
D
4a
Q
4
MR
D
R
D
0a
LEN
1
LEN
2
Q
E
N
Q
MUX
SEL
SEL
D
0b
D
R
D
1a
Q
E
N
Q
MUX
D
1b
D
R
D
2a
Q
E
N
Q
MUX
D
2b
D
R
D
3a
Q
E
N
Q
MUX
D
3b
D
R
D
4a
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
E
N
Q
MUX
D
4b
SEL
SEL
SEL
SEL
1
2
SY10E154
SY100E154
Micrel
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ps
--
t
PHL
D
325
500
700
325
500
700
325
500
700
SEL
475
650
925
475
650
925
475
650
925
LEN
350
500
750
350
500
750
350
500
750
MR
450
600
800
450
600
800
450
600
800
t
S
Set-up Time
ps
--
D
300
100
--
300
100
--
300
100
--
SEL
500
250
--
500
250
--
500
250
--
t
H
Hold Time
ps
--
D
300
100
--
300
100
--
300
100
--
SEL
200
250
--
200
250
--
200
250
--
t
RR
Reset Recovery Time
800
600
--
800
600
--
800
600
--
ps
--
t
PW
Minimum Pulse Width, MR
400
--
--
400
--
--
400
--
--
ps
--
t
skew
Within-Device Skew
--
50
--
--
50
--
--
50
--
ps
1
t
r
Rise/Fall Time
300
475
800
300
475
800
300
475
800
ps
--
t
f
20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
TRUTH TABLES
SEL
Data
H
a
L
b
LEN
1
LEN
2
Latch
L
L
Transparent
H
X
Latched
X
H
Latched
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
A
--
I
EE
Power Supply Current
mA
--
10E
--
76
91
--
76
91
--
76
91
100E
--
76
91
--
76
91
--
87
105
AC ELECTRICAL CHARACTERISTICS
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E154JC
J28-1
Commercial
SY10E154JCTR
J28-1
Commercial
SY100E154JC
J28-1
Commercial
SY100E154JCTR
J28-1
Commercial
4
SY10E154
SY100E154
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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