s
750ps max. LEN to output
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
700ps max. D to output
s
Single-ended outputs
s
Asynchronous Master Reset
s
Dual latch-enables
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E155
s
Available in 28-pin PLCC package
FEATURES
The SY10/100E155 offer six 2:1 multiplexers followed
by latches with single-ended outputs, designed for use in
new, high-performance ECL systems. The two external
latch-enable signals (LEN
1
and LEN
2)
are gated through a
logical OR operation before use as control for the six
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
DESCRIPTION
Rev.: C
Amendment: /1
Issue Date:
February, 1998
6-BIT 2:1
MUX-LATCH
SY10E155
SY100E155
BLOCK DIAGRAM
PIN CONFIGURATION
PIN NAMES
Pin
Function
D
0a
D
5a
Input Data a
D
0b
D
5b
Input Data b
SEL
Data Select Input
LEN
1
, LEN
2
Latch Enables
MR
Master Reset
Q
0
Q
5
Outputs
V
CCO
V
CC
to Output
V
EE
D
5b
LEN
1
SEL
MR
NC
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
D
0b
LEN
2
Q
0
V
CCO
Q
5
D
3a
PLCC
TOP VIEW
J28-1
D
5a
D
3b
D
4a
Q
4
V
CC
Q
3
Q
2
V
CCO
Q
1
D
2b
D
2a
D
1b
D
1a
D
0b
D
4b
V
CCO
D
R
Q
MUX
SEL
D
R
Q
MUX
D
R
Q
MUX
D
R
Q
MUX
D
R
Q
MUX
D
R
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
MUX
MR
D
0a
LEN
1
LEN
2
SEL
D
0b
D
1a
D
1b
D
2a
D
2b
D
3a
D
3b
D
4a
D
4b
D
5a
D
5b
E
N
E
N
E
N
E
N
E
N
E
N
SEL
SEL
SEL
SEL
SEL
1
2
SY10E155
SY100E155
Micrel
TRUTH TABLES
SEL
Data
H
a
L
b
LEN
1
LEN
2
Latch
L
L
Transparent
H
X
Latched
X
H
Latched
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max.
Min. Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
A
--
I
EE
Power Supply Current
mA
--
10E
--
85
102
--
85
102
--
85
102
100E
--
85
102
--
85
102
--
98
117
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ps
--
t
PHL
D
325
500
700
325
500
700
325
500
700
SEL
475
675
925
475
675
925
475
675
925
LEN
350
500
750
350
500
750
350
500
750
MR
450
600
850
450
600
850
450
600
850
t
S
Set-up Time
ps
--
D
300
100
--
300
100
--
300
100
--
SEL
500
250
--
500
250
--
500
250
--
t
H
Hold Time
ps
--
D
300
100
--
300
100
--
300
100
--
SEL
0
250
--
0
250
--
0
250
--
t
RR
Reset Recovery Time
800
650
--
800
650
--
800
650
--
ps
--
t
PW
Minimum Pulse Width, MR
400
--
--
400
--
--
400
--
--
ps
--
t
skew
Within-Device Skew
--
75
--
--
75
--
--
75
--
ps
1
t
r
Rise/Fall Time
300
450
800
300
450
800
300
450
800
ps
--
t
f
20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E155JC
J28-1
Commercial
SY10E155JCTR
J28-1
Commercial
SY100E155JC
J28-1
Commercial
SY100E155JCTR
J28-1
Commercial
4
SY10E155
SY100E155
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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