s
900ps max. D to output
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
800ps max. LEN to output
s
Differential outputs
s
Asynchronous Master Reset
s
Dual latch enables
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E156
s
Available in 28-pin PLCC package
FEATURES
3-BIT 4:1
MUX-LATCH
The SY10/100E156 offer three 4:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
latch enable signals (LEN
1
and LEN
2
) are gated through a
logical OR operation before use as control for the three
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the Select
(SEL
0
, SEL
1
) signals which select one of the four bits of
input data at each mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
DESCRIPTION
Rev.: C
Amendment: /1
Issue Date:
February, 1998
SY10E156
SY100E156
BLOCK DIAGRAM
PIN CONFIGURATION
V
EE
SEL
0
SEL
1
LEN
2
LEN
1
D
2a
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
D
1c
MR
Q
0
V
CCO
Q
2
D
2b
PLCC
TOP VIEW
J28-1
D
1b
D
2c
D
2d
Q
2
V
CC
Q
1
Q
1
V
CCO
Q
0
D
0d
D
0c
D
0b
D
0a
D
1d
D
1a
V
CCO
Pin
Function
D
0x
D
2x
Input Data
SEL
0
, SEL
1
Select Inputs
LEN
1
, LEN
2
Latch Enables
MR
Master Reset
Q
0
Q
2
True Outputs
Q
0
Q
2
Inverted Outputs
V
CCO
V
CC
to Output
PIN NAMES
D
R
E
N
4:1
MUX
D
R
E
N
4:1
MUX
D
R
E
N
4:1
MUX
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
MR
D
0a
LEN
1
LEN
2
SEL
1
D
0b
D
0c
D
0d
D
1a
D
1b
D
1c
D
1d
D
2a
D
2b
D
2c
D
2d
SEL
0
1
2
SY10E156
SY100E156
Micrel
TRUTH TABLES
LEN
1
LEN
2
Latch
L
L
Transparent
H
X
Latched
X
H
Latched
SEL
0
SEL
1
Data
L
L
a
H
L
b
L
H
c
H
H
d
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
A
--
I
EE
Power Supply Current
mA
--
10E
--
75
90
--
75
90
--
75
90
100E
--
75
90
--
75
90
--
86
103
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ps
--
t
PHL
D
400
600
900
400
600
900
400
600
900
SEL
0
550
775
1050
550
775
1050
550
775
1050
SEL
1
450
650
900
450
650
900
450
650
900
LEN
350
500
800
350
500
800
350
500
800
MR
350
600
825
350
600
825
350
600
825
t
S
Set-up Time
ps
--
D
400
275
--
400
275
--
400
275
--
SEL
0
700
300
--
700
300
--
700
300
--
SEL
1
600
400
--
600
400
--
600
400
--
t
H
Hold Time
ps
--
D
300
275
--
300
275
--
300
275
--
SEL
0
100
300
--
100
300
--
100
300
--
SEL
1
200
400
--
200
400
--
200
400
--
t
RR
Reset Recovery Time
800
600
--
800
600
--
800
600
--
ps
--
t
PW
Minimum Pulse Width, MR
400
--
--
400
--
--
400
--
--
ps
--
t
skew
Within-Device Skew
--
50
--
--
50
--
--
50
--
ps
1
t
r
Rise/Fall Time
275
475
700
275
475
700
275
475
700
ps
--
t
f
20% to 80%
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E156JC
J28-1
Commercial
SY10E156JCTR
J28-1
Commercial
SY100E156JC
J28-1
Commercial
SY100E156JCTR
J28-1
Commercial
NOTE:
1. Within-device skew is defined as identical transitions on similar paths
through a device.
4
SY10E156
SY100E156
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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