Pin

Function

IN/IN

Signal Input

Input Enable

D[0:7]

Mux Select Inputs

Q/Q

Signal Output

LEN

Latch Enable

SET MIN

Minimum Delay Set

SET MAX

Maximum Delay Set

CASCADE

Cascade Signal

DESCRIPTION

FEATURES

PIN NAMES

PROGRAMMABLE
DELAY CHIP

PIN CONFIGURATION

Rev.: E

Amendment: /0

Issue Date:

October, 1998

ClockWorksTM

SY10E195

SY100E195

Up to 2ns delay range

Extended 100E V

range of 4.2V to 5.5V

20ps/digital step resolution

>1GHz bandwidth

On-chip cascade circuitry

75Kk

input pulldown resistor

Fully compatible with Motorola MC10E/100E195

Available in 28-pin PLCC package

The SY10/100E195 are programmable delay chips

(PDCs) designed primarily for clock de-skewing and timing
adjustment. They provide variable delay of a differential
ECL input transition.

The delay section consists of a chain of gates

organized as shown in the logic diagram. The first two
delay elements feature gates that have been modified to
have delays 1.25 and 1.5 times the basic gate delay of
approximately 80ps. These two elements provide the
E195 with a digitally-selectable resolution of
approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched
on-chip by a high signal on the latch enable (LEN) control.
If the LEN signal is either LOW or left floating, then the
latch is transparent.

Because the delay programmability of the E195 is

achieved by purely differential ECL gate delays, the
device will operate at frequencies of >1GHz, while
maintaining over 600mV of output swing.

The E195 thus offers very fine resolution, at very high

frequencies, selectable entirely from a digital input,
allowing for very accurate system clock timing.

An eighth latched input, D

, is provided for cascading

multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.

10 11

TOP VIEW

PLCC

J28-1

25 24 23 22 21 20 19

LEN

SET MIN

SET MAX

CASCADE

CCO

ClockWorksTM

SY10E195

SY100E195

Micrel

= 0

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max. Unit

Condition

PLH

Propagation Delay to Output

PHL

IN to Q; Tap = 0

1210

1360

1510

1240

1390

1540

1440

1590

1765

IN to Q; Tap = 127

3320

3570

3820

3380

3630

3880

3920

4270

4720

EN to Q; Tap = 0

1250

1450

1650

1275

1475

1675

1350

1650

1950

to CASCADE

300

450

700

300

450

700

300

450

700

RANGE

Programmable Range

2000

2175

2050

2240

2375

2580

(max.) t

(min.)

Step Delay

High

17.5

High

105

120

High

115

136

180

115

140

180

140

168

205

High

250

272

325

250

280

325

305

336

380

High

505

544

620

515

560

620

672

740

High

1000

1088

1190

1030

1120

1220

1240

1344

1450

Lin

Linearity

skew

Duty Cycle Skew, t

PHL

PLH

Set-up Time

D to LEN

200

D to IN

800

EN to IN

200

Hold Time

LEN to D

500

250

500

250

500

250

IN to EN

Release Time

EN to IN

300

SET MAX to LEN

800

SET MIN to LEN

800

jit

Jitter

Rise/Fall Times

2080% (Q)

125

225

325

125

225

325

125

225

325

2080% (CASCADE)

300

450

650

300

450

650

300

450

650

NOTES:

2. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.

3. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set.

4. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than

75mV to

that IN/IN transition.

5. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than

75mV to that IN/IN transition.

6. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified

IN to Q propagation delay and transition times.

7. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay

control inputs will typically realize D

resolution steps across the specified programmable range.

8. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing

binary counts on the control inputs D

). Typically, the device will be monotonic to the D

input, however, under worst case conditions and process variation,

delays could decrease slightly with increasing binary counts when the D

input is the LSB. With the D

input as the LSB, the device is guaranteed to be

monotonic over all specified environmental conditions and process variation.

9. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

= V

(Min.) to V

(Max.); V

= GND

AC ELECTRICAL CHARACTERISTICS

ClockWorksTM

SY10E195

SY100E195

Micrel

APPLICATIONS INFORMATION

Cascading Multiple E195s

To increase the programmable range of the E195,

internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple E195s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195.
Obviously, cascading multiple PDCs will result in a larger
programmable range; however, this increase is at the
expense of a longer minimum delay.

Figure 1 illustrates the interconnect scheme for

cascading two E195s. As can be seen, this scheme can
easily be expanded for larger E195 chains. The D

input

of the E195 is the cascade control pin. With the
interconnect scheme of Figure 1, when D

is asserted, it

signals the need for a larger programmable range than
is achievable with a single device.

An expansion of the latch section of the block diagram

is pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When
D

of chip #1 above is low, the cascade output will also

be low, while the cascade bar output will be a logical
high. In this condition, the SET MIN pin of chip #2 will
be asserted and, thus, all of the latches of chip #2 will
be reset and the device will be set at its minimum delay.
Since the RESET and SET inputs of the latches are
overriding, any changes on the A

address bus will

not affect the operation of chip #2.

Chip #1, on the other hand, will have both SET MIN

and SET MAX de-asserted so that its delay will be
controlled entirely by the address bus A

. If the delay

needed is greater than can be achieved with 31.75 gate
delays (1111111 on the A

address bus), D

will be

asserted to signal the need to cascade the delay to the
next E195 device. When D

is asserted, the SET MIN

pin of chip #2 will be de-asserted and the delay will be
controlled by the A

address bus. Chip #1, on the

other hand, will have its SET MAX pin asserted, resulting
in the device delay to be independent of the A

address bus.

When the SET MAX pin of chip #1 is asserted, the D

and D

latches will be reset while the rest of the latches

will be set. In addition, to maintain monotonicity, an
additional gate delay is selected in the cascade circuitry.
As a result, when D

of chip #1 is asserted, the delay

increases from 31.75 gates to 32 gates. A 32-gate delay
is the maximum delay setting for the E195.

To expand this cascading scheme to more devices,

one simply needs to connect the D

input and CASCADE

outputs of the current most significant E195 to the new
most significant E195 in the same manner as pictured in
Figure 1. The only addition to the logic is the increase
of one line to the address bus for cascade control of the
second PDC.

Figure 1. Cascading Interconnect Architecture

E196

Chip #1

LEN

VEE

VBB

SET MIN

SET MAX

CASCADE

VCC

VCCO

E196

Chip #2

LEN

VEE

VBB

SET MIN

SET MAX

CASCADE

VCC

VCCO

ADDRESS BUS (A0 A6)

Input

Output

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