s
950ps max. data to output
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
850ps max. latch enable to output
s
Separate select controls
s
Differential outputs
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E256
s
Available in 28-pin PLCC package
FEATURES
3-BIT 4:1
MUX-LATCH
The SY10/100E256 offer three 4:1 multiplexers followed
by latches with differential outputs designed for use in new,
high-performance ECL systems. Separate Select controls
are provided for the leading 2:1 mux pairs (see block
diagram).
When the Latch Enable (LEN) is at a logic LOW, the latch
is transparent and output data is controlled by the multiplexer
select controls. A logic HIGH on LEN latches the outputs.
The Master Reset (MR) overrides all other controls to set
the Q outputs LOW.
DESCRIPTION
SY10E256
SY100E256
Rev.: C
Amendment: /1
Issue Date:
February, 1998
BLOCK DIAGRAM
PIN CONFIGURATION
Pin
Function
D
0x
D
2x
Parallel Data Inputs
SEL
1A
, SEL
1B
First-stage Select Inputs
SEL
2
Second-stage Select Input
LEN
Latch Enable
MR
Master Reset
Q
0
, Q
0
Q
2
, Q
2
Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
TOP VIEW
PLCC
J28-1
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
D
0b
V
CCO
Q
0
D
0a
D
1d
D
0c
D
0d
V
EE
D
1c
SEL
2
MR
LEN
SEL
1A
SEL
1B
V
CCO
D
2c
D
2d
D
1a
D
1b
D
2b
D
2a
V
CC
Q
2
Q
1
V
CCO
Q
2
Q
1
Q
0
D
R
E
N
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
D
R
E
N
D
R
E
N
D
0a
SEL
1B
D
0b
D
0c
D
0d
D
1a
D
1b
D
1c
D
1d
D
2a
D
2b
D
2c
D
2d
SEL
1A
SEL
2
LEN
MR
1
2
SY10E256
SY100E256
Micrel
Pin
State
Operation
SEL
2
H
Output c/d Data
SEL
1A
H
Input d Data
SEL
1B
H
Input b Data
TRUTH TABLE
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ps
--
t
PHL
D
400
600
900
400
600
900
400
600
900
SEL
1
550
775
1050
550
775
1050
550
775
1050
SEL
2
450
650
900
450
650
900
450
650
900
LEN
350
500
800
350
500
800
350
500
800
MR
350
600
825
350
600
825
350
600
825
t
S
Set-up Time
ps
--
D
400
275
--
400
275
--
400
275
--
SEL
1
600
300
--
600
300
--
600
300
--
SEL
2
500
250
--
500
250
--
500
250
--
t
H
Hold Time
ps
--
D
300
275
--
300
275
--
300
275
--
SEL
1
100
300
--
100
300
--
100
300
--
SEL
2
200
250
--
200
250
--
100
250
--
t
RR
Reset Recovery Time
700
600
--
700
600
--
700
600
--
ps
--
t
PW
Minimum Pulse Width, MR
400
--
--
400
--
--
400
--
--
ps
--
t
skew
Within-Device Skew
--
50
--
--
50
--
--
50
--
ps
1
t
r
Rise/Fall Time
275
475
700
275
475
700
275
475
700
ps
--
t
f
20% to 80%
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
I
IH
Input HIGH Current
--
--
150
--
--
150
--
--
150
A
--
I
EE
Power Supply Current
mA
--
10E
--
69
83
--
69
83
--
69
83
100E
--
69
83
--
69
83
--
79
96
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E256JC
J28-1
Commercial
SY10E256JCTR
J28-1
Commercial
SY100E256JC
J28-1
Commercial
SY100E256JCTR
J28-1
Commercial
NOTE:
1. Within-device skew is defined as identical transitions on similar paths
through a device.
4
SY10E256
SY100E256
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
PDF 
ZIP