FEATURES
s
25
cutoff bus output
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
50
receiver output
s
Transmit and receive registers
s
1500ps max. clock to bus
s
1000ps max. clock to Q
s
Internal edge slow-down capacitors on bus outputs
s
Additional package ground pins
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E336
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS
0
- BUS
2
) are designed to drive a 25
bus.
The receive outputs (Q
0
Q
2
) are specified for 50
. The
bus outputs feature a normal logic HIGH level (V
OH
) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to 2.0V and the output emitter-follower is "off",
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to 2.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK
1
or CLK
2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
3-BIT REGISTERED
BUS TRANSCEIVER
PIN CONFIGURATION
Pin
Function
A
0
A
2
Data Inputs A
B
0
B
2
Data Inputs B
TEN
1, 2
Transmit Enable Inputs
RXEN
Receive Enable Input
BUSEN
1, 2
Bus Enable Inputs
CLK
1, 2
Clock Inputs
BUS
0
BUS
2
25
Cutoff Bus Outputs
Q
0
Q
2
Receive Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
SY10E336
SY100E336
Rev.: C
Amendment: /2
Issue Date: February, 1998
TOP VIEW
PLCC
J28-1
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
V
CCO
A
2
B
2
TEN
1
TEN
2
NC
Q
2
V
CC
GND
GND
Q
1
V
CCO
BUS
2
BUS
1
B
1
V
CCO
Q
0
A
1
B
0
GND
BUS
0
V
EE
A
0
CLK
2
CLK
1
BUSEN
1
BUSEN
2
RXEN
1
4
SY10E336
SY100E336
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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