DESCRIPTION

2:1 PECL/ECL multiplexer

Guaranteed ACperformance over temperature/voltage

· >3GHz f

MAX

(toggle)

· <200ps rise/fall time
· <420ps propagation delay (D-to-Q)

Low jitter performance

· Random jitter: <1ps (rms)
· Deterministic jitter: <15ps (pk-pk)
· Total jitter (clock): <1ps (pk-pk)

Flexible supply voltage: 3V to 5.5V

Wide operating temperature range: 40

C to +85

Available in 8-pin MSOP

and SOIC packages

FEATURES

3.3V/5V 3GHz PECL/ECL
2:1 MULTIPLEXER

ECL ProTM

SY10EP58V

SY100EP58V

FINAL

APPLICATIONS

SONET

Gig Ethernet

Fibre Channel

Transponders

Rev.: B

Amendment: /0

Issue Date:

October 2002

The SY10/100EP58V are 3.3V/5V, precision, high-speed,

2:1 multiplexers. Both devices are pin-for-pin, plug-in
replacements for the MC10/100EP58D/DT in 8-pin SOIC
and 6-pin TSSOP (MSOP) packages. The signal-path inputs
(Da and Db) are single-ended PECL/ECL compatible, and
can accept a signal swing as low as 150mV. All I/O pins are
10K/100K EP ECL/PECL compatible.

ACperformance is guaranteed over the industrial 40

to +85

C temperature range and 3.0V to 5.5V supply voltage

range. Maximum throughput (f

MAX

) is guaranteed to be 3GHz

with a differential output swing

400mV. In addition, these

multiplexers are optimized for low-jitter applications. The
SY10EP58V and SY100EP58V are designed to operate in
either ECL/PECL or PECL/LVPECL mode. The
SY100EP58V is internally temperature compensated, thus
is 100K EP ECL/PECL compatible--I/O logic levels remain
constant over temperature.

The SY10/100EP58V is part of Micrel's high-speed,

Precision Edge timing and distribution family. For applications
that require a differential I/O combination, consult the Micrel
website at

www.micrel.com

, and choose from a

comprehensive product line of high-speed, low skew fanout
buffers, translators, and clock dividers.

Micrel Semiconductor

On Semiconductor

Package

SY10EP58VZI

MC10EP58D

8-pin SOIC

SY10EP58VZITR

MC10EP58DR2

8-pin SOIC TR*

SY10EP58VKI

MC10EP58DT

8-pin MSOP/TSSOP

SY10EP58VKITR

MC10EP58DTR2

8-pin MSOP/TSSOP TR*

SY100EP58VZI

MC100EP58D

8-pin SOIC

SY100EP58VZITR

MC100EP58DR2

8-pin SOIC TR*

SY100EP58VKI

MC100EP58DT

8-pin MSOP/TSSOP

SY100EP58VKITR

MC100EP58DTR2

8-pin MSOP/TSSOP TR*

*Tape and Reel

CROSS REFERENCE TABLE

TYPICAL PERFORMANCE

TIME (50ps/div.)

Output Swing

(60mV/div

.
)

2.7Gbps, 2

 1 PRBS

ECL ProTM

ECL Pro is a trademark of Micrel, Inc.

ECL ProTM

SY10EP58V

SY100EP58V

Micrel

PACKAGE/ORDERING INFORMATION

Ordering Information

Package

Operating

Package

Part Number

Type

Range

Marking

SY10EP58VZC

Z8-1

Commercial

HEP58V

SY10EP58VZCTR

(1)

Z8-1

Commercial

HEP58V

SY100EP58VZC

Z8-1

Commercial

EP58V

SY100EP58VZCTR

(1)

Z8-1

Commercial

EP58V

SY10EP58VKC

K8-1

Commercial

HP58V

SY10EP58VKCTR

(1)

K8-1

Commercial

HP58V

SY100EP58VKC

K8-1

Commercial

EP58V

SY100EP58VKCTR

(1,2)

K8-1

Commercial

EP58V

SY10EP58VZI

(2)

Z8-1

Industrial

HEP58V

SY10EP58VZITR

(1,2)

Z8-1

Industrial

HEP58V

SY100EP58VZI

(2)

Z8-1

Industrial

EP58V

SY100EP58VZITR

(1,2)

Z8-1

Industrial

EP58V

SY10EP58VKI

(2)

K8-1

Industrial

HP58V

SY10EP58VKITR

(1,2)

K8-1

Industrial

HP58V

SY100EP58VKI

(2)

K8-1

Industrial

EP58V

SY100EP58VKITR

(1,2)

K8-1

Industrial

EP58V

Note 1.

Tape and Reel.

Note 2.

Recommended for new designs.

Pin Number

Pin Name

Pin Function

No connect.

2, 3

Da, Db

(1)

100KEP PECL/ECL single-ended input channels a and b. Multiplexing of these
inputs are controlled by SEL. The signal inputs include internal 75k

pull-down resistors.

Default condition is LOW when left floating. The input signal should be terminated
externally. See "Termination Recommendations" section.

SEL

100KEP PECL/ECL compatible 2:1 mux select control. See "Mux Select Truth Table."
Enable pin includes an intenal 75k

pull-down resistor. Default condition is LOW.

VEE

Negative Power Supply: For PECL/LVPECL connect to ground. Both V

pins must be

connected together, externally on the PCB, for proper operation.

6, 7

/Q, Q

100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50

resistor to V

2V. Unused single-ended outputs must have a balanced load. For AC

coupled applications, the output stage emitter follower must have a DC current path to
ground. See "Termination Recommendations" section.

VCC

Positive Power Supply. All V

pins must be connected to the same power supply

externally. Bypass with 0.1

F//0.01

F low ESR capacitors.

Note 1.

If the inputs are ACcoupled, teh outputs Q, and /Q will experience duty cycle distoration because the input levels do not track the internal
reference voltage.

PIN DESCRIPTION

SEL

VCC

VEE

MUX

8-Pin MSOP (K8-1)

8-Pin SOIC (Z8-1)

MUX SELECT TRUTH TABLE

SEL1

DATA OUT

ECL ProTM

SY10EP58V

SY100EP58V

Micrel

Absolute Maximum Ratings

(Note 1)

Supply Voltage (V

) ........................................ 6.0V to 0V

Output Current (I

OUT

)

Continuous ............................................................. 50mA
Surge .................................................................... 100mA

Storage Temperature (T

) ....................... 65

C to +150

Operating Ratings

(Note 2)

Supply Voltage |V

| .......................... +3.0V to +5.5V

Ambient Temperature (T

) ......................... 40

C to +85

Package Thermal Resistance

MSOP

(

)

Still-air ........................................................... 206

C/W

500lfpm .......................................................... 155

C/W

SOIC

(

)

Still-air .......................................................... 160

C/W

500lfpm .......................................................... 109

C/W

MSOP

(

) ......................................................... 39

C/W

SOIC

(

) .......................................................... 39

C/W

Note 1.

Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. This is a stress rating only and functional
operation is not implied at conditions other than those detailed in
the operational sections of this data sheet. Exposure to ABSOLUTE
MAXIMUM RATlNG conditions for extended periods may affect
device reliability.

Note 2.

The data sheet limits are not guaranteed if the device is
operated beyond the operating ratings.

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Power Supply Current

(3)

Output HIGH Voltage

(4)

1135

0885

1070

0945

0820

1010

0760

Output LOW Voltage

(4)

1935

1685

1870

1745

1620

1810

1560

Input HIGH Voltage

1210

0885

1145

0820

1085

0760

Input LOW Voltage

1935

1610

1870

1545

1810

1485

Input HIGH Current

150

Input LOW Current

0.5

Note 1.

10KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.

Note 2.

Input and output parameters vary 1:1 with V

Note 3.

= 0V, V

= V

(min) to V

(max), all other pins floating.

Note 4.

All loading with 50

to V

2.0V.

10K DC ELECTRICAL CHARACTERISTICS

(1)

= 3.0V to 5.5V; V

= 0V

(2)

= 0V or V

= 5.5V to 3.0V

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Condition

Power Supply Voltage

(PECL)

4.5

5.0

5.5

4.5

5.0

5.5

4.5

5.0

5.5

(LVPECL)

3.0

3.8

3.0

3.8

3.0

3.8

(ECL)

5.5

5.0

4.5

5.5

5.0

4.5

5.5

5.0

4.5

(LVECL)

3.8

3.3

3.0

3.8

3.3

3.0

3.8

3.3

3.0

Supply Current

No Load

Input HIGH Current

= V

Input LOW Current

All Inputs

0.5

= V

Input Capacitance (MSOP)

1.0

(SOIC)

1.0

Note 1.

100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.

DC ELECTRICAL CHARACTERISTICS

(1)

ECL ProTM

SY10EP58V

SY100EP58V

Micrel

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Condition

Input LOW Voltage

1355

1675

1355

1675

1355

1675

(Single-Ended)

Input HIGH Voltage

2075

2420

2075

2420

2075

2420

(Single-Ended)

Outuput LOW Voltage

1355

1480

1605

1355

1480

1605

1355

1480

1605

to V

Output HIGH Voltage

2155

2280

2405

2155

2280

2405

2155

2280

2405

to V

Output Reference Voltage

1775

1875

1975

1775

1875

1975

1775

1875

1975

IHCMR

Input HIGH Voltage

(2)

2.0

Common Mode Range

Note 1.

= 3.3V. They vary 1:1 with V

Note 2.

The V

IHCMR

range is referenced to the most positive side of the differential input signal.

(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS

(1)

= 3.3V

10%, V

= 0V

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Condition

Input LOW Voltage

3055

3375

3055

3375

3055

3375

(Single-Ended)

Input HIGH Voltage

3775

4120

3775

4120

3775

4120

(Single-Ended)

Outuput LOW Voltage

3055

3180

3305

3055

3180

3305

3055

3180

3305

to V

Output HIGH Voltage

3855

3980

4105

3855

3980

4105

3855

3980

4105

to V

Output Reference Voltage

3475

3575

3675

3475

3575

3675

3475

3575

3675

IHCMR

Input HIGH Voltage

(2)

2.0

Common Mode Range

Note 1.

= 5.0V. They vary 1:1 with V

Note 2.

The V

IHCMR

range is referenced to the most positive side of the differential input signal.

(100KEP) PECL DC ELECTRICAL CHARACTERISTICS

(1)

= 5.0V

10%, V

= 0V

ECL ProTM

SY10EP58V

SY100EP58V

Micrel

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Condition

Input LOW Voltage

1945

1625 1945

1625

Input HIGH Voltage

1225

880

1225

880

1225

880

Outuput LOW Voltage

1945 1820 1695 1945 1820 1695 1945 1820 1695

to V

Output HIGH Voltage

1145 1020

895

1145 1020

895

1145 1020

895

to V

Output Reference Voltage

1525 1425 1325 1525 1425 1325 1525 1425 1325

IHCMR

Input HIGH Voltage

(2)

+2.0

0.0

+2.0

0.0

+2.0

0.0

Common Mode Range

Note 1.

Note 2.

The V

IHCMR

range is referenced to the most positive side of the differential input signal.

(100KEP) ECL/LVECL DC ELECTRICAL CHARACTERISTICS

(1)

= 0V, V

= 5.5V to 3.0V

= 40

= +25

= +85

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Condition

MAX

Max. Toggle Frequency

(1)

GHz

PLH

Propagation Delay (Differential)

PHL

SEL to Q, /Q; D to Q, /Q

170

380

190

230

410

210

420

SKEW

Part-to-Part Skew

(2)

200

JITTER

Cycle-to-Cycle Jitter (rms)

(3)

0.2

pk-pk

Random Jitter

(4)

pk-pk

Note 3

Deterministic Jitter

(5)

@1.25Gbps

<15

pk-pk

Note 4

@2.5Gbps

<25

Total Jitter

(6)

pk-pk

Differential Input Voltage Range

150

800

1200

150

800

1200

150

800

1200

Output Rise/Fall Time Q, /Q

170

140

180

200

(20% to 80%)

Note 1.

Measured with 750mV input signal, 50% duty cycle. Output swing

400mV. All loading with a 50

to V

2.0V.

Note 2.

Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are
measured from the cross point of the inputs to the cross point of the outputs.

Note 3.

The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. t

JITTER_CC

= t

+ 1, where t is the time

between rising edges of the output signal.

Note 4.

RJ is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 2.5Gbps.

Note 5.

DJ is measured at 1.25Gbps and 2.5Gbps, with both K28.5 and 2

1 PRBS pattern.

Note 6.

Total Jitter is defined as an ideal clock input, no more than 1 output edge in 10

output edges will deviate by more than specifed peak-to-peak

jitter value.

AC ELECTRICAL CHARACTERISTICS

= 3.0V to 5.5V, V

= 0V or V

= 0V; V

= 3.0V to 5.5V

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