DESCRIPTION
FEATURES
s
9-bit ideal for byte-parity applications
s
Flow-through configuration
s
Extra TTL and ECL power/ground pins to minimize
switching noise
s
ECL and TTL enable inputs
s
Dual supply
s
3.5ns max. D to Q
s
PNP TTL inputs for low loading
s
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s
Fully compatible with Motorola MC10H/100H600
s
Available in 28-pin PLCC package
The SY10/100H600 are 9-bit, dual supply TTL-to-ECL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The H600 features both ECL and TTL logic enable
controls for maximum flexibility.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
9-BIT TTL-TO-ECL WITH
TTL, ECL ENABLE
SY10H600
SY100H600
BLOCK DIAGRAM
Rev.: D
Amendment: /0
Issue Date: February, 1998
PIN CONFIGURATION
18
17
16
15
14
13
12
Q
8
Q
7
V
CCO
Q
6
V
EE
Q
5
Q
4
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
25 24 23 22 21 20 19
V
CCT
D
3
D
2
D
1
D
5
D
4
D
0
D
6
D
7
D
8
GND
ENTTL
NC
ENECL
Q
0
Q
1
V
CCE
V
CCO
Q
2
V
CCO
Q
3
Pin
Function
GND
TTL Ground (0V)
V
CCE
ECL V
CC
(0V)
V
CCO
ECL V
CC
(0V) -- Outputs
V
CCT
TTL Supply (+5.0V)
V
EE
ECL Supply (5.2/4.5V)
D
0
D
8
Data Inputs (TTL)
Q
0
Q
8
Data Outputs (ECL)
ENECL
Enable Control (ECL)
ENTTL
Enable Control (TTL)
PIN NAMES
Q
0
D
0
TTL
ECL
ENECL
ENTTL
Q
1
D
1
Q
2
D
2
Q
3
D
3
Q
4
D
4
Q
5
D
5
Q
6
D
6
Q
7
D
7
Q
8
D
8
1
2
SY10H600
SY100H600
Micrel
LOGIC DIAGRAM
DC ELECTRICAL CHARACTERISTICS
V
CCT
= 5.0V
10%; V
EE
= 4.75V to 5.5V (10H Version); V
EE
= 4.2V to 5.5V (100H Version)
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
I
EE
Power Supply Current,
mA
--
ECL
10H
--
125
--
125
--
125
100H
--
122
--
123
--
132
I
CCH
Power Supply Current,
--
48
--
48
--
48
mA
--
I
CCL
TTL
--
50
--
50
--
50
LOGIC DIAGRAM
AC ELECTRICAL CHARACTERISTICS
V
CCT
= 5.0V
10%; V
EE
= 4.75V to 5.5V (10H Version); V
EE
= 4.2V to 5.5V (100H Version)
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
t
PLH
Propagation Delay to Output
ns
50
to 2.0V
t
PHL
D
1.4
3.0
1.5
3.2
1.7
3.5
ENECL/ENTTL
1.8
3.7
1.9
3.9
2.0
4.1
t
r
Output Rise/Fall Time
0.5
1.5
0.5
1.5
0.5
1.5
ns
50
to 2.0V
t
f
20% to 80%, 80% to 20%
LOGIC DIAGRAM
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10H600JC
J28-1
Commercial
SY10H600JCTR
J28-1
Commercial
SY100H600JC
J28-1
Commercial
SY100H600JCTR
J28-1
Commercial
LOGIC DIAGRAM
TRUTH TABLE
ENECL
ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
4
SY10H600
SY100H600
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2000 Micrel Incorporated
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