The SY89429A is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a
range of frequencies from 400MHz to 800MHz. The
differential PECL output can be configured to be the VCO
frequency divided by 2, 4, 8 or 16. With the output configured
to divide the VCO frequency by 2, and with a 16MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz
steps.
FEATURES
DESCRIPTION
Rev.: H
Amendment: /0
Issue Date:
October, 1998
ClockWorksTM
SY89429A
PROGRAMMABLE
FREQUENCY SYNTHESIZER
(25MHz to 400MHz)
s
Improved jitter performance over SY89429
s
25MHz to 400MHz differential PECL outputs
s
25ps peak-to-peak output jitter
s
Minimal frequency over-shoot
s
Synthesized architecture
s
Serial 3 wire interface
s
Parallel interface for power-on
s
Internal quartz reference oscillator driven by quartz
crystal or PECL source
s
PECL output can operate with either +3.3V or +5V
VCC_OUT power supply
s
External loop filter optimizes performance/cost
s
Applications note (AN-06) for ease of design-ins
s
Available in PLCC and SOIC 28-pin packages
PIN CONFIGURATION
APPLICATIONS
s
Workstations
s
Advanced communications
s
High end consumer
s
High-performance computing
s
RISC CPU clock
s
Graphics pixel clock
s
Test equipment
s
Other high-performance processor-based
applications
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21
20 19
5
6
7
8
9
10 11
V
CC_QUIET
XTAL1
S
_CLOCK
S
_DATA
LOOP_
REF
S
_LOAD
LOOP
_FILTER
V
CC1
M[3]
M[0]
M[1]
M[2]
XTAL2
P
_LOAD
M[8]
M[4]
M[7]
M[5]
N[1]
M[6]
N[0]
FOUT
V
CC_OUT
TEST
GND
V
CC
(TTL)
GND (TTL)
FOUT
PLCC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
28
26
25
24
23
22
21
20
19
18
17
16
15
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
M[8]
N[0]
N[1]
GND (TTL)
TEST
V
CC
(TTL)
P
_LOAD
V
CC1
XTAL
2
XTAL
1
LOOP
_REF
LOOP
_FILTER
V
CC_QUIET
S
_LOAD
S
_DATA
S
_CLOCK
V
CC_OUT
FOUT
FOUT
GND
TOP VIEW
SOIC
Z28-1
1
2
ClockWorksTM
SY89429A
Micrel
BLOCK DIAGRAM
DETAILED BLOCK DIAGRAM
NOTE:
Pin numbers reference PLCC pinout.
+5.0V
PHASE DETECTOR
PLL
VCO
N
F
REF
PECL
400 800
MHz
TEST
CONFIG INFO
3 WIRE
INTERFACE
10-25MHz
Fundamental
Crystal
or
PECL
Source
FOUT
OSC
INTERFACE
LOGIC
SERIAL
PARALLEL
8
M
+5.0V
PHASE DETECTOR
8
OSC
FREF
FOUT
VCO
400-800
MHz
V
CC_QUIET
2
3
1
XTAL1
XTAL2
25
V
CC_OUT
FOUT
24
23
LATCH
3-BIT SR
0
1
0
1
6, 21
8 -> 16
9
M[8:0]
17,18
N[1:0]
19,22
S_
CLOCK
S_
DATA
P_
LOAD
S_
LOAD
4
5
28
7
27
26
1025MHz
Fundamental
Crystal
or
PECL
Source
V
CC1
N
(2,4,8,16)
2
1
0
9-BIT M
COUNTER
LATCH
LATCH
2-BIT SR
9-BIT SR
TEST
20
T110
+5.0V
+5.0V
L = LATCH
H = Transparent
LOOP_REF
LOOP_FILTER
7
FOUT 4 --
S_
CLOCK
M --
LOW --
FOUT --
M --
FREF --
HIGH --
6
5
4
3
2
1
0
3
ClockWorksTM
SY89429A
Micrel
INPUTS
XTAL1, XTAL2
These pins form an oscillator when connected to an external
crystal. The crystal is series resonant. Alternatively, these
pins can be driven with 100K PECL level by an external
source.
S_
LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S_
LOAD
for proper operation.
S_
DATA
This TTL pin is the input to the serial configuration shift
registers.
S_
CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_
DATA
is sampled.
P_
LOAD
This TTL pin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when this
signal is LOW; thus, the parallel data must be stable on the
LOW-to-HIGH transition of P_
LOAD
for proper operation.
M[8:0]
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of P_
LOAD
.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of P_
LOAD
.
OUTPUTS
FOUT, FOUT
These differential positive-referenced ECL signals (PECL)
are the output of the synthesizer.
TEST
The function of this TTL output is determined by the serial
configuration bits T[2:0].
POWER
V
CC1
This is the positive supply for the chip and is normally connected
to +5.0V.
V
CC_OUT
This is the positive reference for the PECL outputs, FOUT and
FOUT. It is constrained to be less than or equal to
VCC1
.
V
CC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
OTHER
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
PIN DESCRIPTIONS
N[1:0]
Output Division
0 0
2
0 1
4
1 0
8
1 1
16
4
ClockWorksTM
SY89429A
Micrel
in 50
. The positive reference for the output driver is provided by
a dedicated power pin (V
CC_OUT
) to reduce noise and provide
application flexibility.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally upon system
reset, the P_
LOAD
input is held LOW until sometime after
power becomes valid. With S_
LOAD
held LOW, on the LOW-
to-HIGH transition of P_
LOAD
, the parallel inputs are captured.
The parallel interface has priority over the serial interface.
Internal pull-up resistors are provided on the M[8:0] and N[1:0]
inputs to reduce component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S_
CLOCK
input. The serial input S_
DATA
must meet set-up and
hold timing as specified in the AC parameters section of this data
sheet. With P_
LOAD
held HIGH, the configuration latches will
capture the value in the shift register on the HIGH-to-LOW edge
of the S_
LOAD
input. See the programming section for more
information.
The TEST output reflects various internal node values and is
controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
Symbol
Parameter
Value
Unit
V
CC
Power Supply Voltage
0.5 to +7.0
V
V
I
Input Voltage
0.5 to +7.0
V
I
OUT
Output Source
Continuous
50
mA
Surge
100
T
store
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +75
C
WITH 16MHZ INPUT
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may
affect device reliability.
The internal oscillator uses the external quartz crystal as the
basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference frequency
of 2MHz.
The VCO within the PLL operates over a range of 400
800MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
The phase detector and loop filter force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low) the PLL will not achieve loop lock. External loop
filter components are utilized to allow for optimal phase jitter
performance.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. The output
divider is configured through either the serial or the parallel
interfaces and can provide one of four divider ratios (2, 4, 8 or 16).
This divider extends the performance of the part while providing
a 50% duty cycle.
The output driver is driven differentially from the output divider
and is capable of driving a pair of transmission lines terminated
FUNCTIONAL DESCRIPTION
VCO Frequency
256
128
64
32
16
8
4
2
1
(MHz)
M Count
M8
M7
M6
M5
M4
M3
M2
M1
M0
400
200
0
1
1
0
0
1
0
0
0
402
201
0
1
1
0
0
1
0
0
1
404
202
0
1
1
0
0
1
0
1
0
406
203
0
1
1
0
0
1
0
1
1
794
397
1
1
0
0
0
1
1
0
1
796
398
1
1
0
0
0
1
1
1
0
798
399
1
1
0
0
0
1
1
1
1
800
400
1
1
0
0
1
0
0
0
0
5
ClockWorksTM
SY89429A
Micrel
M,N
S
_CLOCK
S
_DATA
S
_LOAD
P
_LOAD
M[8:0]
N[1:0]
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
PROGRAMMING INTERFACE
Programming the device is accomplished by properly
configuring the internal dividers to produce the desired
frequency at the outputs. The output frequency can be
represented by this formula:
Where F
XTAL
is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200
M
400 for a 16MHz input reference.
M[8:0] and N[1:0] are normally specified once at power-on,
through the parallel interface, and then possibly again through
the serial interface. This approach allows the designer to bring
up the application at one frequency and then change or fine-
tune the clock, as the ability to control the serial interface
becomes available. To minimize transients in the frequency
domain, the output should be varied in the smallest step size
possible.
The TEST output provides visibility for one of several
internal nodes (as determined by the T[1:0] bits in the serial
configuration stream). It is not configurable through the parallel
interface. Although it is possible to select the node that
represents FOUT, the TTL output may not be able to toggle
fast enough for some of the higher output frequencies. The T2,
T1, T0 configuration latches are preset to 000 when P_LOAD
is low, so that the FOUT outputs are as jitter-free as possible.
The serial configuration port can be used to select one of the
alternate functions for this pin.
The Test register is loaded with the first three bits, the N
register with the next two and the M register with the final eight
bits of the data stream on the S_
DATA
input. For each register
the most significant bit is loaded first (T2, N1 and M8).
When T[2:0] is set to 100 the SY89429A is placed in PLL
bypass mode. In this mode the S_
CLOCK
input is fed directly
into the M and N dividers. The N divider drives the FOUT
differential pair and the M counter drives the TEST output pin.
In this mode the S_
CLOCK
input could be used for low speed
board level functional test or debug. Bypassing the PLL and
driving FOUT directly gives the user more control on the test
clocks sent through the clock tree (See detailed Block Diagram).
Because the S_
CLOCK
is a TTL level the input frequency is
limited to 250MHz or less. This means the fastest the FOUT
pin can be toggled via the S_
CLOCK
is 125MHz as the
minimum divide ratio of the N counter is 2. Note that the M
counter output on the TEST output will not be a 50% duty cycle
due to the way the divider is implemented.
Input S_
DATA
to M0 then M1, then M2, etc., as indicated above.
First
Bit
Last
Bit
T2
T1
T0
TEST
FOUT / FOUT
0
0
0
Data Out Last Bit SR
FVCO
N
0
0
1
HIGH
FVCO
N
0
1
0
FREF
FVCO
N
0
1
1
M Counter Output
FVCO
N
1
0
0
FOUT
FVCO
N
1
0
1
LOW
FVCO
N
1
1
0
S_
CLOCK
M
S_
CLOCK
N
1
1
1
FOUT
4
FVCO
N
FOUT = ( ) x
FXTAL
8
M
N
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