SY89845U
Precision CML Runt Pulse Eliminator 2:1 MUX
with 1:2 Fanout and Internal Termination
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
Micro
LeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
May 2005
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
General Description
The SY89845U is a low jitter CML, 2:1 differential
input multiplexer (MUX) optimized for redundant
source switchover applications. Unlike standard
multiplexers, the SY89845U unique 2:1 Runt Pulse
Eliminator (RPE) MUX prevents any short cycles or
"runt" pulses during switchover. In addition, a unique
Fail-Safe Input protection prevents metastable
conditions when the selected input clock fails to a
DC voltage (voltage between the pins of the
differential input drops below 100mV).
The differential input includes Micrel's unique, 3-pin
input termination architecture that allows customers
to interface to any differential signal (AC- or DC-
coupled) as small as 100mV (200mV
PP
) without any
level shifting or termination resistor networks in the
signal path. The outputs are 400mV CML with fast
rise/fall times guaranteed to be less than 80ps.
The SY89845U operates from a 2.5V 5% or 3.3V
10% supply and is guaranteed over the full
industrial temperature range of 40C to +85C. The
SY89845U is part of Micrel's high-speed, Precision
Edge
product line.
All support documentation can be found on Micrel's
web site at:
www.micrel.com
.
Precision Edge
Features
Selects between two sources, and provides a glitch-
free, stable CML output
Guaranteed AC performance over temperature and
supply voltage:
Wide operating frequency: 1kHz to >1.5GHz
< 840ps In-to-Out t
pd
< 80ps t
r
/t
f
Unique, patent-pending input isolation design
minimizes crosstalk
Fail-Safe Input prevents oscillations
Ultra-low jitter design:
<1ps
RMS
random jitter
<1ps
RMS
cycle-to-cycle jitter
<10ps
PP
total jitter (clock)
<0.7ps
RMS
MUX crosstalk induced jitter
Unique patented input termination and VT pin accepts
DC- and AC-coupled inputs (CML, PECL, LVDS)
400mV CML output swing
2.5V 5% or 3.3V 10% supply voltage
-40C to +85C industrial temperature range
Available in 24-pin (4mm x 4mm) MLFTM package
Applications
Redundant clock switchover
Fail-safe clock protection
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
Micrel,
Inc.
SY89845U
May 2005
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
2
Typical Application
Simplified Example Illustrating Runt Pulse Eliminator
(RPE) when Primary Clock Fails
Micrel,
Inc.
SY89845U
May 2005
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
3
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY89845UMG MLF-24 Industrial
SY89845U with Pb-Free bar-line
Indicator
NiPdAu
Pb-Free
SY89845UMGTR
(2)
MLF-24
Industrial
SY89845U with Pb-Free bar-line
Indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25C, DC Electricals Only.
2. Tape
and
Reel.
Pin Configuration
24-Pin MLFTM (MLF-24)
Micrel,
Inc.
SY89845U
May 2005
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
4
Pin Description
Pin Number
Pin Name
Pin Function
5, 2
23, 20
IN0, /IN0,
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV
(200mV
pp
). Each pin of a pair internally terminates to a VT
pin through 50.
Please refer to the "Input Interface Applications" section for more details.
3, 21
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to V
CC
1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01F low ESR capacitor to VCC. Due to the limited drive
capability, the VREF-AC pin is only intended to drive its respective VT pin.
Maximum sink/source current is 1.5mA. Please refer to the "Input Interface
Applications" section for more details.
4, 22
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. Please refer to the "Input Interface Applications"
section for more details.
1, 6, 9, 10
13, 19, 24
VCC
Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors as close
to the VCC pins as possible.
7, 8, 11, 12
Q0, /Q0
Q1, /Q1
Differential Outputs: These differential CML outputs are a logic function of the
IN0, IN1, and SEL inputs. Please refer to the "Truth Table" below for details.
15 SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k pull-up resistor
and will default to logic HIGH state if left open.
14, 17, 18
GND,
Exposed Pad
Ground: Ground and exposed pad must be connected to the same ground plane.
16 CAP
Power-On Reset (POR) initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure
the internal RPE logic starts up in a known state. See "Power-On Reset (POR)
Description" section for more details regarding capacitor selection. If this pin is
tied directly to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. The CAP pin should never be left open.
Truth Table
Inputs Outputs
IN0 /IN0 IN1 /IN1 SEL Q /Q
0 1 X X 0 0 1
1 0 X X 0 1 0
X X 0 1 1 0 1
X X 1 0 1 1 0
Micrel,
Inc.
SY89845U
May 2005
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
5
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ..........................0.5V to +4.0V
Input Voltage (V
IN
) ..................................0.5V to V
CC
CML Output Voltage (V
OUT
) .. V
CC
1.0V to V
CC
+0.5V
Input Current (I
IN
) ........................................................
Source/Sink Current on IN, /IN ................ 50mA
Source/Sink Current on V
T
..................... 100mA
V
REF-AC
Current
Source/Sink Current on V
REF-AC
.................. 2mA
Lead Temperature (soldering, 20 sec.) ..........+260C
Storage Temperature (T
s
)..................65C to 150C
Operating Ratings
(2)
Supply Voltage (V
CC
).................. +2.375V to +2.625V
......................................................+3.0V to +3.6V
Ambient Temperature (T
A
)................ 40C to +85C
Package Thermal Resistance
(3)
MLFTM (
JA
)
Still-Air ..................................................... 50C/W
MLFTM (
JB
)
Junction-to-Board .................................... 30C/W
DC Electrical Characteristics
(4)
T
A
= 40C to +85C, unless otherwise stated.
Symbol Parameter
Condition
Min
Typ
Max
Units
V
CC
Power
Supply
2.375
3.0
2.5
3.3
2.625
3.6
V
V
I
CC
Power Supply Current
No load, max V
CC
110
140
mA
R
IN
Input Resistance
(IN-to-V
T
)
45 50 55
R
DIFF_IN
Differential Input Resistance
(IN-to-/IN)
90
100
110
V
IH
Input High Voltage
(IN, /IN)
1.2
V
CC
V
V
IL
Input Low Voltage
(IN, /IN)
0
V
IH
0.1 V
V
IN
Input Voltage Swing
(IN, /IN)
See Figure 1a. Note 5.
0.1
V
CC
V
V
DIFF_IN
Differential Input Voltage Swing
|IN-/IN|
See Figure 1b.
0.2
V
V
IN_FSI
Input Voltage Threshold that
Triggers FSI
30
100
mV
V
T_IN
IN-to-V
T
(IN, /IN)
1.28
V
V
REF-AC
Output Reference Voltage
V
CC
1.3 V
CC
1.2 V
CC
1.1 V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
JA
and
JB
values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V
IN
(max) is specified when V
T
is floating.
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