DESCRIPTION
I Two matched-delay outputs:
Bank A: undivided pass-through (QA)
Bank B: programmable divide by
2, 4, 8, 16 > (QB0, QB1)
I Matched delay: all outputs have matched delay,
independent of divider setting
I Guaranteed AC performance:
> 2.5GHz f
MAX
< 250ps t
r
/t
f
< 670ps T
pd
(matched delay)
< 15ps within-device skew
I Low jitter design
< 1ps (rms) cycle-to-cycle jitter
< 10ps (pk-pk) total jitter
I Power supply 3.3V or 2.5V
I Unique input termination and V
T
pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
I TTL/CMOS inputs for select and reset
I 100K EP compatible LVPECL outputs
I Parallel programming capability
I Wide operating temperature range: 40
C to +85
C
I Available in 16-pin (3mm 3mm) MLFTM package
FEATURES
2.5GHz ANY DIFF. IN-TO-LVPECL
PROGRAMMABLE CLOCK DIVIDER/FANOUT
BUFFER WITH INTERNAL TERMINATION
Precision EdgeTM
SY89871U
FINAL
APPLICATIONS
I OC-3 to OC-192 SONET/SDH applications
I Transponders
I Oscillators
I SONET/SDH line cards
1
Rev.: B
Amendment: /1
Issue Date:
February 2003
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a V
T
pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output
banks. Bank A (QA) is a frequency-matched copy of the
input. Bank B (QB0, QB1) is a divided down output of the
input frequency. Bank A and Bank B maintain a matched
delay independent of the divider setting.
FUNCTIONAL BLOCK DIAGRAM
Precision EdgeTM
TYPICAL PERFORMANCE
Precision Edge is a trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
IN
50
50
/IN
S0
S1
QB1
/QB1
QB0
/QB0
QA
/QA
/RESET
V
T
V
REF-AC
Divided
by
2, 4, 8
or 16
Decoder
/QB0
QB0
/QA
QA
QA@622MHz and QB@155.5MHz
4
622MHz
Output
155.5MHz
Output
2
Precision EdgeTM
SY89871U
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY89871UMI
MLF-16
Industrial
SY89871U
SY89871UMITR*
MLF-16
Industrial
SY89871U
*Tape and Reel
Pin Number
Pin Name
Pin Function
1, 2, 3, 4
QB0, /QB0
Differential Buffered Output Clocks: This differential output is a divided-down version of the input
QB1, /QB1
frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16. See "Truth
Table." Unused output pairs may be left floating.
5, 6
QA, /QA
Differential Buffered Undivided Output Clock.
7, 14
VCC
Positive Power Supply: Bypass with 0.1
F//0.01F low ESR capacitors.
8
/RESET
Output Reset: Internal 25k
pull-up. Logic LOW will reset the divider select. See "Truth Table."
Input threshold is V
CC
/2.
12, 9
IN, /IN
Differential Input: Internal 50
termination resistors to V
T
input. See "Input Interface Applications"
section.
10
VREF-AC
Reference Voltage: Equal to V
CC
1.4V (approx.), and used for AC-coupled applications.
Maximum sink/source current is 0.5mA. See "Input Interface Applications" section.
11
VT
Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise, see "Input
Interface Application" section.
13
GND
Ground.
15, 16
S1, S0
Select Pins: See "Truth Table." LVTTL/CMOS logic levels. Internal 25k
pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is V
CC
/2.
PIN DESCRIPTION
1
2
3
4
12
11
10
9
16 15 14 13
5
6
7
8
QB0
/QB0
QB1
/QB1
IN
VT
VREF-AC
/IN
GND
VCC
S1
S0
/RESET
VCC
/QA
QA
16-Pin MLFTM
/RESET
S1
S0
Bank A Output
Bank B Outputs
1
0
0
Input Clock
Input Clock
2
1
0
1
Input Clock
Input Clock
4
1
1
0
Input Clock
Input Clock
8
1
1
1
Input Clock
Input Clock
16
0
X
X
Input Clock
QB = LOW, /QB = HIGH
TRUTH TABLE
3
Precision EdgeTM
SY89871U
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) .................................. 0.5V to +4.0V
Input Voltage (V
IN
) ............................... 0.5V to V
CC
+0.3V
ECL Output Current (I
OUT
)
Continuous ......................................................... 50mA
Surge ................................................................ 100mA
V
T
Current (I
VT
) ......................................................
100mA
Input Current IN, /IN (I
IN
) ..........................................
50mA
V
REF-AC
Sink/Source Current (I
VREF-AC
), Note 3 .......
2mA
Lead Temperature (soldering, 10sec.) ...................... 220
C
Storage Temperature (T
S
) ....................... 65
C to +150C
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) ............................ +2.375V to +3.63V
Ambient Temperature (T
A
) ......................... 40
C to +85C
Package Thermal Resistance
MLFTM
(
JA
)
Still-Air ............................................................. 60
C/W
500lfpm ............................................................ 54
C/W
MLFTM
(
JB
), Note 4
Junction-to-Board ............................................ 32
C/W
T
A
= 40
C to +85C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply Voltage
2.375
3.63
V
I
CC
Power Supply Current
No load, max V
CC
50
75
mA
R
IN
Differential Input Resistance,
80
100
120
(IN, /IN)
V
IH
Input HIGH Voltage, (IN, /IN)
Note 3
0.1
V
CC
+0.3
V
V
IL
Input LOW Voltage, (IN, /IN)
Note 3
0.3
V
CC
+0.2
V
V
IN
Input Voltage Swing
Notes 3, 4
0.1
3.6
V
V
DIFF_IN
Differential Input Voltage Swing
Notes 3, 4, 5
0.2
V
|I
IN
|
Input Current, (IN, /IN)
Note 3
45
mA
V
REF-AC
Reference Voltage
Note 6
V
CC
1.525 V
CC
1.425 V
CC
1.325
V
Note 1.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2.
Specification for packaged product only.
Note 3.
Due to the internal termination (see "Input Stucture Buffer") the input current depends on the applied voltages at IN, /IN and V
T
inputs. Do not apply
a combination of voltages that causes the input current to exceed the maximum limit.
Note 4.
See "Timing Diagram" for V
IN
definition. V
IN
(max.) is specified when V
T
is floating.
Note 5.
See "Typical Operating Characteristics" section for V
DIFF
definition.
Note 6.
Operating using V
IN
is limited to AC-coupled PECL or CML applications only. Connect directly to V
T
pin.
DC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3.
Due to the limited drive capability use for input of the same package only.
Note 4.
Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
4
Precision EdgeTM
SY89871U
Micrel
V
CC
= 3.3V
10% or 2.5V 5%; T
A
= 40
C to +85C
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
I
IH
Input HIGH Current
125
20
A
I
IL
Input LOW Current
300
A
Note 1.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2.
Specification for packaged product only.
LVTTL/LVCMOS DC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
V
CC
= 3.3V
10% or 2.5V 5%; T
A
= 40
C to +85C, R
L
= 50
to V
CC
2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output HIGH Voltage
V
CC
1.145 V
CC
1.020 V
CC
0.895
V
V
OL
Output LOW Voltage
V
CC
1.945 V
CC
1.820 V
CC
1.695
V
V
OUT
Output Voltage Swing
550
800
1050
mV
V
DIFF_OUT
Differential Output Voltage Swing
1.10
1.6
210
V
Note 1.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameters are for
V
CC
= 2.5V. They vary 1:1 with V
CC
.
Note 2.
Specification for packaged product only.
(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
5
Precision EdgeTM
SY89871U
Micrel
TIMING DIAGRAM
V
IN
Swing
/RESET
IN
/IN
/QB
QB
QA
/QA
t
PD
t
RR
V
CC/2
V
OUT
Swing
V
CC
= 3.3V
10% or 2.5V 5%; T
A
= 40
C to +85C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Output Toggle Frequency
Output Swing
400mV
2.5
GHz
Maximum Input Frequency
Note 3
3.2
GHz
t
PLH
Differential Propagation Delay
Input Swing < 400mV
460
580
710
ps
t
PHL
IN-to-QA or QB
Input Swing
400mV
420
550
670
ps
t
SKEW
Within-Device Skew (Differential)
Note 4
7
15
ps
QB0-to-QB1
Within-Device Skew (Differential)
Note 4
12
30
ps
QA-to-QB
Part-to-Part Skew (Differential)
Note 4
250
ps
T
jitter
Cycle-to-Cycle Jitter
Note 5
1
ps(rms)
Total Jitter
Note 6
10
ps(pk-pk)
t
RR
Reset Recovery Time
600
ps
t
r
,
t
f
Output Rise/Fall Times
70
150
250
ps
(20% to 80%)
Note 1.
Measured with 400mV input signal, 50% duty cycle, all loading with 50
to V
CC
2V, unless otherwise stated.
Note 2.
Specification for packaged product only.
Note 3.
Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output
2, 4, 8, 16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
Note 4.
Skew is measured between outputs under identical transitions.
Note 5.
Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
jitter_cc
=T
n
T
n+1
,
where T is the time between rising edges of the output signal.
Note 6.
Total jitter definition: with an ideal clock input, of frequency
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
(NOTE 1)
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