May 1997
ML4819
*
Power Factor and PWM Controller "Combo"
1
GENERAL DESCRIPTION
The ML4819 is a complete boost mode Power factor
Controller (PFC) which also contains a PWM controller.
The PFC circuit is similar to the ML4812 while the PWM
controller can be used for current or voltage mode control
for a second stage converter. Since the PWM and PFC
circuits share the same oscillator, synchronization of the
two stages is inherent. The outputs of the controller IC
provide high current (>1A peak) and high slew rate to
quickly charge and discharge MOSFET gates. Special care
has been taken in the design of the ML4819 to increase
system noise immunity.
The PFC section is of the peak current sensing boost type,
using a current sense transformer or current sensing
MOSFETs to non-dissipatively sense switch current. This
gives the system overall efficiency over average current
sensing control method.
The PWM section includes cycle by cycle current limiting,
* Some Packages Are Obsolete
precise duty cycle limiting for single ended converters,
and slope compensation.
BLOCK DIAGRAM
+
R
T
I
SENSE
B
I
SENSE
A
INV A
OVP
EA OUT A
I
SINE
RAMP COMP
C
T
ERROR
AMP
+
5V
I
EA
I
MULT
OSC
SLOPE
COMPENSATION
UNDER
VOLTAGE
LOCKOUT
S
R
Q
S
R
Q
DUTY CYCLE
I
LIM
PWM B
OUT B
PGND B
PGND A
V
REF
V
CC
V
CC
V
CC
GND
OUT A
GM OUT
5V
5V
0.7V
1V
10
20
12
7
11
9
8
14
18
17
16
15
13
1
3
2
5
4
6
19
GAIN MODULATOR
PWM
CONTROLLER
POWER FACTOR
CONTROLLER
+
+
+
+
FEATURES
s
Two 1A peak current totem-pole output drivers
s
Precision buffered 5V reference (1%)
s
Large oscillator amplitude for better noise immunity
s
Precision duty cycle limit for PWM section
s
Current input gain modulator improves noise immunity
s
Programmable Ramp Compensation circuit
s
Over-Voltage comparator helps prevent output
"runaway"
s
Wide common mode range in current sense
compensators for better noise immunity
s
Under-Voltage Lockout circuit with 6V hysteresis
Please See Ml48
24 for New Designs
ML4819
2
PIN CONFIGURATION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
I
SENSE
A
Input form the PFC current sense
transformer to the PWM comparator
(+). Current Limit occurs when this
point reaches 5V.
2
OVP
Input to Over-Voltage comparator.
3
GM OUT
Output of Gain Modulator. A resistor
to ground on this pin converts the
current to a voltage.
4
EA OUT A
Output of error amplifier.
5
INV A
Inverting input to error amplifier.
6
I
SINE
Current Multiplier input.
7
DUTY CYCLE PWM controller duty cycle is limited
by setting this pin to a fixed voltage.
8
PWM B
Error voltage feedback input.
9
I
SENSE
B
Input for Current Sense resistor for
current mode operation or for
Oscillator ramp for voltage mode
operation.
10 R
T
Oscillator timing resistor pin. A 5V
source across this resistor sets the
charging current for C
T
11 I
LIM
Cycle by cycle PWM current limit.
Exceeding 1V threshold on this pin
terminates the PWM cycle.
12 RAMP COMP Buffered output from the Oscillator
Ramp (C
T
). A resistor to ground sets a
current, 1/2 of which is sourced on
pins 9 and 11.
13 GND B
Return for the high current totem pole
output of the PWM controller.
14 OUT B
PWM controller totem pole output.
15 V
CC
Positive Supply for the IC.
16 OUT A
PFC controller totem pole output.
17 GND A
Return for the high current totem pole
output of the PFC controller.
18 V
REF
Buffered output for the 5V voltage
reference
19 GND
Analog signal ground.
20 C
T
Timing Capacitor for the Oscillator.
PIN DESCRIPTION
ML4819
20-Pin PDIP
I
SENSE
A
OVP
GM OUT
EA OUT A
INV A
I
SINE
DUTY CYCLE
PWM B
I
SENSE
B
R
T
C
T
GND
V
REF
PGND A
OUT A
V
CC
OUT B
PGND B
RAMP COMP
I
LIM
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
ML4819
3
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, R
T
= 14k
W, C
T
= 1000pF, T
A
= Operating Temperature Range, V
CC
= 15V (Notes 1, 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Initial Accuracy
T
J
= 25
C
90
97
104
kHz
Voltage Stability
12V < V
CC
< 18V
0.2
%
Temperature Stability
2
%
Total Variation
Line, temp.
88
106
kHz
Ramp Valley
0.9
V
Ramp Peak
4.3
V
R
T
Voltage
4.8
5.0
5.2
V
Discharge Current (PWM B open)
T
J
= 25
C, V
OUT A
= 2V
7.5
8.4
9.3
mA
V
OUT A
= 2V
7.2
8.4
9.5
mA
DUTY CYCLE LIMIT COMPARATOR
Input Offset Voltage
15
15
mV
Input Bias Current
2
10
mA
Duty Cycle
V
DUTY CYCLE
= V
REF/2
43
45
49
%
REFERENCE
Output Voltage
T
J
= 25
C, I
O
= 1mA
4.95
5.00
5.05
V
Line Regulation
12V < V
CC
< 25V
2
20
mV
Load Regulation
1mA < I
O
< 20mA
8
25
mV
Temperature Stability
0.4
%
Total Variation
Line, load, temperature
4.9
5.1
V
Output Noise Voltage
10Hz to 10kHz
50
mV
Long Term Stability
T
J
= 125
C, 1000 hours, (Note 1)
5
25
mV
Short Circuit Current
V
REF
= 0V
30
85
180
mA
ERROR AMPLIFIER
Input Offset Voltage
15
15
mV
Input Bias Current
0.1
1.0
mA
Open Loop Gain
1 < V
EA OUT A
< 5V
60
75
dB
PSRR
12V < V
CC
< 25V
60
90
dB
Output Sink Current
V
EA OUT A
= 1.1V, V
INV A
= 5.2V
2
12
mA
Output Source Current
V
EA OUT A
= 5.0V, V
INV A
= 4.8V
0.5
1.0
mA
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Voltage (V
CC
) ................................................. 35V
Output Current, Source or Sink (RAMP COMP)
DC ....................................................................... 1.0A
Output Energy (capacitive load per cycle)................... 5
mJ
Multiplier I
SINE
Input (I
SINE
) ................................... 1.2mA
Error Amp Sink Current (GM OUT) ......................... 10mA
Oscillator Charge Current ......................................... 2mA
Analog Inputs (ISENSE A, EA OUT A, INV A)
............................................................... 0.3V to 5.5V
Junction Temperature ............................................ 150
C
Storage Temperature Range ..................... 65
C to 150C
Lead Temperature (soldering 10 sec.) ..................... 260
C
Thermal Resistance (
q
JA
)
Plastic DIP or SOIC .......................................... 60
C/W
OPERATING CONDITIONS
Temperature Range
ML4819C .................................................. 0
C to 70C
ML4819
4
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER (continued)
Output High voltage
I
EA OUT A
= 0.5mA, V
INV A
= 4.8V
6.5
7.0
V
Output Low Voltage
I
EA OUT A
= 2mA, V
INV A
= 5.2V
0.7
1.0
V
Unity Gain Bandwidth
1.0
MHz
GAIN MODULATOR
I
SINE
Input Voltage
I
SINE
= 500
mA
0.4
0.7
0.9
V
Output Current (GM OUT)
I
SINE
= 500
mA, INV A = V
REF
20mV
460
495
505
mA
I
SINE
= 500
mA, INV A = V
REF
+ 20mV
0
10
mA
I
SINE
= 1mA, INV A = V
REF
20mV
900
990
1005
mA
Bandwidth
200
kHz
PSRR
12V < V
CC
< 25V
70
dB
SLOPE COMPENSATION CIRCUIT
RAMP COMP Voltage
V
C(T)
1
V
I
OUT
(I
SENSE
A or I
SENSE
B)
I
RAMP COMP
= 100
mA (Note 3)
45
48
51
mA
OVP COMPARATOR
Input Offset Voltage
Output Off
15
15
mV
Hysteresis
Output On
100
120
140
mV
Input Bias Current
0.3
3
mA
Propagation Delay
150
ns
I
SENSE
COMPARATORS
Input Common Mode Range
0.2
5.5
V
Input Offset Voltage
I
SENSE
A
15
15
mV
I
SENSE
B
0.4
0.7
0.9
V
Input Bias Current
3
10
mA
Input Offset Current
3
0
3
mA
Propagation Delay
150
ns
I
LIMIT
(A) Trip Point
V
OVP
= 5.5V
4.8
5
5.2
V
I
LIM
COMPARATOR
I
LIMIT
Trip Point
.95
1.0
1.05
V
Input Bias Current
2
10
mA
Propagation Delay
150
ns
OUTPUT DRIVERS
Output Voltage Low
I
OUT
= 20mA
0.1
0.4
V
I
OUT
= 200mA
1.6
2.2
V
Output Voltage High
I
OUT
= 20mA
13
13.5
V
I
OUT
= 200mA
12
13.4
V
Output Voltage Low in UVLO
I
OUT
= 1mA, V
CC
= 8V
0.1
0.8
V
Output Rise/Fall Time
C
L
= 1000pF
50
ns
ML4819
5
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4819 oscillator charges the external capacitor (C
T
)
with a current (I
SET
) equal to 5/R
SET
. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
the clock provides a high pulse.
The oscillator period can be described by the following
relationship:
t
OSC
= t
RAMP
+ t
DEADTIME
where:
t
=
C(Ramp Valley to Peak)
I
RAMP
SET
and:
t
C(Ramp Valley to Peak)
8.4mA - I
DEADTIME
SET
=
The maximum duty cycle of the PWM section can be
limited by setting a threshold on pin 7. when the C
T
ramp
is above the threshold at pin 7, the PWM output is held
off and the PWM flip-flop is set:
D
D
(V
- 0.9)
3.4
LIMIT
OSC
PIN7
where:
D
LIMIT
= Desired duty cycle limit
D
OSC
= Oscillator duty cycle
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
UNDER-VOLTAGE LOCKOUT
Start-Up Threshold
15
16
17
V
Shut-Down Threshold
9
10
11
V
V
REF
Good Threshold
4.4
V
SUPPLY
Supply Current
Start-Up, V
CC
= 14V
0.6
1.2
mA
Operating, T
J
= 25
C
25
35
mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V
CC
is raised above the Start-Up Threshold first to activate the IC, then returned to 15V.
Note 3: PWM comparator bias currents are subtracted from this reading.
Figure 1. Oscillator Block Diagram
R
T
I
SET
C
T
CLOCK
DUTY CYCLE
20
10
I
SET
V
REF
5V
+5V
TO PWM
LATCH B
TO PWM
LATCHES
8.4mA
Q1
CLOCK
t
D
RAMP PEAK
RAMP VALLEY
C
T
7
+
+
ML4819
6
ERROR AMPLIFIER
The ML4819 error amplifier is a high open loop gain, wide
bandwidth amplifier.
GAIN MODULATOR
The ML4819 gain modulator is a linear current input
multiplier to provide high immunity to the disturbances
caused by high power switching. The rectified line input
sine wave is converted to a current via a dropping resistor.
In this way, small amounts of ground noise produce an
insignificant effect on the reference to the PWM
comparator.
The output of the gain modulator is a current of the form:
I
OUT
is proportional to I
SINE
I
EA
where I
SINE
is the current in the dropping resistor, and I
EA
is a current proportional to the output of the error
amplifier. When the error amplifier is saturated high, the
output of the gain modulator is approximately equal to
the I
SINE
input current.
The gain modulator output current is converted into the
reference voltage for the PWM comparator through a
resistor to ground on the gain modulator output. The gain
modulator output is clamped to 5V to provide current
limiting.
100pF
200pF
500pF
1nF
2nF
5nF
10nF
50
V
CC
= 15V
T
A
= 25 C
R
T
, TIMING RESISTOR (k
)
20
10
8
5
3
30
50
100
200
300
500
85%
90%
95%
30
20
f
OSC
, OSCILLATOR FREQUENCY (kHz)
MAX DUTY CYCLE
SOURCE SATURATION
(LOAD TO GROUND)
V
CC
T
A
= 25 C
T
A
= 25 C
V
CC
= 15V
80
s PULSED LOAD
120 Hz RATE
SINK SATURATION
(LOAD TO V
CC
)
GND
0
1.0
2.0
3.0
2.0
1.0
0
0
200
400
600
800
I
O
, OUTPUT LOAD CURRENT (mA)
V
SAT
, OUTPUT SATURATION VOLTAGE (V)
Figure 2. Oscillator Timing Resistance vs. Frequency
Figure 3. Output Saturation Voltage vs. Output Current
+5V
INV
4
3
+
+8V
0.5mA
EA OUT
Figure 4. Error Amplifier Configuration
V
CC
= 15V
V
O
= 1.0V TO 5.0V
R
L
= 100k
T
A
= 25 C
GAIN
PHASE
100
80
60
40
20
0
20
10
100
1.0k
10k
100k
1.0M
10M
0
30
60
90
120
150
180
f, FREQUENCY (Hz)
A
VOL
, OPEN-LOOP VOLTAGE GAIN (dB)
, EXCESS PHASE (DEGREES)
Figure 5. Error Amplifier Open-Loop Gain and
Phase vs Frequency
Figure 6. Gain Modulator Block Diagram
6
3
I
SINE
MULTIPLIER
ERROR
VOLTAGE
9V
GAIN MODULATOR
I
SINE
! I
ERR
I
ERR
ML4819
7
SLOPE COMPENSATION
Slope compensation is accomplished by adding 1/2 of the
current flowing out of pin 12 to pin 1 (for the PFC section
and pin 9 (for the PWM section). The amount of slope
compensation is equal to (I
RAMP COMP
/2)
R
L
where R
L
is
the impedance to GND on pin 1 or pin 9. Since most of
the PWM applications will be limited to 50% duty cycle,
slope compensation should not be needed for the PWM
section. This can be defeated by using a low impedance
load to the current sense on pin 9.
500
400
300
200
100
0
0
100
200
300
400
500
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
1. 5V
SINE INPUT CURRENT (A)
MULTIPLIER OUTPUT CURRENT (A)
E/A OUTPUT VOLTAGE (V)
Figure 8. Gain Modulator Linearity
ENABLE
V
REF
V
REF
GEN.
9V
INTERNAL
BIAS
5V V
REF
V
CC
+
Figure 9. Under-Voltage Lockout Block Diagram
T
A
= 25 C
40
30
20
10
0
0
10
20
30
40
V
CC,
SUPPLY VOLTAGE (V)
I
CC,
SUPPLY CURRENT (mA)
Figure 10a. Total Supply Current vs. Supply Voltage
START-UP
25
30
35
20
15
10
5
0
0
10
20
30
40
50
60
70
TEMPERATURE ( C)
I CC
-- SUPPLY CURRENT
OPERATING
CURRENT
Figure 10b. Supply Current (I
CC
) vs. Temperature
OSC
10
20
12
R
T
R
SC
V
REF
I
R(SC)
TO PIN 9
TO PIN 1
I
R(SC)
" 2
I
R(SC)
" 2
9V
C
T
RAMP COMP
SLOPE
COMPENSATION
Q1
Figure 7. Slope Compensation Circuit
UNDER VOLTAGE LOCKOUT
On power-up the ML4819 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when V
CC
reaches 16V. When V
CC
drops
below 10V, the UVLO condition is imposed. During the
UVLO condition, the 5V V
REF
pin is "off", making it
usable as a status flag.
ML4819
8
APPLICATIONS
POWER FACTOR SECTION
The power factor section in the ML4819 is similar to the
power factor section in the ML4812 with the exception of
the operation of the slope compensation circuit. Please
refer to the ML4812 data sheet for more information.
The following calculations refer to Figure 12 in this data
sheet. The component designators in the equations below
refer to the following components in Figure 12:
R
T
= R16, C
T
= C6.
INPUT INDUCTOR (L1) SELECTION
The central component in the regulator is the input boost
inductor. The value of this inductor controls various
critical operational aspects of the regulator. If the value is
too low, the input current distortion will be high and will
result in low power factor and increased noise at the
input. This will require more input filtering. In addition,
when the value of the inductor is low the inductor dries
out (runs out of current) at low currents. Thus the power
factor will decrease at lower power levels and/or higher
line voltages. If the inductor value is too high, then for a
given operating current the required size of the inductor
core will be large and/or the required number of turns will
be high. So a balance must be reached between distortion
and core size.
One more condition where the inductor can dry out is
analyzed below where it is shown to be maximum duty
cycle dependent.
For the boost converter at steady state:
V
V
D
OUT
IN
ON
=
-
1
(1)
Where D
ON
is the duty cycle [T
ON
/(T
ON
+ T
OFF
)]. The
input boost inductor will dry out when the following
condition is satisfied:
(2)
or
V
D
V
INDRY
ON MAX
OUT
= -
[
]
1
(
)
(3)
V
INDRY
: Voltage where the inductor dries out.
V
OUT
: Output dc voltage.
Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver during
the OFF time. The net result is that the inductor dries out.
The recommended maximum duty cycle is 95% at
100KHz to allow time for the input inductor to dump its
energy to the output capacitors.
For example:
if: V
OUT
= 380V and
D
ON(MAX)
= 0.95
then substituting in (3) yields V
INDRY
= 20V. The effect of
drying out is an increase in distortion at low input voltages.
For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
waveform. As the input voltage sweeps from zero volts to
its maximum value and back, so does the current.
The load of the power factor regulator is usually a
switching power supply which is essentially a constant
power load. As a result, an increase in the input voltage
will be offset by a decrease in the input current.
By combining the ideas set forth above, some ground
rules can be obtained for the selection and design of the
input inductor:
Step 1: Find minimum operating current.
I
P
V
IN MIN PEAK
IN MIN
IN MAX
(
)
(
)
(
)
.
=
1 414
(4)
V
IN(MAX)
= 260V
P
IN(MIN)
= 50W
then:
I
IN(MIN)PEAK
= 0.272A
Step 2: Choose a minimum current at which point the
inductor current will be on the verge of drying
out. For this example 40% of the peak current
found in step 1 was chosen.
V
CC
= 15V
T
A
= 25 C
0
4.0
8.0
12
16
20
24
0
20
40
60
80
100
120
I
REF
, REFERENCE SOURCE CURRENT (mA)
V
REF
, REFERENCE VOLTAGE CHANGE (mV)
Figure 11. Reference Load Regulation
V t
V
D
IN
OUT
ON MAX
( )
(
)
<
-
[
]
1
ML4819
9
Figure 12. Typical Application, 180W Power Factor Corrected 12V Output Power Supply
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
UI
ML4819
I
SENSE
A
OV
P
GM OUT
EA OUT
A
INV A
I
SINE
DUTY CYCLE
PWM B
I
SENSE
B
R
T
C
T
GND
V
REF
PGND A
OUT A
V
CC
OUT B
PGND B
RAMP COMP
I
LIM
C9 0.1
F
C13 1
F
V
REF
C8 1
C12
1
F
C6
1000pF
V
REF
OUT
L1
N
P
F1
PGND
PFC
ENHANCEMENT
D5
1N5406
D6
MUR850
R12
10
PO
WER F
A
C
T
OR CORRECTION
D1 - D4
1N5406
D7
1N4148
C1
0.6
F
IN
B+ 380
VDC
C2
330
F
400V
DC
C3
0.62
F
C4
6800pF
V
IN
+
+12V
C10
330
F
25V
DC
T3
T1
D9
MUR110
T3
D13
C18
1500
F
C16
1
F
C19
4.7
F
R27
1.2k
R29
U3
TL431
MOC
8102
R24
1
R25
1
D14
D13
C5
1000pF
D12
MUR150
D11
MUR150
D10
1N4148
C11
1
F
R23, 100
R22
10
PWM REGULA
T
O
R
R20
7.5
R19, 3k
T2
R17, 3
R10
33k
R15
4.3k
V
REF
V
REF
V
REF
R9
27k
R18
65k
V
CC
2.26k
R26
1.5k
U2
R28
8.66k
C14
2200pF
C11
1
F
R16
15k
Q3
IRF840
Q3
IRF840
R7
357k
B+ 380V
R8
4.53k
R5
357k
R2
510k
R1
330k
D8
3V
Q4
2N2222
R6
4.75k
R21
3k
R11
91
Q1
IRF840
C20
0.1
F
D83
004
C7
10
F
35V
R4
12k
R3
5.6k
R13
4.7k
R14
4.7k
V
OUT
ST
AR
TUP
CIRCUIT
+
+
ML4819
10
then:
I
LDRY
= 100mA
Step 3: The value of the inductance can now be found
using previously calculated data.
L
V
D
I
f
V
mA
kHz
mH
INDRY
ON MAX
L DRY
OSC
1
20
0 95
100
100
2
=
=
=
(
)
(
)
.
(5)
The inductor can be allowed to decrease in value when
the current sweeps from minimum to maximum value.
This allows the use of smaller core sizes. The only
requirement is that the ramp compensation must be
adequate for the lower inductance value of the core so
that there is adequate compensation at high current.
Step 4: The presence of the ramp compensation will
change the dry out point, but the value found
above can be considered a good starting point.
Based on the amount of power factor correction
the value of L1 can be optimized after a few
iterations.
Gapped Ferrites, Molypermalloy, and Powdered Iron cores
are typical choices for core material. The core material
selected should have a high saturation point and
acceptable losses at the operating frequency.
One ferrite core that is suitable at around 200W is the
#4229PL00-3C8 made by Ferroxcube. This ungapped core
will require a total gap of 0.180" for this application.
OSCILLATOR COMPONENT SELECTION
The oscillator timing components can be calculated by
using the following expression:
f
R
C
OSC
T
T
=
1 36
.
(6)
For example:
Step 1: At 100kHz with 95% duty cycle T
OFF
= 500ns
calculate C
T
using the following formula:
C
t
I
V
pF
T
OFF
DIS
OSC
=
=
1000
(7)
Step 2: Calculate the required value of the timing
resistor.
R
f
C
kHz
pF
k
Choose R
k
T
OSC
T
T
=
=
=
=
1 36
1 36
100
1000
13 6
14
.
.
.
.
.
(8)
CURRENT SENSE AND SLOPE (RAMP) COMPENSATION
COMPONENT SELECTION
Slope compensation in the ML4819 is provided internally.
A current equal to V
CT
/2(R18) is added to I
SENSE
A (pin 1).
this is converted to a voltage by R10, adding slope to the
sensed current through T1. The amount of slope
compensation should be at least 50% of the downslope of
the inductor current during the off time as reflected on pin
1. Note that slope compensation is a requirement only if
the inductor current is continuous and the duty cycle is
more than 50%. The highest inductor downslope is found
at the point of inductor discontinuity:
di
dt
V
V
L
V
V
mH
A
s
L
B
IN DRY
=
-
=
-
=
380
20
2
0 18
.
/
(9)
The downslope as reflected to the input of the PWM
comparator is given by:
S
V
V
L
R
N
PWM
B
IN DRY
C
=
-
1
11
(10)
Where N
C
is the turns ratio of the current transformer (T1)
used. In general, current transformers simplify the sensing of
switch currents, especially at high power levels where the
use of sense resistors is complicated by the amount of
power they have to dissipate. Normally the primary side
of the transformer consists of a single turn and the
secondary consists of several turns of either enameled
magnet wire or insulated wire. The diameter of the ferrite
core used in this example is 0.5" (SPANG/Magnetics
F41206-TC). The rectifying diode at the output of the
current transformer can be a 1N4148 for secondary
currents up to 75mA average.
Current-sensing MOSFETs or resistive sensing can also be
used to sense the switch current. In these cases, the
sensed signal has to be amplified to the proper level
before it is applied to the ML4819.
The value of the ramp compensation (SC
PWM
) as seen at
pin 1 is:
SC
R
R
C
R
PWM
=
2 5
9
16
6
18
.
(11)
The required value for R
18
can therefore be found by
equating:
SC
A
S
PWM
SC
PWM
=
where A
SC
is the amount of slope compensation and
solving for R
18
.
ML4819
11
The value of R
9
(pin 3) depends on the selection of R
2
(pin 6).
R
V
I
mA
k
IN MAX PEAK
SINE PEAK
2
260 1 414
0 72
510
=
=
=
(
)
(
)
.
.
(12)
R
V
R
V
k
k
CLAMP
IN MIN PEAK
9
2
4 8 510
80 1 414
22
>
=
=
(
)
.
.
(13)
Choose R9 = 27k
W
The peak of the inductor current can be found
approximately by:
I
P
V
A
LPEAK
OUT
IN MIN RMS
=
=
=
1 414
1 414 200
90
3 14
.
.
.
(
)
(14)
Next select N
C
, which depends on the maximum switch
current. Assume 4A for this example. N
C
is 80 turns.
R
V
N
I
CLAMP
C
LPEAK
11
4 9 80
4
100
=
=
=
.
(15)
Where R
11
is the sense resistor, and V
CLAMP
is the current
clamp at the inverting input of the PWM comparator. This
clamp is internally set to 5V. In actual application it is a
good idea to assume a value less than 5V to avoid
unwanted current limiting action due to component
tolerances. In this application V
CLAMP
was chosen as 4.8V.
Having calculated R
11
the value S
PWM
and of R
18
can
now be calculated:
S
V
mH
V
s
PWM
=
-
=
380
20
2
100
80
0 225
.
/
R
R
A
S
R
C
R
k
k
nF
k
SC
PWM
T
T
18
9
18
6
2 5
2 5 28 8
0 7
0 225 10
14
1
30
=
=
.
.
.
.
( .
)
(16)
Choose R18 = 33k
W
The following values were used in the calculation:
R
9
= 27k
W
A
SC
= 0.7
R
T
= 14k
W
C
T
= 1nF
VOLTAGE REGULATION COMPONENTS
The values of the voltage regulation loop components are
calculated based on the operating output voltage. Note
that voltage safety regulations require the use of sense
resistors that have adequate voltage rating. As a rule of
thumb if 1/4W through-hole resistors are used, two of
them should be put in series. The input bias current of the
error amplifier is approximately 0.5A, therefore the
current available from the voltage sense resistors should
be significantly higher than this value. Since two 1/4W
resistors have to be used the total power rating is 1/2W.
The operating power is set to be 0.4W then with 380V
output voltage the value can be calculated as follows:
R
V
W
k
5
2
380
0 4
360
=
=
(
) / .
(17)
Choose two 178k
W, 1% connected in series.
Then R6 can be calculated using the formula below:
R
V
R
V
V
V
k
V
V
k
REF
B
REF
6
5
5
356
380
5
4 747
=
-
=
-
=
.
(18)
Choose 4.75k
W, 1%. One more critical component in the
voltage regulation loop is the feedback capacitor for the
error amplifier. The voltage loop bandwidth should be set
such that it rejects the 120Hz ripple which is present at
the output. If this ripple is not adequately attenuated it
will cause distortion on the input current waveform.
Typical bandwidths range anywhere from a few Hertz to
15Hz. The main compromise is between transient
response and distortion. The feedback capacitor can be
calculated using the following formula:
C
R
BW
C
k
Hz
F
8
5
8
1
3 142
1
3 142 356
2
0 44
=
=
=
.
.
.
(19)
ML4819
12
OVERVOLTAGE PROTECTION (OVP) COMPONENTS
The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to
a level where the power components are safe to operate.
Ten to fifteen volts above V
OUT
seems to be adequate.
This sets the maximum transient output voltage to about
395V.
By choosing the high voltage side resistor of the OVP
circuit the same way as above i.e. R
7
= 356K then R
8
can
be calculated as:
R
V
R
V
V
V
k
V
V
k
REF
OVP
REF
8
7
5
356
395
5
4 564
=
-
=
-
=
.
(20)
Choose 4.53k
W, 1%.
Note that R
5
, R
6
, R
7
and R
8
should be tight tolerance
resistors such as 1% or better.
OFF-LINE START-UP AND BIAS SUPPLY GENERATION
The Start-Up circuit in Figure 12 can be either a "bleed
resistor" (39k
W, 2W) or the circuit shown in Figure 13. The
bleed resistor method offers advantage of simplicity and
lowest cost, but may yield excessive turn-on delay at low
line.
When the voltage on pin 15 (V
CC
) exceeds 16V, the IC
starts up. The energy stored on the C21 supplies the IC
with running power until the supplemental winding on T3
can provide the power to sustain operation.
PWM SECTION
The PWM section in Figure 12 is a two switch forward
converter, shown in Figure 14 below for clarity. This fully
clamped circuit eliminates the need for very high
voltage MOSFETs. Flyback topology is also possible with
the ML4819.
ENHANCEMENT CIRCUIT
The power factor enhancement circuit (inside the dotted
lines) in Figure 11 is described in Application Note 11. It
improves the power factor and lowers the input current
harmonics. Note that the circuit meets IEC1000-3-2
specifications (with the enhancement circuit installed) on
the harmonics by a large margin while correcting the
input power factor to better than 0.99 under most steady
state operating conditions.
R33
2k
R31
510k
R32
2k
Q5
2N2222
C21
0.1
D16
22V
V
REF
TO V
CC
OUT
IN
R30
4.3k
Q6
IRF821
D15
1N4001
START-UP
CIRCUIT
Figure 13. Start-Up Circuit
D12
D11
T2
T2
ML4819
T3
Q2
Q3
385VDC
Figure 14. Two-Switch Forward Converter
This regulator (Figure 12) uses current mode control.
Current is sensed through R24 and filtered for high
frequency noise and leading edge transient through T23
and C14. The main regulation loop is through PWM B. The
TL431 (U3) in the secondary serves as both the voltage
reference and error amplifier. Galvanic isolation is
provided by an optocoupler (U2) which provides a current
command signal on pin 8. Loop compensation is provided
by R29 and C20. The output voltage is set by:
V
R
R
OUT
=
+
2 5 1
29
28
.
(21)
The control loop is compensated using standard
compensation techniques.
Current is limited to a threshold of 2A (1V on R24). The duty
cycle is limited in this circuit to below 50% to prevent
transformer (T3) core saturation. The maximum duty cycle
limit of 45% is set using a threshold of V
REF
/2 on pin 7.
the circuit in Figure 12 can be modified for voltage mode
operation by utilizing the slope current which appears on
pin 9 as show in figure 15 below.
The ramp amplitude appearing on pin 9 will be:
V
I
R V
R
R
=
18
2
( )
(22)
where R18 is the slope compensation resistor. Since this
circuit operates with a constant input voltage (as supplied
by the PFC section) voltage feed-forward is unnecessary.
ML4819
13
CONSTRUCTION AND LAYOUT TIPS
High frequency power circuits require special care during
breadboard construction and layout. Double sided printed
circuit boards with ground plane on one side are highly
recommended. All critical switching leads (power FET,
output diode, IC output and ground leads, bypass
capacitors) should be kept as small as possible. This is to
minimize both the transmission and pickup of switching
noise.
There are two kinds of noise coupling; inductive and
capacitive. As the name implies inductive coupling is
due to fast changing (high di/dt) circulating switching
currents. The main source is the loop formed by Q1, D6,
and
C3C4. Therefore this loop should be as small as possible,
and the above capacitors should be good, high frequency
types.
The second form of noise coupling is due to fast changing
voltages (high dv/dt). The main source in this case is the
drain of the power FET. The radiated noise in this case can
be minimized by insulating the drain of the FET from the
heatsink and then tying the heatsink to the source of the
FET with a high frequency capacitor.
The IC has two ground pins named PWR GND and Signal
GND. These two pins should be connected together with a
very short lead at the printed circuit board exit point. In
general grounding is very important and ground loops
should be avoided. Star grounding schemes are preferred.
FROM
R23, C14
OSC
SLOPE
COMP.
C
T
C6
DUTY CYCLE
I
LIM
V
REF
I
RSC
2
PWM B
I
SENSE
B
R
V
1V
FROM U2, R15
0.7V
R13
R14
+
+
+
7
20
11
9
8
OSC
+
Figure 15. Voltage Mode Configuration
ML4819
14
Component Values/Bill of Materials for Figure 12
Reference
Description
C1, C3
0.6F, 630V Film (250 VAC)
C2
330F 25V Electrolytic
C4
6800pF 1KV Ceramic
C5, C6
1000pF
C7
10F 35V
C8, C11, C13, C15, C16 1F Ceramic
C9, C20, C21
0.1F Ceramic
C10
1500F 25V Electrolytic
C12, C17
1F Ceramic
C14
2200 pF
C18
1500F 16V Electrolytic
C19
4.7F
D1- D5
1N5406
D6
MUR850
D7, D10
1N4148
D8
3V Zener diode or 4 x 1N4148
in series
D9
MUR110
D11, D12
MUR150
D13
D83-004K
D15
1N4001
D16, D14
1N5818 or 1N5819
F1
5A, 250V, 3AG
L1
2mH, 4A I
PEAK
Core: Ferroxcube 4229-3CB
150 Turns #24 AWG
0.150" gap
L2
10
mH
Core: Spang OF 43019 UG00
8 Turns #15AWG gap 0.05"
Q1-Q3
IRF840
Q4, Q5
2N2222
Q6
IRF821
R1
330k
R2, R31
510k
R3
5.6k
Reference
Description
R4
12k
R5, R7
357k, 1%
R6
4.57k, 1%
R8
4.53k, 1%
R9
27k
R10, R18
33k
R11
9 1
R12, R22
1 0
R13, R14
4.7k
R15
4.3k
R16
15k
R17
3
R20
7.5
R21,R19
3 k
R23
100
R24, R25
1
R26
1.5k
R27
1.2k
R28
8.66k, 1%
R29
2.26k, 1%
R30
2k, 1W
R32, R33
2 k
T1
Spang F41206-TC or
Siemens B64290-K45-X27 or X830 or
Ferroxcube 768T188-38
N
S
= 80, N
P
= 1
T2
Same core as T1
N
S
= N
P
= 15 bifilar
T3
Core: Ferroxcube 4229-3C8
Pri. 44 Turns #18 Litz wire
Sec. 4 Turns of copper strip
Aux. 2 Turns #24 AWG
U2
MOC8102
U3
TL431
ML4819
15
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
PIN 1 ID
0.295 - 0.325
(7.49 - 8.26)
1.010 - 1.035
(25.65 - 26.29)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
20
0 - 15
1
0.055 - 0.065
(1.40 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.060 MIN
(1.52 MIN)
(4 PLACES)
Package: P20
20-Pin PDIP
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4819CP
0C to 70C
Molded DIP (P20)
ML4819CS (Obsolete)
0C to 70C
Molded SOIC (S20)
ORDERING INFORMATION
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
DS4819-01
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
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