November 1999
PRELIMINARY
ML6554
3A Bus Termination Regulator
1
GENERAL DESCRIPTION
The ML6554 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired
output voltage or termination voltage for various
applications. The ML6554 can be implemented to
produce regulated output voltages in two different modes.
In the default mode, when the V
REF
pin is open, the
ML6554 output voltage is 50% of the voltage applied to
V
CCQ
. The ML6554 can also be used to produce various
user-defined voltages by forcing a voltage on the VREF
IN
pin. In this case, the output voltage follows the input
VREF
IN
voltage. The switching regulator is capable of
sourcing or sinking up to 3A of current while regulating an
output V
TT
voltage to within 3% or less.
The ML6554, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator
can be used as a termination voltage for other bus
interface standards such as SSTL, CMOS, Rambus
TM
,
GTL+, VME, LV-CMOS, LV-TTL, and PECL.
BLOCK DIAGRAM
FEATURES
s
Power SOP package
s
Can source and sink up to 3A, no heat sink required
s
Integrated Power MOSFETs
s
Generates termination voltages for SSTL-2 SDRAM,
SGRAM, or equivalent memories
s
Generates termination voltages for active termination
schemes for GTL+, Rambus, VME, LV-TTL, PECL and
other high speed logic
s
V
REF
input available for external voltage divider
s
Separate voltages for V
CCQ
and PV
DD
s
Buffered V
REF
output
s
V
OUT
of 3% or less at 3A
s
Minimum external components
s
Shutdown for standby or suspend mode operation
s
Thermal Shutdown
130C
FEATURING
POWER SOP
High-Performance
Thermal Dissipation Package
VL2
AGND
13
VREFIN
VREFOUT
11
6
VDD
1
SHDN
12
PVDD2
PVDD1
7
VL1
3
+
+
AVCC
VCCQ
15
OSCILLATOR/
RAMP
GENERATOR
S
R
Q
Q
(VOUT)
(VOUT)
PGND1
DGND
VFB
PGND2
2
4
5
8
VDD
9
14
10
VREF BUFFER
ERROR AMP
RAMP
COMPARATOR
+
16
200k
200k
ML6554
2
NOVEMBER, 1999
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
V
DD
Digital supply voltage
2
PV
DD1
Voltage supply for internal power
transistors
3
V
L1
Output voltage/ inductor connection
4
P
GND1
Ground for output power transistors
5
P
GND2
Ground for output power transistors
6
V
L2
Output voltage/inductor connection
7
PV
DD2
Voltage supply for internal power
transistors
8
D
GND
Digital ground
PIN
NAME
FUNCTION
9
V
DD
Digital supply voltage
10
V
FB
Input for external compensation
feedback
11
VREF
IN
Input for external reference voltage
12
SHDN
Shutdown active low. CMOS input
level
13
AGND
Ground for internal reference voltage
divider
14
VREF
OUT
Reference voltage output
15
V
CCQ
Voltage reference for internal voltage
divider
16
AV
CC
Analog voltage supply
ML6554
16-Pin PSOP (U16)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
ML6554
3
NOVEMBER, 1999
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
PV
DD ..........................................................................................
5.0V
Voltage on Any Other Pin ...... GND 0.3V to V
IN
+ 0.3V
Average Switch Current (I
AVG
) .................................. 3.0A
Junction Temperature .......................................................
Storage Temperature Range .............................................
Lead Temperature (Soldering, 10 sec) ..............................
Thermal Resistance (
q
JC
)(Note 3) ........................... 2C/W
Output Current, Source or Sink ................................. 3.0A
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C
PV
DD
Operating Range ................................ 2.0V to 4.0V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, PV
DD
= 3.3V10%, T
A
= Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING REGULATOR
V
TT
Output Voltage, SSTL_2
I
OUT
= 0,
V
CCQ
= 2.3V
1.12
1.15
1.18
V
(See Figure 1)
V
REF
= open
V
CCQ
= 2.5V
1.22
1.25
1.28
V
Note 2
V
CCQ
= 2.7V
1.32
1.35
1.38
V
I
OUT
= 3A,
V
CCQ
= 2.3V
1.09
1.15
1.21
V
V
REF
= open
V
CCQ
= 2.5V
1.19
1.25
1.31
V
Note 2
V
CCQ
= 2.7V
1.28
1.35
1.42
V
VREF
OUT
Internal Resistor Divider
I
OUT
= 0
V
CCQ
= 2.3V
1.139
1.15
1.162
V
Note 2
V
CCQ
= 2.5V
1.238
1.25
1.263
V
V
CCQ
= 2.7V
1.337
1.35
1.364
V
Z
IN
V
REF
Reference Pin Input Impedance
Note 2
V
CCQ
= 0
100
k
W
Switching Frequency
650
kHz
DV
OFFSET
Offset Voltage V
TT
VREF
OUT
V
CCA
= 2.5V No Load
V
CCQ
= 2.5
12.5
12.5
mV
SUPPLY
I
Q
Quiescent Current
I
OUT
= 0, no load
I
VCCQ
10
A
I
AVCC
500
A
I
DVCC
7
mA
BUFFER
I
REF
Output Load Current
3
mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: AV
CC
, PV
DD
= 3.3V 10%
Note 3: Infinite heat sink
ML6554
4
NOVEMBER, 1999
FUNCTIONAL DESCRIPTION
This switching regulator is capable of sinking and sourcing
3A of current without an external heatsink. The ML6554
uses a power surface mount package (PSOP) that includes
an integrated heat slug. The heat can be piped through the
bottom of the device and onto the PCB (Figure 2).
The ML6554 integrates two power MOSFETs that can be
used to source and sink 3A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less,
depending on the external components chosen. Separate
voltage supply inputs have been added to accommodate
applications with various power supplies for the databus
and power buses.
OUTPUTS
The output voltage pins (V
L1
, V
L2)
are tied to the databus,
address, or clock lines via an external inductor. See the
Applications section for recommendations. Output
voltage is determined by the V
CCQ
or VREF
IN
inputs.
INPUTS
The input voltage pins (V
CCQ
or VREF
IN
) determine the
output voltages (V
L1
or V
L2)
. In the default mode, where
the VREF
IN
pin is floating, the output voltage is 50% of
the V
CCQ
input. V
CCQ
can be the reference voltage for the
databus.
Figure 1.
16
15
14
13
12
11
10
9
U1
ML6554
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
1
2
3
4
5
6
7
8
R3
100k
VCCQ
VREFOUT
TPI
VTT
2.5V TO 4V
SHDN
VREFIN
GND
GND
TO SDRAMS
220F
C7 1nF
220F
C4 0.1F
R4 100k
R5 1k
C9 0.1F
R2 100
R1 100
C8 0.1F
C2
0.1F
C1
820F
F2V
OS-CON
L1 3.3H C3 0.1F
Output voltage can also be selected by forcing a voltage
at the VREF
IN
pin. In this case, the output voltage follows
the voltage at the VREF
IN
input. Simple voltage dividers
can be used this case to produce a wide variety of output
voltages between 2.3V to 4V.
VREF INPUT AND OUTPUT
The VREF
IN
input can be used to force a voltage at the
outputs (Inputs section, above). The VREF
OUT
pin is an
output pin that is driven by a small output buffer to
provide the V
REF
signal to other devices in the system.
The output buffer is capable of driving several output
loads. The output buffer can handle 3mA.
OTHER SUPPLY VOLTAGES
Several inputs are provide for the supply voltages: PV
DD1
,
PV
DD2
, AV
CC
, and V
DD
.
The PV
DD1
and PV
DD2
and provide the power supply to
the power MOSFETs. V
DD
provides the voltage supply to
the digital sections, while AV
CC
supplies the voltage for
the analog sections. Again, see the Applications section
for recommendations.
FEEDBACK INPUT
The V
FB
pin is an input that can be used for closed loop
compensation. This input is derived from the voltage
output. See application section for recommendation.
ML6554
5
NOVEMBER, 1999
HEAT SLUG
Figure 2. Cutaway view of PSOP Package
APPLICATIONS
USING THE ML6554 FOR SSTL BUS TERMINATION
The circuit schematic in Figure 1 shows a recommended
approach for an constructing a bus terminating solution for
an SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 3 and
4. Note that the ML6554 can provide the voltage
reference (V
REF
) and terminating voltages (V
TT
). Using
the layout as shown in Figures 5, 6, and 7, and measuring
the V
TT
performance using the test setup as described in
Figure 8, the ML6554 delivered a V
TT
20mV for 1A to
3A loads (see Figure 9). Table 1 provides a recommended
parts list. For more recent Applications Notes or
Evaluation Boards contact Micro Linear.
POWER HANDLING CAPABILITY OF THE PSOP PACKAGE
Using the board layout shown in Figures 5,6, and 7;
soldering the ML6554 to the board at zero LFPM the
temperature around the package measured 55
C for 3A
loads. Note that a 1ounce copper plane was used in the
board construction.
Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). The power handling performance of the PSOP
package is shown by a study of the package manufacturer
for various airflow vs.
q
JA
conditions in Figure 10.
BUS TERMINATION SOLUTIONS FOR OTHER BUSES
Table 2 provides a summary of various bus termination
V
REF
& V
TT
requirements. The ML6554 can be used for
those applications.
ML6554
6
NOVEMBER, 1999
DATA LINE, CLOCK LINES,
ADDRESS LINES, CONTROL LINES
TERMINATION
RESISTORS
ML6554
PC CHIP SET
NORTHBRIDGE
TERMINATION
RESISTORS
VTT
VREF
168/184/208-PIN DIMM CONNECTORS
AND SDRAM/SGRAM MODULES
Figure 3. Complete Termination Solution PC Main Memory (PC Motherboard)
ML6554
7
NOVEMBER, 1999
Figure 4. Complete Termination Solution Graphics Memory Bus AGP Graphics Cards
DATA LINE, CLOCK LINES,
ADDRESS LINES, CONTROL LINES
TERMINATION
RESISTORS
3D
GRAPHIC CHIP
TERMINATION
RESISTORS
SO DIMM
AND MODULES
SGRAM
ML6554
VOLTAGE
REGULATOR
2.5V
VREF
VTT
5V OR 3.3V
AGP/PCI BUS
ML6554
8
NOVEMBER, 1999
Figure 5. Top Silk
Figure 6. Top Layer
Figure 7. Bottom Layer
ML6554
9
NOVEMBER, 1999
3.3V POWER
SUPPLY
ACTIVE
CLAMP
VDD
CURRENT SOURCE/SINK
POWER SUPPLY
VTT
GND
VCCQ
V
A
VCCQ
SUPPLY
V
A
ML6554
EVAL
ITT
Figure 8. Test Circuit Setup
Figure 9. VTT Performance for SSTL-2 Bus
3A SOURCING
2A SOURCING
1A SOURCING
VTT VARIANCE WITH VDD@ITT (VCCQ 2.5V)
TESTED WITH EVAL PCB
3A SINKING
ITT
2A SINKING
1A SINKING
0A SINKING
1.29
1.28
1.27
1.26
V
TT
(V)
VDD (V)
2.0
2.5
3.0
4.0
3.5
ML6554
10
NOVEMBER, 1999
ITEM
QTY
DESCRIPTION
MANUFACTURER / PART NUMBER
DESIGNATOR
RESISTORS
1
2
100
W1210 SMD
Panasonic/ERJ-8ENF1000V
R1, R2
2
1
1k
W 1210 SMD
Panasonic/ERJ-8ENF1001V
R5
3
2
100k
W1210 SMD
Panasonic/ERJ-8ENF1003V
R3, R4
CAPACITORS
4
3
0.1F 1210 Film SMD
Panasonic/ECV3VB1E104K
C2, C8, C9
Panasonic/ECU-V1H104KBW
5
1
820F 2V Solid Elect. SMD
Sanyo/ 2SV820M Os Con
C1
6
2
330F Tant 6.3V 100m
W
AVX/ TPSE337M006R0100
C5, C6
7
1
1nF 1210 Film SMD
Panasonic/ECU-V1H102KBM
C7
8
2
0.1F 0805 Film
Panasonic/ECJ-2VF1C104Z
C3, C4
ICS
9
1
ML6554 Bus Terminator
ML6554CU
U1
Power SOP Package
MAGNETICS
10
1
3.3H 5A inductor SMD
Coilcraft/D03316P-332HC
L1
Pulse Eng./ P0751.332T
Gowanda/SMP3316-331M
XFMRS inc./XF0046-S4
OTHER
11
1
Scope probe socket
Tektronics/131-4353-00
TP1
12
1
12 Pin breakaway strip
Sullins/PTC36SAAN (36 PINS)
I/O, standoffs
Table 1. Recommend Parts List for SSTL-2 Termination Circuit
VENDOR LIST
1. AVX
(207) 282-5111
2. Sanyo
(619) 661-6835
3. Tektronix
(408) 496-0800
4. Coilcraft
(847) 639-6400
5. Pulse
(800) 797-8573
6. Gowanda
(716) 532-2234
7. Xfmrs Inc.
(317) 834-1066
8. Panasonic
(714) 373-7366
9. Digikey
(800) 344-4539
ML6554
11
NOVEMBER, 1999
Figure 10. Graphical Results Summary 1S2P Test Board
POWER (W)
NATURAL CONVECTION
JA TEST RESULTS
1.27mm PITCH PowerSOPTM 2
SLUG SOLDERED
FORCED CONVECTION
JA TEST RESULTS
1.27mm PITCH PowerSOPTM 2
SLUG SOLDERED
60
40
20
0
JA
(
C/W)
0.2
1.0
1.4
1.8
0.6
0.4
1.2
1.6
2.0
0.8
0.0
60
40
20
0
JA
(
C/W)
AIR VELOCITY (LFPM)
0
200
300
500
400
100
16Ld PSOP2
2.3x3.1mm PAD
1.9mm DIE
16Ld PSOP2
2.3x3.1mm PAD
1.9mm DIE @ 0.8 WATTS
Figure 11. Test Board Layout for
Q
JA
vs. Airflow
DRAWING NUMBER
ENG-CB-1007 REV A
Applicable Jedec Spec
JC 51-X (Note 1)
(Sroposed Spec)
Substrate Material
FR-4
Dimensions (LxW) (Overall)
114.3 x 76.2mm
Dimensions (LxW) (Metallization)
55 x 65mm
Dimensions (LxW) (Inner Planes)
73 x 73mm
Thickness
1.6 mm
Pitch
1.27mm
Stackup (# Signal Layers, # Cu Planes)
1S2P
Cu Trace Coverage (Signal Layer)
12%
Cu Coverage (Internal Layer)
100%
Trace Width (Spec/Measured)
235.525.5/288m
Trace Cu Thickness (Spec/Measured)
7014/67m
Inner Cu Thickness (Spec/Measured)
353.5/31m
Build #
C1797
Note 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".
ML6554
12
NOVEMBER, 1999
BUS
DESCRIPTION
DRIVING
VDDQ
VTT
VREF
MICRO
INDUSTRY
METHOD
LINEAR
SYSTEM
SOUTIONS
COMPONENTS
GTL+
Gunning
Open Drain
5v or 3.3V 1.5V10%
1.0V2%
ML6554CU;
300 to 500MHz
Transceiver
Note 10
Note12
Note 11
Mode: V
REF
Processor;
Bus Plus
Input = 1.5V,
PC Chipsets;
V
CC
= 5V
GTLP 16xxx
Buffers;
Fairchild,
Texas Instr.
SSTL_2
Series Stub
Symmetric
2.5V10% 0.5x(V
DDQ
)
2.5V
ML6554CU
SSTL SDRAM;
Terminated
Drive, Series
3%
or ML6553CS;
Hitachi,
Logic for 2V
Resistance
Mode: V
REF
Fujitsu,
Input = Floating
NEC, Micro,
or Forced,
Mitsubishi
V
CC
= 3.3V
RAMBUS
RAMBUS
Open Drain
None
2.5V
2.0V
ML6553CS;
nDRAM,
Signaling
Specified
Mode: V
REF
RAMBUS,
Logic
Input = Open,
Intel, Toshiba
V
CC
= V
DDQ
LV-TTL
Low Voltage
Symmetric
3.310%
V
DDQ
/2
3.3V
ML6553CS;
Processors or
TTL Logic or
Drive
Mode: V
REF
backplanes;
PECL or
Input = Open,
LV-TTL
3.3V VME
VCC = VDDQ
SDRAM,
EDO RAM
Table 2. Termination Solutions Summary By Buss Type
ML6554
13
NOVEMBER, 1999
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML6554CU
0C to 70C
16-Pin PSOP (U16)
DS6554-01
PHYSICAL DIMENSIONS
inches (millimeters)
ORDERING INFORMATION
Micro Linear Corporation
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
SEATING PLANE
0.150 - 0.157
3.81 - 3.99
0.230 - 0.244
(5.84 - 6.20)
0.386 - 0.393
9.80 - 9.98
0.014 - 0.019
(0.35 - 0.49)
0.050 BSC
(1.27 BSC)
0.016 - 0.035
(0.41 - 0.89)
0.061 - 0.068
(1.55 - 1.73)
0.00 - 0.004
(0.127 - 0.25)
0.055 - 0.061
(1.40 - 1.55)
16
0.0075 - 0.0098
(0.19 - 0.25)
0 - 8
1
0.017 - 0.027
0.43 - 0.69
(4 PLACES)
Package: U16
16-Pin PSOP
PIN 1 ID
HEAT SLUG
HEAT SLUG
DIMENSIONS:
0.079
0.279
(2.01
7.09)
Micro Linear 1999.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property
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