Document Outline

• TOC
• 1.0 Device Overview
  • FIGURE 1-1: PIC16F913/916 Block Diagram
  • FIGURE 1-2: PIC16F914/917 Block Diagram
  • TABLE 1-1: PIC16F91X Pinout Descriptions 
• 2.0 Memory Organization
  • 2.1 Program Memory Organization
    • FIGURE 2-1: Program Memory Map And Stack For The PIC16F913/914
    • FIGURE 2-2: Program Memory Map And Stack For The PIC16F916/917
  • 2.2 Data Memory Organization
    • 2.2.1 General Purpose Register File
    • 2.2.2 Special FUNCTION Registers
      • FIGURE 2-3: PIC16F913/916 Special Function Registers
      • FIGURE 2-4: PIC16F914/917 Special Function Registers
      • TABLE 2-1: PIC16F91X Special Registers Summary Bank 0
      • TABLE 2-2: PIC16F91X Special Function Registers Summary Bank 1
      • TABLE 2-3: PIC16F91X Special Registers Summary Bank 2
      • TABLE 2-4: PIC16F91X Special Function Registers Summary Bank 3
      • Register 2-1: STATUS � STATUS REGISTER (ADDRESS: 03h, 83h, 103h, OR 183h)
      • Register 2-2: OPTION_REG � OPTION REGISTER (ADDRESS: 81h OR 181h)
      • Register 2-3: INTCON � INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, OR 18Bh)
      • Register 2-4: PIE1 � PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
      • Register 2-5: PIE2 � PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS: 8Dh)
      • Register 2-6: PIR1 � PERIPHERAL INTERRUPT Request REGISTER 1 (ADDRESS: 0Ch)
      • Register 2-7: PIR2 � PERIPHERAL INTERRUPT Request REGISTER 2 (ADDRESS: 0Dh)
      • Register 2-8: PCON � POWER CONTROL REGISTER (ADDRESS: 8Eh)
  • 2.3 PCL and PCLATH
    • FIGURE 2-5: Loading Of PC In Different Situations
    • 2.3.1 computed goto
    • 2.3.2 Stack
  • 2.4 Program Memory Paging
    • EXAMPLE 2-1: Call of a Subroutine in Page 1 from Page 0
  • 2.5 Indirect Addressing, INDF and FSR Registers
    • EXAMPLE 2-2: Indirect Addressing
    • FIGURE 2-6: Direct/indirect Addressing PIC16F91X
• 3.0 Clock Sources
  • 3.1 Overview
    • FIGURE 3-1: PIC16F91X System Clock Block Diagram
    • Register 3-1: OSCCON � OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
  • 3.2 Clock Source Modes
  • 3.3 External Clock Modes
    • 3.3.1 Oscillator Start-up Timer (OST)
      • TABLE 3-1: Oscillator Delay Examples
    • 3.3.2 EC Mode
      • FIGURE 3-2: External Clock (EC) Mode Operation
    • 3.3.3 LP, XT, HS Modes
      • FIGURE 3-3: Quartz Crystal Operation (LP, XT or HS Mode)
      • FIGURE 3-4: Ceramic Resonator Operation (XT or HS Mode)
    • 3.3.4 External RC Modes
      • FIGURE 3-5: RC Mode
      • FIGURE 3-6: RCIO Mode
  • 3.4 Internal Clock Modes
    • 3.4.1 INTOSC and INTRCIO Modes
    • 3.4.2 HFINTOSC
      • Register 3-2: OSCTUNE � OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)
    • 3.4.3 LFINTOSC
    • 3.4.4 Frequency Select Bits (IRCF)
    • 3.4.5 HF and LF INTOSC Clock Switch Timing
  • 3.5 Clock Switching
    • 3.5.1 System Clock Select (SCS) bit
    • 3.5.2 Oscillator Start-up Time-out Status Bit
  • 3.6 Two-Speed Clock Start-up Mode
    • 3.6.1 Two-Speed Start-up Mode Configuration
    • 3.6.2 Two-Speed Start-up Sequence
    • 3.6.3 Checking External/Internal Clock Status
      • FIGURE 3-7: Two-Speed Start-Up
  • 3.7 Fail-Safe Clock Monitor
    • FIGURE 3-8: FSCM Block Diagram
    • 3.7.1 Fail-Safe Condition Clearing
      • FIGURE 3-9: FSCM Timing Diagram
    • 3.7.2 Reset or Wake-up From Sleep
      • TABLE 3-2: Summary Of Registers Associated With Clock Sources
• 4.0 I/O Ports
  • 4.1 PORTA and TRISA Registers
    • EXAMPLE 4-1: INITIALIZING PORTA
    • Register 4-1: PORTA � PORTA Register (ADDRESS: 05h)
    • Register 4-2: TRISA � PORTA Tri-state Register (ADDRESS: 85h)
    • 4.1.1 Pin Descriptions and Diagrams
      • FIGURE 4-1: Block Diagram of RA0
      • FIGURE 4-2: Block Diagram of RA1
      • FIGURE 4-3: Block Diagram of RA2
      • FIGURE 4-4: Block Diagram of RA3
      • FIGURE 4-5: Block Diagram of RA4
      • FIGURE 4-6: Block Diagram of RA5
      • FIGURE 4-7: Block Diagram of RA6
      • FIGURE 4-8: Block Diagram of RA7
      • TABLE 4-1: Summary of Registers Associated with PORTA
  • 4.2 PORTB and TRISB Registers
    • EXAMPLE 4-2: INITIALIZING PORTb
  • 4.3 Additional PORTB Pin Functions
    • 4.3.1 Weak Pull-ups
    • 4.3.2 Interrupt-on-change
      • Register 4-3: PORTB � PORTB Register (ADDRESS: 06h or 106h)
      • Register 4-4: TRISB � PORTB Tri-state Register (ADDRESS: 86h, 186h)
      • Register 4-5: IOCB � PORTB Interrupt-on-change Register (ADDRESS: 96h)
      • Register 4-6: WPUB � WEAK PULL-UP REGISTER (ADDRESS: 95h)
    • 4.3.3 Pin Descriptions and Diagrams
      • FIGURE 4-9: Block Diagram of RB<3:0>
      • FIGURE 4-10: Block Diagram of RB4
      • FIGURE 4-11: Block Diagram of RB5
      • FIGURE 4-12: Block Diagram of RB6
      • FIGURE 4-13: Block Diagram of RB7
      • TABLE 4-2: Summary of Registers Associated with PORTB
  • 4.4 PORTC and TRISC Registers
    • EXAMPLE 4-3: INITIALIZING PORTc
    • Register 4-7: PORTc � PORTc Register (ADDRESS: 07h)
    • Register 4-8: TRISC � PORTC Tri-state Register (ADDRESS: 87h)
    • 4.4.1 Pin Descriptions and Diagrams
      • FIGURE 4-14: Block Diagram of RC0
      • FIGURE 4-15: Block Diagram of RC1
      • FIGURE 4-16: Block Diagram of RC2
      • FIGURE 4-17: Block Diagram of RC3
      • FIGURE 4-18: Block Diagram of RC4
      • FIGURE 4-19: Block Diagram of RC5
      • FIGURE 4-20: Block Diagram of RC6
      • FIGURE 4-21: Block Diagram of RC7
      • TABLE 4-3: Summary of Registers Associated with PORTC
  • 4.5 PORTD and TRISD Registers
    • EXAMPLE 4-4: INITIALIZING PORTD
    • Register 4-9: PORTd � PORTd register (ADDRESS: 08h)
    • Register 4-10: TRISD � PORTD Tri-state Register (ADDRESS: 88h)
    • 4.5.1 Pin Descriptions and Diagrams
      • FIGURE 4-22: Block Diagram of RD0
      • FIGURE 4-23: Block Diagram of RD1
      • FIGURE 4-24: Block Diagram of RD2
      • FIGURE 4-25: Block Diagram of RD<7:3>
      • TABLE 4-4: Summary of Registers Associated with PORTD
  • 4.6 PORTE and TRISE Registers
    • EXAMPLE 4-5: INITIALIZING PORTE
    • Register 4-11: PORTE � PORTE Register (ADDRESS: 09h)
    • Register 4-12: TRISE � PORTe Tri-state Register (ADDRESS: 89h)
    • 4.6.1 Pin Descriptions and Diagrams
      • FIGURE 4-26: Block Diagram of RE<2:0>
      • FIGURE 4-27: Block Diagram of RE3/MCLR/Vpp
      • TABLE 4-5: Summary of Registers Associated with PORTE
• 5.0 Timer0 Module
  • 5.1 Timer0 Operation
  • 5.2 Timer0 Interrupt
    • FIGURE 5-1: Block Diagram Of The TIMER0/WDT Prescaler
  • 5.3 Using Timer0 with an External Clock
    • Register 5-1: OPTION_REG � OPTION REGISTER (ADDRESS: 81h OR 181h)
  • 5.4 Prescaler
    • 5.4.1 Switching Prescaler Assignment
      • EXAMPLE 5-1: CHANGING PRESCALER (TIMER0�WDT)
      • EXAMPLE 5-2: CHANGING PRESCALER (WDT�TIMER0)
      • TABLE 5-1: Registers Associated With TIMER0
• 6.0 Timer1 Module With Gate Control
  • FIGURE 6-1: TIMER1 On The PIC16F91X Block Diagram
  • 6.1 Timer1 Modes of Operation
  • 6.2 Timer1 Interrupt
  • 6.3 Timer1 Prescaler
  • 6.4 Timer1 Gate
    • FIGURE 6-2: TIMER1 Incrementing Edge
    • Register 6-1: T1CON � TIMER1 CONTROL REGISTER (ADDRESS: 10h)
  • 6.5 Timer1 Operation in Asynchronous Counter Mode
    • 6.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode
  • 6.6 TIMER1 OSCILLATOR
  • 6.7 Resetting Timer1 Using a CCP Trigger Output
  • 6.8 Resetting of Timer1 Register Pair (TMR1H, TMR1L)
  • 6.9 Timer1 Operation During Sleep
    • TABLE 6-1: Registers Associated With TIMER1
• 7.0 Timer2 Module
  • 7.1 Timer2 Operation
    • Register 7-1: T2CON � Timer2 Control Register (Address: 12H)
  • 7.2 Timer2 Interrupt
  • 7.3 Timer2 Output
    • FIGURE 7-1: Timer2 Block Diagram
    • TABLE 7-1: Registers Associated with Timer2
• 8.0 Comparator Module
  • Register 8-1: CMCON0 � COMPARATOR CONFIGURATION REGISTER (ADDRESS: 9Ch)
  • 8.1 Comparator Operation
    • TABLE 8-1: Output State vs. Input Conditions
    • FIGURE 8-1: Single Comparator
  • 8.2 Analog Input Connection Considerations
    • FIGURE 8-2: Analog Input Model
  • 8.3 Comparator Configuration
    • FIGURE 8-3: Comparator I/O Operating Modes
    • FIGURE 8-4: Modified Comparator C1 Output Block Diagram
    • FIGURE 8-5: Comparator C2 Output Block Diagram
    • Register 8-2: CMCON1 � COMPARATOR CONFIGURATION REGISTER (ADDRESS: 97h)
  • 8.4 Comparator Outputs
  • 8.5 Comparator Interrupts
  • 8.6 Comparator Reference
    • 8.6.1 Configuring the Voltage Reference
      • EQUATION 8-1:
    • 8.6.2 Voltage Reference Accuracy/Error
      • FIGURE 8-6: Comparator Voltage Reference Block Diagram
  • 8.7 Comparator Response Time
  • 8.8 Operation During Sleep
  • 8.9 Effects of a Reset
    • Register 8-3: VRCON � VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh)
    • TABLE 8-2: Registers Associated With Comparator Module
• 9.0 Liquid Crystal Display (LCD) Driver Module
  • FIGURE 9-1: LCD Driver Module Block Diagram
  • Register 9-1: LCDCON � Liquid Crystal Display Control Register (Address: 107h)
  • Register 9-2: LCDPS � LCD Prescaler Select Register (Address: 108h)
  • Register 9-3: LCDSEn � LCD Segment Registers (Address: 11Ch, 11Dh, or 11Eh)
  • Register 9-4: LCDDATAx � LCD Data Registers (Address: 110h-119h, 11Ah, 11Bh)
  • 9.1 LCD Clock Source Selection
    • 9.1.1 LCD Prescaler
  • 9.2 LCD Bias Types
    • FIGURE 9-2: LCD Bias Resistor Ladder Connection Diagram
  • 9.3 LCD Multiplex Types
    • TABLE 9-1: PORTC<2:0> Function
  • 9.4 Segment Enables
  • 9.5 Pixel Control
  • 9.6 LCD Frame Frequency
    • TABLE 9-2: Frame Frequency Formulas
    • TABLE 9-3: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or INTOsc
    • FIGURE 9-3: LCD Clock Generation
    • FIGURE 9-4: LCD Segment Mapping Worksheet
  • 9.7 LCD Waveform Generation
    • FIGURE 9-5: Type-A/Type-B Waveforms in Static Drive
    • FIGURE 9-6: Type-A Waveforms in 1/2 Mux, 1/2 Bias Drive
    • FIGURE 9-7: Type-B Waveforms in 1/2 Mux, 1/2 Bias Drive
    • FIGURE 9-8: Type-A Waveforms in 1/2 Mux, 1/3 Bias Drive
    • FIGURE 9-9: Type-B Waveforms in 1/2 Mux, 1/3 Bias Drive
    • FIGURE 9-10: Type-A Waveforms in 1/3 Mux, 1/2 Bias Drive
    • FIGURE 9-11: Type-B Waveforms in 1/3 Mux, 1/2 Bias Drive
    • FIGURE 9-12: Type-A Waveforms in 1/3 Mux, 1/3 Bias Drive
    • FIGURE 9-13: Type-B Waveforms in 1/3 Mux, 1/3 Bias Drive
    • FIGURE 9-14: Type-A Waveforms in 1/4 Mux, 1/3 Bias Drive
    • FIGURE 9-15: Type-B Waveforms in 1/4 Mux, 1/3 Bias Drive
  • 9.8 LCD Interrupts
    • FIGURE 9-16: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example � Type-B, Non-St...
  • 9.9 Operation During Sleep
    • TABLE 9-4: LCD Module Status During Sleep
    • FIGURE 9-17: Sleep Entry/Exit when SLPEN = 1 or CS<1:0> = 00
  • 9.10 Configuring the LCD Module
    • TABLE 9-5: Registers Associated with LCD Operation
• 10.0 Programmable Low-Voltage Detect (PLVD) Module
  • 10.1 Voltage Trip Points
    • 10.1.1 PLVD Calibration
      • Register 10-1: LVDCON � Low-Voltage Detect Control Register (Address: 109h)
      • TABLE 10-1: Registers Associated with Programmable Low-Voltage Detect
• 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
  • Register 11-1: TXSTA � Transmit Status and Control Register (Address 98h)
  • Register 11-2: RCSTA � Receive Status and Control Register (Address 18h)
  • 11.1 USART Baud Rate Generator (BRG)
    • 11.1.1 SAMPLING
      • TABLE 11-1: Baud Rate Formula
      • TABLE 11-2: Registers Associated with Baud Rate Generator
      • TABLE 11-3: Baud Rates for Asynchronous Mode (BRGH = 0)
      • TABLE 11-4: Baud Rates for Asynchronous Mode (BRGH = 1)
  • 11.2 USART Asynchronous Mode
    • 11.2.1 USART Asynchronous Transmitter
      • FIGURE 11-1: USART Transmit Block Diagram
      • FIGURE 11-2: Asynchronous Master Transmission
      • FIGURE 11-3: Asynchronous Master Transmission (Back to Back)
      • TABLE 11-5: Registers Associated with Asynchronous Transmission
    • 11.2.2 USART Asynchronous Receiver
      • FIGURE 11-4: USART Receive Block Diagram
      • FIGURE 11-5: Asynchronous Reception
      • TABLE 11-6: Registers Associated with Asynchronous Reception
    • 11.2.3 Setting up 9-bit mode with Address Detect
      • FIGURE 11-6: USART Receive Block Diagram
      • FIGURE 11-7: Asynchronous Reception with Address Detect
      • FIGURE 11-8: Asynchronous Reception with Address Byte First
      • TABLE 11-7: Registers Associated with Asynchronous Reception
  • 11.3 USART Synchronous Master Mode
    • 11.3.1 USART Synchronous Master Transmission
      • TABLE 11-8: Registers Associated with Synchronous Master Transmission
      • FIGURE 11-9: Synchronous Transmission
      • FIGURE 11-10: Synchronous Transmission (Through TXEN)
    • 11.3.2 USART Synchronous Master Reception
      • TABLE 11-9: Registers Associated with Synchronous Master Reception
      • FIGURE 11-11: Synchronous Reception (Master Mode, SREN)
  • 11.4 USART Synchronous Slave Mode
    • 11.4.1 USART Synchronous Slave Transmit
      • TABLE 11-10: Registers Associated with Synchronous Slave Transmission
    • 11.4.2 USART Synchronous Slave Reception
      • TABLE 11-11: Registers Associated with Synchronous Slave Reception
• 12.0 Analog-to-Digital Converter (A/D) Module
  • FIGURE 12-1: A/D Block Diagram
  • 12.1 A/D Configuration and Operation
    • 12.1.1 Analog Port Pins
    • 12.1.2 Channel Selection
    • 12.1.3 Voltage Reference
    • 12.1.4 Conversion Clock
      • TABLE 12-1: Tad vs. Device Operating Frequencies
    • 12.1.5 Starting a Conversion
      • FIGURE 12-2: A/D Conversion Tad Cycles
    • 12.1.6 Conversion Output
      • FIGURE 12-3: 10-Bit A/D Result Format
      • Register 12-1: ANSEL � Analog Select Register (Address: 91H)
      • Register 12-2: ADCON0 � A/D Control Register (Address: 1Fh)
      • Register 12-3: ADCON1 � A/D Control Register 1 (Address: 9FH)
    • 12.1.7 Configuring the A/D
      • EXAMPLE 12-1: A/D Conversion
  • 12.2 A/D Acquisition Requirements
    • EQUATION 12-1: Acquisition Time
    • FIGURE 12-4: Analog Input Model
  • 12.3 A/D Operation During Sleep
    • FIGURE 12-5: A/D Transfer Function
  • 12.4 Effects of Reset
    • TABLE 12-2: Summary Of A/D Registers
• 13.0 Data EEPROM and Flash Program Memory Control
  • 13.1 EEADRL and EEADRH Registers
    • 13.1.1 EECON1 and EECON2 Registers
      • Register 13-1: EEDATL � EEPROM Data lOW bYTE Register (Address: 10Ch)
      • Register 13-2: EEADRL � EEPROM Address lOW bYTE Register (Address: 10Dh)
      • Register 13-3: EEDATH � EEPROM Data hIGH bYTE Register (Address: 10Eh)
      • Register 13-4: EEADRH � EEPROM Address hIGH bYTE Register (Address: 10Fh)
      • Register 13-5: EECON1 � EEPROM Control Register 1 (Address: 18Ch)
    • 13.1.2 Reading the Data EEPROM Memory
      • EXAMPLE 13-1: Data EEPROM Read
    • 13.1.3 Writing to the Data EEPROM Memory
      • EXAMPLE 13-2: Data EEPROM Write
    • 13.1.4 Reading the Flash Program Memory
      • EXAMPLE 13-3: Flash PROGRAM Read
      • FIGURE 13-1: Flash Program Memory Read Cycle Execution
      • TABLE 13-1: Registers/Bits Associated With Data Eeprom
• 14.0 SSP Module Overview
  • 14.1 SPI Mode
    • Register 14-1: SSPSTAT � Sync Serial Port Status Register (ADDRESS 94h)
    • Register 14-2: SSPCON � Sync Serial Port Control Register (ADDRESS 14h)
    • FIGURE 14-1: SSP Block Diagram (SPIMode)
  • 14.2 Operation
    • EXAMPLE 14-1: Loading the SSPBUF (SSPSR) Register
  • 14.3 Enabling SPI I/O
  • 14.4 Typical Connection
    • FIGURE 14-2: SPI� Master/Slave Connection
  • 14.5 Master Mode
    • FIGURE 14-3: SPI� Mode Waveform (Master Mode)
  • 14.6 Slave Mode
  • 14.7 Slave Select Synchronization
    • FIGURE 14-4: Slave Synchronization Waveform
    • FIGURE 14-5: SPI� Mode Waveform (Slave Mode with CKE = 0)
    • FIGURE 14-6: SPI� Mode Waveform (Slave Mode with CKE = 1)
  • 14.8 Sleep Operation
  • 14.9 Effects of a Reset
  • 14.10 Bus Mode Compatibility
    • TABLE 14-1: SPI� Bus Modes
    • TABLE 14-2: Registers Associated with SPI� Operation
  • 14.11 SSP I2 C Operation
    • FIGURE 14-7: SSP Block Diagram (I2 C� Mode)
  • 14.12 Slave Mode
    • 14.12.1 Addressing
      • TABLE 14-3: Data Transfer Received Byte Actions
    • 14.12.2 Reception
      • FIGURE 14-8: I2 C� Waveforms for Reception (7-bit Address)
      • FIGURE 14-9: I2C� Slave Mode Timing (Reception, 10-bit Address)
    • 14.12.3 Transmission
      • FIGURE 14-10: I2 C� Waveforms for Transmission (7-bit Address)
      • FIGURE 14-11: I2C� Slave Mode Timing (Transmission, 10-bit Address)
  • 14.13 Master Mode
  • 14.14 Multi-master Mode
    • 14.14.1 Clock Synchronization and the CKP Bit
      • FIGURE 14-12: Clock synchronization Timing
      • TABLE 14-4: Registers Associated with I2 C� Operation
• 15.0 Capture/Compare/PWM Modules
  • TABLE 15-1: CCP Mode - Timer ResourceS REQUIRED
  • TABLE 15-2: Interaction of Two CCP Modules
  • Register 15-1: CCP1CON � CCP2CON(1) Register (Address: 17h/1DH)
  • 15.1 Capture Mode
    • 15.1.1 CCP pin Configuration
      • FIGURE 15-3: Capture Mode Operation Block Diagram
    • 15.1.2 Timer1 Mode Selection
    • 15.1.3 Software Interrupt
    • 15.1.4 CCP Prescaler
      • EXAMPLE 15-1: Changing between capture prescalers
  • 15.2 Compare Mode
    • FIGURE 15-4: Compare Mode Operation Block Diagram
    • 15.2.1 CCP Pin Configuration
    • 15.2.2 timer1 Mode Selection
    • 15.2.3 Software Interrupt Mode
    • 15.2.4 Special Event Trigger
  • 15.3 PWM Mode (PWM)
    • FIGURE 15-5: Simplified PWM Block Diagram
    • FIGURE 15-6: PWM Output
    • 15.3.1 PWM period
    • 15.3.2 PWM Duty Cycle
    • 15.3.3 Setup for PWM Operation
      • TABLE 15-1: Example PWM Frequencies and Resolutions at 20 MHz
      • TABLE 15-2: Registers Associated with Capture, compare and Timer1
      • TABLE 15-3: Registers Associated with PWM and Timer2
• 16.0 Special Features of the CPU
  • 16.1 Configuration Bits
    • Register 16-1: CONFIG � Configuration Word (Address: 2007h)
  • 16.2 Reset
    • FIGURE 16-1: Simplified Block Diagram Of On-Chip Reset Circuit
  • 16.3 Power-on Reset
    • 16.3.1 MCLR
      • FIGURE 16-2: Recommended MCLR Circuit
    • 16.3.2 Power-up Timer (PWRT)
    • 16.3.3 Brown-Out Reset (BOR)
    • 16.3.4 BOR Calibration
      • FIGURE 16-3: Brown-Out Situations
    • 16.3.5 Time-out Sequence
    • 16.3.6 Power Control (PCON) Register
      • TABLE 16-1: Time-Out In Various Situations
      • TABLE 16-2: PCON Bits And Their Significance
      • TABLE 16-3: Summary Of Registers Associated With Brown-Out
      • FIGURE 16-4: Time-Out Sequence On Power-Up (Delayed MCLR): Case 1
      • FIGURE 16-5: Time-Out Sequence On Power-Up (Delayed MCLR): Case 2
      • FIGURE 16-6: Time-Out Sequence On Power-Up (MCLR With Vdd): Case 3
      • TABLE 16-4: Initialization Condition for Registers
      • TABLE 16-5: Initialization Condition For Special Registers
  • 16.4 Interrupts
    • 16.4.1 RB0/INT/SEG0 Interrupt
    • 16.4.2 TMR0 Interrupt
    • 16.4.3 PORTB Interrupt
      • FIGURE 16-7: Interrupt Logic
      • FIGURE 16-8: INT Pin Interrupt Timing
      • TABLE 16-6: Summary Of Interrupt Registers
  • 16.5 Context Saving During Interrupts
    • EXAMPLE 16-1: Saving Status and W Registers in RAM
  • 16.6 Watchdog Timer (WDT)
    • 16.6.1 WDT Oscillator
    • 16.6.2 WDT Control
      • FIGURE 16-9: Watchdog Timer Block Diagram
      • TABLE 16-7: WDT Status
      • Register 16-2: WDTCON � Watchdog Timer Control Register (Address: 105H)
      • TABLE 16-8: Summary Of Watchdog Timer Registers
  • 16.7 Power-Down Mode (Sleep)
    • 16.7.1 Wake-up from Sleep
    • 16.7.2 Wake-up Using Interrupts
      • FIGURE 16-10: Wake-Up From Sleep Through Interrupt
  • 16.8 Code Protection
  • 16.9 ID Locations
  • 16.10 In-Circuit Serial Programming
    • FIGURE 16-11: Typical In-Circuit Serial Programming Connection
  • 16.11 In-Circuit Debugger
    • 16.11.1 ICD Pinout
      • TABLE 16-9: PIC16F91X-ICD Pin Descriptions
• 17.0 Instruction Set Summary
  • 17.1 READMODIFY-WRITE OPERATIONS
    • TABLE 17-1: Opcode Field Descriptions
    • FIGURE 17-1: General Format For Instructions
    • TABLE 17-2: PIC16F91X Instruction Set
  • 17.2 Instruction Descriptions
• 18.0 Development Support
  • 18.1 MPLAB Integrated Development Environment Software
  • 18.2 MPASM Assembler
  • 18.3 MPLAB C17 and MPLAB C18 C Compilers
  • 18.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 18.5 MPLAB C30 C Compiler
  • 18.6 MPLAB ASM30 Assembler, Linker and Librarian
  • 18.7 MPLAB SIM Software Simulator
  • 18.8 MPLAB SIM30 Software Simulator
  • 18.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
  • 18.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
  • 18.11 MPLAB ICD 2 In-Circuit Debugger
  • 18.12 PRO MATE II Universal Device Programmer
  • 18.13 MPLAB PM3 Device Programmer
  • 18.14 PICSTART Plus Development Programmer
  • 18.15 PICDEM 1 PICmicro Demonstration Board
  • 18.16 PICDEM.net Internet/Ethernet Demonstration Board
  • 18.17 PICDEM 2 Plus Demonstration Board
  • 18.18 PICDEM 3 PIC16C92X Demonstration Board
  • 18.19 PICDEM 4 8/14/18-Pin Demonstration Board
  • 18.20 PICDEM 17 Demonstration Board
  • 18.21 PICDEM 18R PIC18C601/801 Demonstration Board
  • 18.22 PICDEM LIN PIC16C43X Demonstration Board
  • 18.23 PICkitTM 1 Flash Starter Kit
  • 18.24 PICDEM USB PIC16C7X5 Demonstration Board
  • 18.25 Evaluation and Programming Tools
• 19.0 Electrical Specifications
  • FIGURE 19-1: PIC16F91X Voltage-Frequency Graph, -40C � ta � +125C
  • 19.1 DC Characteristics: PIC16F91X -I (Industrial) PIC16F91X -E (Extended)
  • 19.2 DC Characteristics: PIC16F91X-I (Industrial)
  • 19.3 DC Characteristics: PIC16F91X-E (Extended)
  • 19.4 DC Characteristics: PIC16F91X-I (Industrial), PIC16F91X-E (Extended) 
  • 19.5 Timing Parameter Symbology
    • FIGURE 19-2: Load Conditions
  • 19.6 AC Characteristics: PIC16F91X (Industrial, Extended)
    • FIGURE 19-3: External Clock Timing
    • TABLE 19-1: External Clock Timing Requirements
    • TABLE 19-2: Precision Internal Oscillator Parameters
    • FIGURE 19-4: CLKO And I/O Timing
    • TABLE 19-3: CLKO And I/O Timing Requirements
    • FIGURE 19-5: Reset, Watchdog Timer, Oscillator Start-Up Timer And Power-Up Timer Timing
    • FIGURE 19-6: Brown-Out Reset Timing And Characteristics
    • TABLE 19-4: Reset, Watchdog Timer, Oscillator Start-Up Timer, Power-Up Timer And Brown-Out Reset ...
    • FIGURE 19-7: TIMER0 And TIMER1 External Clock Timings
    • TABLE 19-5: TIMER0 And TIMER1 External Clock Requirements
    • FIGURE 19-8: USART Synchronous Transmission (Master/Slave) Timing
    • TABLE 19-6: USART Synchronous Transmission Requirements
    • FIGURE 19-9: USART Synchronous Receive (Master/Slave) Timing
    • TABLE 19-7: USART Synchronous Receive Requirements
    • FIGURE 19-10: Capture/Compare/PWM Timings
    • TABLE 19-8: Capture/Compare/PWM Requirements
    • TABLE 19-9: Comparator Specifications
    • TABLE 19-10: COmparator Voltage Reference Specifications
    • TABLE 19-11: PIC16F91X PLVD Characteristics:
    • FIGURE 19-11: SPI� Master Mode Timing (CKE=0, smp = 0)
    • FIGURE 19-12: SPI� Master Mode Timing (CKE=1, SMP = 1)
    • FIGURE 19-13: SPI� Slave Mode Timing (CKE=0)
    • FIGURE 19-14: SPI� Slave Mode Timing (CKE=1)
    • TABLE 19-12: SPI� Mode requirements
    • FIGURE 19-15: I2C� Bus Start/Stop Bits Timing
    • TABLE 19-13: I2C� Bus Start/Stop Bits Requirements
    • FIGURE 19-16: I2C� Bus Data Timing
    • TABLE 19-14: I2C� Bus Data Requirements
    • TABLE 19-15: PIC16F91X A/D Converter Characteristics:
    • FIGURE 19-17: PIC16F91X A/D Conversion Timing (Normal Mode)
    • TABLE 19-16: PIC16F91X A/D Conversion Requirements
• 20.0 DC and AC Characteristics Graphs and Tables
• 21.0 Packaging Information
  • 21.1 Package Marking Information
  • 21.2 Package Details
• Appendix A: Data Sheet Revision History
• Appendix B: Migrating From Other PICmicro� Devices
• Appendix C: Conversion Considerations
• INDEX
• Worldwide Sales and Service