2003 Microchip Technology Inc.
DS21178D-page 1
24AA00/24LC00/24C00
Device Selection Table
Features
Low-power CMOS technology
- 500
A typical active current
- 250 nA typical standby current
Organized as 16 bytes x 8 bits
2-wire serial interface bus, I
2
CTM compatible
100 kHz (1.8V) and 400 kHz (5V) compatibility
Self-timed write cycle (including auto-erase)
4 ms maximum byte write cycle time
1,000,000 erase/write cycles
ESD protection > 4 kV
Data retention > 200 years
8L DIP, SOIC, TSSOP and 5L SOT-23 packages
Standard or Pb-free finish available
Temperature ranges available:
Description
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM memory organized as 16 x 8 with a 2-wire serial
interface. Low voltage design permits operation down
to 1.8 volts for the 24XX00 version, and every version
maintains a maximum standby current of only 1
A and
typical active current of only 500
A. This device was
designed for where a small amount of EEPROM is
needed for the storage of calibration values, ID
numbers or manufacturing information, etc. The
24XX00 is available in 8-pin PDIP, 8-pin SOIC (150
mil), 8-pin TSSOP and the 5-pin SOT-23 packages.
Package Types
Block Diagram
Pin Function Table
Device
V
CC
Range
Temp Range
24AA00
1.8 - 5.5
C,I
24LC00
2.5 - 5.5
C,I
24C00
4.5 - 5.5
C,I,E
- Commercial (C):
0
C
to
+70
C
- Industrial (I):
-40
C
to
+85
C
- Automotive (E):
-40
C
to +125
C
Name
Function
V
SS
Ground
SDA
Serial Data
SCL
Serial Clock
V
CC
+1.8V to 5.5V (24AA00)
+2.5V to 5.5V (24LC00)
+4.5V to 5.5V (24C00)
NC
No Internal Connection
24X
X00
1
2
3
4
8
7
6
5
1
5
4
3
24
XX00
2
4
XX00
8-PIN PDIP/SOIC
8-PIN TSSOP
5-PIN SOT-23
NC
NC
NC
Vss
V
CC
NC
SCL
SDA
NC
NC
NC
V
SS
V
CC
NC
SCL
SDA
SCL
V
SS
SDA
V
CC
NC
1
2
3
4
8
7
6
5
2
HV Generator
EEPROM
Array
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
SDA
SCL
V
CC
V
SS
128 Bit I
2
C
TM
Bus Serial EEPROM
I
2
C is a trademark of Philips Corporation.
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
24AA00/24LC00/24C00
DS21178D-page 2
2003 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
()
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied ................................................................................................-65C to +125C
ESD protection on all pins .......................................................................................................................................... 4 kV
FIGURE 1-1:
BUS TIMING DATA
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All Parameters apply across the
recommended operating ranges unless
otherwise noted
Commercial (C):
T
A
= 0C to +70C,
V
CC
= 1.8V to 5.5V
Industrial (I):
T
A
= -40C to +85C,
V
CC
= 1.8V to 5.5V
Automotive (E)
T
A
= -40C to +125C,
V
CC
= 4.5V to 5.5V
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High-level input voltage
V
IH
0.7 V
CC
V
(Note)
Low-level input voltage
V
IL
0.3 V
CC
V
(Note)
Hysteresis of Schmitt Trigger
inputs
V
HYS
.05 V
CC
--
V
V
CC
2.5V (Note)
Low-level output voltage
V
OL
0.4
V
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, V
CC
= 2.5V
Input leakage current
I
LI
--
1
A
V
IN
= V
CC
or V
SS
Output leakage current
I
LO
--
1
A
V
OUT
= V
CC
or V
SS
Pin capacitance (all inputs/outputs)
C
IN
,
C
OUT
--
10
pF
V
CC
= 5.0V (Note)
T
A
= 25C, f = 1 MHz
Operating current
I
CC
Write
--
2
mA
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Read
--
1
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
--
1
A
V
CC
= 5.5V, SDA = SCL = V
CC
Note:
This parameter is periodically sampled and not 100% tested.
T
F
T
HIGH
T
R
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
SP
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
2003 Microchip Technology Inc.
DS21178D-page 3
24AA00/24LC00/24C00
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Commercial (C):
T
A
= 0C to +70C,
V
CC
= 1.8V to 5.5V
Industrial (I) :
T
A
= -40C to +85C,
V
CC
= 1.8V to 5.5V
Automotive (E):
T
A
= -40C to +125C, V
CC
= 4.5V to 5.5V
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
--
--
--
100
100
400
kHz
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Clock high time
T
HIGH
4000
4000
600
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Clock low time
T
LOW
4700
4700
1300
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
SDA and SCL rise time
(Note 1)
T
R
--
--
--
1000
1000
300
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
SDA and SCL fall time
T
F
--
300
ns
(Note 1)
Start condition hold time
T
HD
:
STA
4000
4000
600
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Start condition setup time
T
SU
:
STA
4700
4700
600
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Data input hold time
T
HD
:
DAT
0
--
ns
(Note 2)
Data input setup time
T
SU
:
DAT
250
250
100
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Stop condition setup time
T
SU
:
STO
4000
4000
600
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Output valid from clock
(Note 2)
T
AA
--
--
--
3500
3500
900
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
T
BUF
4700
4700
1300
--
--
--
ns
4.5V
Vcc
5.5V (E Temp range)
1.8V
Vcc
4.5V
4.5V
Vcc
5.5V
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
20+0.1
CB
250
ns
(Note 1), CB
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
--
50
ns
(Notes 1, 3)
Write cycle time
T
WC
--
4
ms
Endurance
1M
--
cycles
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total EnduranceTM Model which can be obtained on www.microchip.com.
24AA00/24LC00/24C00
DS21178D-page 4
2003 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
2003 Microchip Technology Inc.
DS21178D-page 5
24AA00/24LC00/24C00
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 4-2).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24XX00 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
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