1997 Microchip Technology Inc.
Preliminary
DS21233A-page 1
M
24C01B/02B
FEATURES
Single supply with 5.0V operation
Low power CMOS technology
- 1 mA active current typical
- 10
A standby current typical at 5.0V
- 5
A standby current typical at 5.0V
Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
2-wire serial interface bus, I
2
C compatible
100 kHz compatibility
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
2 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
ESD protection > 3,000V
1,000,000 ERASE/WRITE cycles guaranteed
Data retention > 200 years
8 pin DIP or SOIC package
Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24C01B and 24C02B
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single block of 128 x 8 bit or
256 x 8 bit memory with a 2-wire serial interface. The
24C01B and 24C02B also have page-write capability
for up to 8 bytes of data. The 24C01B and 24C02B are
available in the standard 8-pin DIP and an 8-pin surface
mount SOIC package.
These devices are for extended temperature
applications only. It is recommended that all other
applications use Microchip's 24LC01B/02B.
PACKAGE TYPES
BLOCK DIAGRAM
- Automotive (E):
-40C to
+125C
24C01B/02B
24C01B/02B
1
2
3
4
8
7
6
5
NC
NC
NC
Vss
Vcc
WP
SCL
SDA
NC
NC
NC
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA
SCL
V
CC
V
SS
1K/2K 5.0V I
2
C
TM
Serial EEPROM
I
2
C is a trademark of Philips Corporation.
24C01B/02B
DS21233A-page 2
Preliminary
1997 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
................-0.6V to V
CC
+1.0V
Storage temperature ..................................... -65C to +150C
Ambient temp. with power applied................. -65C to +125C
Soldering temperature of leads (10 seconds) ............. +300C
ESD protection on all pins.............................................
4 kV
*Notice:
Stresses above those listed under "Maximum ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
FIGURE 1-1:
BUS TIMING START/STOP
Name
Function
V
SS
SDA
SCL
WP
V
CC
NC
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5.0V Power Supply
No Internal Connection
TABLE 1-1:
DC CHARACTERISTICS
All parameters apply across the speci-
fied operating ranges unless otherwise
noted.
V
CC
= +4.5V to 5.5V
Automotive (E):
Tamb = -40
C to 125
C
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
V
Low level input voltage
V
IL
.3 V
CC
V
Hysteresis of Schmidt trigger inputs
V
HYS
.05 V
CC
--
V
(Note)
Low level output voltage
V
OL
.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
A
V
IN
= .1V to 5.5V
Output leakage current
I
LO
-10
10
mA
V
OUT
= .1V to 5.5V
Pin capacitance (all inputs/outputs)
C
IN
,
C
OUT
--
10
pF
V
CC
= 5.0V (Note 1)
Tamb = 25C, F
CLK
= 1 MHz
Operating current
I
CC
Write
--
3
mA
V
CC
= 5.5V, SCL = 100 kHz
I
CC
Read
--
1
mA
Standby current
I
CCS
--
30
A
V
CC
= 3.0V, SDA = SCL = V
CC
100
A
V
CC
= 5.5V, SDA = SCL = V
CC
Note:
This parameter is periodically sampled and not 100% tested.
SCL
SDA
T
SU
:
STA
T
HD
:
STA
START
STOP
V
HYS
T
SU
:
STO
24C01B/02B
1997 Microchip Technology Inc.
Preliminary
DS21233A-page 3
FIGURE 1-2:
BUS TIMING DATA
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across the
specified operating ranges unless
otherwise noted
Vcc = 4.5V to 5.5V
Automotive (E):
Tamb = -40C to +125C,
Parameter
Symbol
Min.
Max.
Units
Remarks
Clock frequency
F
CLK
--
100
kHz
Clock high time
T
HIGH
4000
--
ns
Clock low time
T
LOW
4700
--
ns
SDA and SCL rise time
T
R
--
1000
ns
(Note 1)
SDA and SCL fall time
T
F
--
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
--
ns
After this period the first clock pulse is
generated
START condition setup time
T
SU
:
STA
4700
--
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
--
ns
(Note 2)
Data input setup time
T
SU
:
DAT
250
--
ns
STOP condition setup time
T
SU
:
STO
4000
--
ns
Output valid from clock
T
AA
--
3500
ns
(Note 2)
Bus free time
T
BUF
4700
--
ns
Time the bus must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
--
250
ns
(Note 1), CB
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
--
50
ns
(Note 3)
Write cycle time
T
WR
--
10
ms
Byte or Page mode
Endurance
--
1M
--
cycles
25
C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
T
SU
:
STA
T
F
T
HIGH
T
R
T
SU
:
STO
T
SU
:
DAT
T
HD
:
DAT
T
BUF
T
AA
T
HD
:
STA
T
AA
T
SP
T
LOW
24C01B/02B
DS21233A-page 4
Preliminary
1997 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24C01B/02B supports a bi-directional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C01B/02B works as slave. Both master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24C01B/02B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
SCL
SDA
(
A
)
(B)
(D)
(D)
(C)
(
A
)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
24C01B/02B
1997 Microchip Technology Inc.
Preliminary
DS21233A-page 5
3.6
Device Address
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01B/02B, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24C01B/02B
(Figure 3-2).
The 24C01B/02B monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24C01B/02B. After
receiving another acknowledge signal from the
24C01B/02B the master device will transmit the data
word to be written into the addressed memory location.
The 24C01B/02B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24C01B/02B will
not generate acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24C01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
Operation
Control
Code
Chip
Select
R/W
Read
Write
1010
1010
XXX
XXX
1
0
X = Don't care
R/W
A
1
0
1
0
X
X
X
READ/WRITE
START
SLAVE ADDRESS
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATAn + 7
DATAn + 1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
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