1998 Microchip Technology Inc.
DS21125D-page 1
FEATURES
Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Maximum read current 150
A at 5.5V
- Standby current 1
A typical
1 MHz SE2.bus two wire protocol
Up to eight devices may be connected to the
same bus for up to 512K bits total memory
Programmable block security options
Programmable endurance options
Schmitt trigger inputs for noise suppression
Self-timed ERASE and WRITE cycles
Power on/off data protection circuitry
Endurance:
- 10,000,000 E/W cycles guaranteed for a 4K
block
- 1,000,000 E/W cycles guaranteed for a 60K
block
Variable page size up to 64 bytes
8 byte x 8 line input cache (64 bytes)
for fast write loads
<3 ms typical write cycle time, byte or page
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP/SOIC packages
Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24FC65 is a "smart"
8K 8x 8 Serial Electrically Erasable PROM (EEPROM)
with a high-speed 1MHz SE2.bus whose protocol is
functionally equivalent to the industry-standard I
2
C
bus. This device has been developed for advanced
applications such as personal communications, and
provides the systems designer with flexibility through
the use of many new user-programmable features. The
24FC65 offers a relocatable 4K-bit block of
ultra-high-endurance memory for data that changes
frequently. The remainder of the array, or 60K bits, is
rated at 1,000,000 ERASE/WRITE (E/W) cycles
guaranteed. The 24FC65 features an input cache for
fast write loads with a capacity of eight pages, or 64
bytes. This device also features programmable
security options for E/W protection of critical data
and/or code of up to fifteen 4K blocks. Functional
- Commercial (C):
0
C to +70
C
- Industrial (I):
-40
C to +85
C
address lines allow the connection of up to eight
24FC65's on the same bus for up to 512K bits
contiguous EEPROM memory. The 24FC65 is available
in the standard 8-pin plastic DIP and 8-pin surface
mount SOIC package.
24FC65
64K 5.0V 1 MHz I
2
C
TM
Smart Serial
TM
EEPROM
PACKAGE TYPES
BLOCK DIAGRAM
24FC65
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
24FC65
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
SDA
SCL
V
CC
V
SS
I/O
A2
A1
A0
CACHE
I
2
C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
24FC65
DS21125D-page 2
1998 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
................-0.6V to V
CC
+1.0V
Storage temperature .....................................-65
C to +150
C
Ambient temp. with power applied.................-65
C to +125
C
Soldering temperature of leads (10 seconds) ............. +300
C
ESD protection on all pins
..................................................
4 kV
*Notice:
Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
A0,A1,A2
User Configurable Chip Selects
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
V
CC
+4.5V to 5.5V Power Supply
NC
No Internal Connection
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
V
CC
= +4.5V to +5.5V
Commercial (C): Tamb = 0
C to +70
C
Industrial (I):
Tamb = -40
C to +85
C
Parameter
Symbol
Min
Max
Units
Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of SCL and SDA
Low level output voltage of SDA
V
IH
V
IL
V
HYS
V
OL
0.7 V
CC
--
0.05 V
CC
--
--
0.3 Vcc
--
0.40
V
V
V
V
(Note)
I
OL
= 3.0 mA
Input leakage current
I
LI
-10
10
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
A
V
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
INT
--
10
pF
V
CC
= 5.0V (Note)
Tamb = 25C, F
CLK
= 1 MHz
Operating current
I
CC
Write
I
CC
Read
--
--
3
150
mA
A
V
CC
= 5.5V, SCL = 1 MH
Z
V
CC
= 5.5V, SCL = 1 MHz
Standby current
I
CCS
--
5
A
V
CC
= 5.5V, SCL = SDA =V
CC
A0, A1, A2 = V
SS
Note: This parameter is periodically sampled and not 100% tested.
SCL
SDA
START
STOP
V
HYS
T
SU
:
STO
T
HD
:
STA
T
SU
:
STA
1998 Microchip Technology Inc.
DS21125D-page 3
24FC65
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
1 MHz Bus
Units
Remarks
Min
Max
Clock frequency
F
CLK
0
1000
kHz
Clock high time
THIGH
500
--
ns
Clock low time
T
LOW
500
--
ns
SDA and SCL rise time
T
R
--
300
ns
(Note 1)
SDA and SCL fall time
T
F
--
100
ns
(Note 1)
START hold time
T
HD
:
STA
250
--
ns
After this period the first clock pulse is
generated
START setup time
T
SU
:
STA
250
--
ns
Only relevant for repeated START
Data input hold time
T
HD
:
DAT
0
--
ns
Data input setup time
T
SU
:
DAT
100
--
ns
STOP setup time
T
SU
:
STO
250
--
ns
Output valid from clock
T
AA
--
350
ns
(Note 2)
Bus free time
T
BUF
500
--
ns
Time the bus must be free before a
new transmission can start
Write cycle time
T
WR
--
5
ms/page (Note 3)
Endurance
High Endurance Block
Rest of Array
10M
1M
--
--
cycles
25
C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100 percent tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOPs.
3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24FC65
DS21125D-page 4
1998 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24FC65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOPs, while the 24FC65 works as slave.
Both master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START. All
commands must be preceded by a START.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP. All
operations must be ended with a STOP.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START, the data line is stable for the duration of
the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START and
terminated with a STOP. The number of the data bytes
transferred between the START and STOPs is
determined by the master device.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account.
During reads, a master must signal an end of data to
the slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24FC65) must leave the data line
HIGH to enable the master to generate the STOP.
Note:
The 24FC65 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A)
(B)
START
(C)
(A)
(D)
(D)
Address
or
Acknowledge
Valid
Data Allowed
to Change
STOP
Condition
Condition
1998 Microchip Technology Inc.
DS21125D-page 5
24FC65
3.6
Device Addressing
A control byte is the first byte received following the
START from the master device. The control byte
consists of a four bit control code, for the 24FC65 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device to
select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a
one a read operation is selected, when set to a zero a
write operation is selected. The next two bytes received
define the address of the first data byte (Figure 4-1).
Because only A12..A0 are used, the upper three
address bits must be zeros. The most significant bit of
the most significant byte is transferred first. Following
the START, the 24FC65 monitors the SDA bus checking
the device type identifier being transmitted. Upon
receiving a 1010 code and appropriate device select
bits, the slave device (24FC65) outputs an acknowledge
signal on the SDA line. Depending upon the state of the
R/W bit, the 24FC65 will select a read or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
SLAVE ADDRESS
X = Don't care
1
0
1
0
A2
A1
A0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the START from the master, the control code
(four bits), the device select (three bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver (24FC65) that a byte with a word address will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmitted
by the master is the high-order byte of the word address
and will be written into the address pointer of the
24FC65. The next byte is the least significant address
byte. After receiving another acknowledge signal from
the 24FC65 the master device will transmit the data
word to be written into the addressed memory location.
The 24FC65 acknowledges again and the master
generates a STOP. This initiates the internal write cycle,
and during this time the 24FC65 will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24FC65 in the same way as
in a byte write. But instead of generating a STOP the
master transmits up to eight pages of eight data bytes
each (64 bytes total) which are temporarily stored in the
on-chip page cache of the 24FC65. They will be written
from the cache into the EEPROM array after the master
has transmitted a STOP. After the receipt of each word,
the six lower order address pointer bits are internally
incremented by one. The higher order seven bits of the
word address remain constant. If the master should
transmit more than eight bytes prior to generating the
STOP (writing across a page boundary), the address
counter (lower three bits) will roll over and the pointer will
be incremented to point to the next line in the cache. This
can continue to occur up to eight times or until the cache
is full, at which time a STOP should be generated by the
master. If a STOP is not received, the cache pointer will
roll over to the first line (byte 0) of the cache, and any
further data received will overwrite previously captured
data. The STOP can be sent at any time during the
transfer. As with the byte write operation, once the
STOP is received an internal write cycle will begin. The
64 byte cache will continue to capture data until a STOP
occurs or the operation is aborted (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS (1)
A
C
K
S
T
A
R
T
WORD
ADDRESS (0)
A
C
K
A
C
K
0
S
T
O
P
A
C
K
0 0
DATA
S
P
24FC65
DS21125D-page 6
1998 Microchip Technology Inc.
FIGURE 4-2:
PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 7-1)
FIGURE 4-3:
CURRENT ADDRESS READ
FIGURE 4-4:
RANDOM READ
FIGURE 4-5:
SEQUENTIAL READ
BUS
MASTER
SDA LINE
BUS
CONTROL
BYTE
WORD
ADDRESS (1)
S
T
O
P
S
T
A
R
T
A
C
K
0
A
C
K
A
C
K
ACTIVITY:
ACTIVITY:
A
C
K
A
C
K
DATA n
DATA n+7
0 0
WORD
ADDRESS (0)
S
P
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
BYTE
DATA n
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S
P
BUS
MASTER
SDA LINE
BUS
CONTROL
BYTE
WORD
ADDRESS (1)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
ACTIVITY:
ACTIVITY:
A
C
K
N
O
DATA n
0 0 0
WORD
ADDRESS (0)
S
T
A
R
T
CONTROL
BYTE
A
C
K
P
S
S
A
C
K
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
DATA n
DATA n+1
DATA n+2
DATA n+X
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P
P
1998 Microchip Technology Inc.
DS21125D-page 7
24FC65
5.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
5.1
Current Address Read
The 24FC65 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n (n is any legal address), the next current
address read operation would access data from
address n + 1. Upon receipt of the slave address with
R/W bit set to one, the 24FC65 issues an acknowledge
and transmits the eight bit data word. The master will
not acknowledge the transfer but does generate a
STOP and the 24FC65 discontinues transmission
(Figure 4-3).
5.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24FC65 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
START following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24FC65 will
then issue an acknowledge and transmit the eight bit
data word. The master will not acknowledge the
transfer but does generate a STOP which causes the
24FC65 to discontinue transmission (Figure 4-4).
5.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24FC65 transmits
the first data byte, the master issues an acknowledge
as opposed to the STOP used in a random read. This
acknowledge directs the 24FC65 to transmit the next
sequentially addressed 8 bit word (Figure
4-5).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will
generate a STOP.
To provide sequential reads the 24FC65 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
5.4
Contiguous Addressing Across
Multiple Devices
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to
512K-bits by adding up to eight 24FC65's on the same
bus. In this case, software can use A0 of the control
byte as address bit A13, A1 as address bit A14, and A2
as address bit A15.
5.5
Noise Protection
The SCL and SDA inputs incorporate Schmitt triggers
which suppress noise spikes to assure proper device
operation even on a noisy bus.
5.6
High Endurance Block
The location of the high-endurance block within the
memory map is programmed by setting the leading bit
7 (S/HE) of the configuration byte to 0. The upper bits
of the address loaded in this command will determine
which 4K block within the memory map will be set to
high endurance (Figure 8-1). This block will be capable
of 10,000,000 erase/write cycles guaranteed.
5.7
Security Options
The 24FC65 has a sophisticated mechanism for
write-protecting portions of the array. This write protect
function is programmable and allows the user to protect
0-15 contiguous 4K blocks. The user sets the security
option by sending to the device the starting block num-
ber for the protected region and the number of blocks
to be protected. All parts will come from the factory in
the default configuration with the starting block number
set to 15 and the number of protected blocks set to
zero. THE SECURITY OPTION CAN BE SET ONLY
ONCE.
To invoke the security option, a write command is sent
to the device with the leading bit (bit7) of the first
address byte set to a 1 (Figure 8-1). Bits 1-4 of the first
address byte define the starting block number for the
protected region. For example, if the starting block
number is to be set to 5, the first address byte would be
1XX0101X. Bits 0, 5 and 6 of the first address byte are
disregarded by the device and can be either high or
low. The device will acknowledge after the first address
byte. A byte of don't care bits is then sent by the master,
with the device acknowledging afterwards. The third
byte sent to the device has bit7 (S/HE) set high and bit6
(R) set low. Bits 4 and 5 are don't cares and bits 0-3
define the number of blocks to be write protected. For
example, if three blocks are to be protected, the third
Note:
The High Endurance Block cannot be
changed after the security option has been
set. If the H.E. block is not programmed by
the user, the default location is the highest
block of memory.
24FC65
DS21125D-page 8
1998 Microchip Technology Inc.
byte would be 10XX0011. After the third byte is sent to
the device, it will acknowledge and a STOP bit is then
sent by the master to complete the command.
During a normal write sequence, if an attempt is made
to write to a protected address, no data will be written
and the device will not report an error or abort the
command. If a write command is attempted across a
secure boundary, unprotected addresses will be written
and protected addresses will not.
5.8
Security Configuration Read
The status of the secure portion of memory can be read
by using the same technique as programming this
option except the READ bit (bit 6) of the configuration
byte is set to a one. After the configuration byte is sent,
the device will acknowledge and then send two bytes of
data to the master just as in a normal read sequence.
The master must acknowledge the first byte and not
acknowledge the second, and then send a stop bit to
end the sequence. The upper four bits of both of these
bytes will always be read as '1's. The lower four bits of
the first byte contains the starting secure block. The
lower four bits of the second byte contains the number
of secure blocks. The default starting secure block is
fifteen and the default number of secure blocks is zero
(Figure 8-1).
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the STOP for a write command has
been issued from the master, the device initiates the
internally timed write cycle. ACK polling can be initiated
immediately. This involves the master sending a START
followed by the control byte for a write command (R/W
= 0). If the device is still busy with the write cycle, then
no ACK will be returned. If the cycle is complete, then
the device will return the ACK and the master can then
proceed with the next read or write command. See
Figure 6-1 for flow diagram.
FIGURE 6-1:
ACKNOWLEDGE POLLING
FLOW
Did Device
Acknowledge
(ACK = 0)?
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
1998 Microchip Technology Inc.
DS21125D-page 9
24FC65
7.0
PAGE CACHE AND ARRAY
MAPPING
The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer.
The cache allows the loading of up to 64 bytes of data
before the write cycle is actually begun, effectively
providing a 64-byte burst write at the maximum bus
rate. Whenever a write command is initiated, the cache
starts loading and will continue to load until a stop bit is
received to start the internal write cycle. The total
length of the write cycle will depend on how many
pages are loaded into the cache before the stop bit is
given. Maximum cycle time for each page is 5 ms. Even
if a page is only partially loaded, it will still require the
same cycle time as a full page. If more than 64 bytes of
data are loaded before the stop bit is given, the address
pointer will wrap around' to the beginning of cache
page 0 and existing bytes in the cache will be
overwritten. The device will not respond to any
commands while the write cycle is in progress.
7.1
Cache Write Starting at a Page
Boundary
If a write command begins at a page boundary
(address bits A2, A1 and A0 are zero), then all data
loaded into the cache will be written to the array in
sequential addresses. This includes writing across a
4K block boundary. In the example shown below,
(Figure 7-1) a write command is initiated starting at
byte 0 of page 3 with a fully loaded cache (64 bytes).
The first byte in the cache is written to byte 0 of page 3
(of the array), with the remaining pages in the cache
written to sequential pages in the array. A write cycle is
executed after each page is written. Since the write
begins at page 3 and 8 pages are loaded into the
cache, the last 3 pages of the cache are written to the
next row in the array.
7.2
Cache Write Starting at a Non-Page
Boundary
When a write command is initiated that does not begin
at a page boundary (i.e., address bits A2, A1 and A0
are not all zero), it is important to note how the data is
loaded into the cache, and how the data in the cache is
written to the array. When a write command begins, the
first byte loaded into the cache is always loaded into
page 0. The byte within page 0 of the cache where the
load begins is determined by the three least significant
address bits (A2, A1, A0) that were sent as part of the
write command. If the write command does not start at
byte 0 of a page and the cache is fully loaded, then the
last byte(s) loaded into the cache will roll around to
page 0 of the cache and fill the remaining empty bytes.
If more than 64 bytes of data are loaded into the cache,
data already loaded will be overwritten. In the example
shown in Figure 7-2, a write command has been
initiated starting at byte 2 of page 3 in the array with a
fully loaded cache of 64 bytes. Since the cache started
loading at byte 2, the last two bytes loaded into the
cache will 'roll over' and be loaded into the first two
bytes of page 0 (of the cache). When the stop bit is
sent, page 0 of the cache is written to page 3 of the
array. The remaining pages in the cache are then
loaded sequentially to the array. A write cycle is
executed after each page is written. If a partially loaded
page in the cache remains when the STOP bit is sent,
only the bytes that have been loaded will be written to
the array.
7.3
Power Management
The design incorporates a power standby mode when
not in use and automatically powers off after the normal
termination of any operation when a stop bit is received
and all internal functions are complete. This includes
any error conditions, i.e. not receiving an acknowledge
or STOP per the two-wire bus specification. The device
also incorporates V
DD
monitor circuitry to prevent inad-
vertent writes (data corruption) during low-voltage con-
ditions. The V
DD
monitor circuitry is powered off when
the device is in standby mode in order to further reduce
power consumption.
24FC65
DS21125D-page 10
1998 Microchip Technology Inc.
FIGURE 7-1:
CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
FIGURE 7-2:
CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
1
Write command initiated at byte 0 of page 3 in the array;
First data byte is loaded into the cache byte 0.
2 64 bytes of data are loaded into cache.
cache page 0
cache
byte 0
cache
byte 1
cache
byte 7
cache page 1
bytes 8-15
cache page 2
bytes 16-23
cache page 7
bytes 56-63
4
Remaining pages in cache are written
to sequential pages in array.
page 0 page 1 page 2 byte 0 byte 1
byte 7 page 4
page 0 page 1 page 2
page 3
page 4
page 7
page 7
array row n
array row n + 1
3
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
5 Last page in cache written to page 2 in next row.
1
Write command initiated; 64 bytes of data
loaded into cache starting at byte 2 of page 0.
cache
byte 0
cache
byte 1
cache
byte 7
cache page 1
bytes 8-15
cache page 2
bytes 16-23
cache page 7
bytes 56-63
page 0 page 1 page 2 byte 0 byte 1
page 4
page 0 page 1 page 2
page 3
page 4
page 7
page 7
4
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
6 Last 3 pages in cache written to next row in array.
cache
byte 2
2
Last 2 bytes `roll ever'
to beginning.
3
5
Remaining bytes in cache
are written sequentially to
array.
Last 2 bytes
loaded into
page 0 of cache.
byte 2 byte 3 byte 4
byte 7
array row n
array row n+1
1998 Microchip Technology Inc.
DS21125D-page 11
24FC65
8.0
PIN DESCRIPTIONS
8.1
A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24FC65 for multiple
device operation and conform to the two-wire bus
standard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-2 and Figure 8-1).
8.2
SDA Serial Address/Data
Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 2 K
,
must consider total bus
capacitance and maximum rise/fall times).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOPs.
8.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
FIGURE 8-1:
CONTROL SEQUENCE BIT ASSIGNMENTS
R X X
B
3
B
2
B
1
B
0
S 0 0
A
12
A
11
A
10
A
9
A
8
CONTROL
BYTE
ADDRESS
BYTE 0
1 0 1 0
A
2
A
1
A
0
R
W
A
7
A
0
ADDRESS
BYTE 1
CONFIGURATION
BYTE
Slave
Address
Device
Select
Bits
Block
Count
S/HE
Acknowledges from Device
S
S
A
Data from Device
1 0 1 0
A
2
A
1
A
0 0 C
K
A
C
K
A
C
K
A
C
K
1 X X X X X X X
X X X X X X X X
1 1 X X X X X X
1 1 1 1 B
3
B
2
B
1
B
0
A
C
K
1 1 1 1 N
3
N
2
N
1
N
0
Data from Device
S/HE
Starting Block
Number
Number of
Blocks to
Protect
No
ACK
t
o
p
Acknowledge
from Master
t
a
r
t
Security Read
R
Acknowledges from Device
S
S
A
1 0 1 0
A
2
A
1
A
0 0 C
K
A
C
K
A
C
K
A
C
K
1 X X
X
X X X X X X X X
1 0 X X N
3
N
2
N
1
N
0
S/HE
t
o
p
t
a
r
t
Security Write
B
3
B
2
B
1
B
0
R
Starting Block
Number
Number of
Blocks to
Protect
Acknowledges from Device
S
S
A
Data from Device
1 0 1 0
A
2
A
1
A
0 0 C
K
A
C
K
A
C
K
A
C
K
1 X X X X X X X
X X X X X X X X
0 1 X X X X X X
1 1 1 1 B
3
B
2
B
1
B
0
A
C
K
High Endurance
Block Number
No
ACK
t
o
p
t
a
r
t
High Endurance Block Read
R
S/HE
Acknowledges from Device
S
S
A
1 0 1 0
A
2
A
1
A
0 0 C
K
A
C
K
A
C
K
A
C
K
1 X X
X
X X X X X X X X
0 0 X X 0 0 0 0
B
3
B
2
B
1
B
0
S/HE
t
o
p
t
a
r
t
High Endurance Block Write
R
High Endurance
Block Number
24FC65
DS21125D-page 12
1998 Microchip Technology Inc.
NOTES:
1998 Microchip Technology Inc.
DS21125D-page 13
24FC65
NOTES:
24FC65
DS21125D-page 14
1998 Microchip Technology Inc.
NOTES:
24FC65
24FC65 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
Your local Microchip sales office
2.
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3.
The Microchip Worldwide Web Site (www.microchip.com)
Package:
P = Plastic DIP (300 mil Body)
SM = Plastic SOIC (207 mil Body, EIAJ standard)
Temperature
Blank = 0
C to +70
C
Range:
I
= -40
C to +85
C
Device:
24FC65
64K, 1MHz I
2
C Serial EEPROM
24FC65T
64K, 1MHz I
2
C Serial EEPROM (Tape & Reel)
24FC65
/P
1998 Microchip Technology Inc.
DS21125D-page 15
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
All rights reserved. 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
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AMERICAS
(continued)
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(continued)
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11/15/99
W
ORLDWIDE
S
ALES
AND
S
ERVICE
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company's quality system processes and
procedures are QS-9000 compliant for its
PICmicro
8-bit MCUs, K
EE
L
OQ
code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip's quality
system for the design and manufacture of
development systems is ISO 9001 certified.
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