1999 Microchip Technology Inc.

DS21140D-page 1

FEATURES

· Single supply with operation down to 2.5V
· Completely implements DDC1

/DDC2

interface

for monitor identification

· Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

· Low power CMOS technology
· 2 mA active current typical
· 20

A standby current typical at 5.5V

· Dual 2-wire serial interface bus
· Hardware write-protect for both ports
· Self-timed write cycle (including auto-erase)
· Page-write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

· 100 kHz (2.5V) and 400 kHz (5V) compatibility
· 1,000,000 erase/write cycles guaranteed
· Data retention > 40 years
· 8-pin PDIP package
· Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24LC41 is a dual-port
128 x 8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applica-
tions requiring storage and serial transmission of con-
figuration and control information. Three modes of
operation have been implemented:

· Transmit-Only Mode for the DDC Monitor Port

· Bi-directional Mode for the DDC Monitor Port

· Bi-directional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Upon power-up, the DDC Monitor Port will be in the
Transmit-Only Mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK/DWP pin. A valid high to low transition on the
DSCL pin will cause the device to enter the bi-direc-
tional Mode, with byte-selectable read/write capability
of the memory array. The 4K-bit microcontroller port is
completely independent of the DDC port, therefore, it
can be accessed continuously by a microcontroller
without interrupting DDC transmission activity. The
24LC41 is available in a standard 8-pin PDIP package
in both commercial and industrial temperature ranges.

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

PACKAGE TYPE

BLOCK DIAGRAM

24LC

DSCL

VCLK/DWP

MSDA

DSDA

MWP

MSCL

PDIP

EDID Table

1K Bit

4K Bit

Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

C M

r
P

r
t

i
cro

t
r
o

l
l
e

r Acc

ss P

r
t

24LC41

1K/4K 2.5V Dual Mode, Dual Port I

Serial EEPROM

DDC is a trademark of the Video Electronics Standards Association.

C is a trademark of Philips Corporation.

24LC41

DS21140D-page 2

1999 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins

..................................................

4 kV

*Notice: Stresses above those listed under "Maximum ratings"
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

DSCL

Serial Clock for DDC Bi-directional
Mode (DDC2)

DSDA

Serial Address and Data I/O
(DDC Bus)

VCLK/DWP

Serial Clock for DDC transmit-only
mode (DDC1)/Write Protect

MSCL

Serial clock for 4K-bit MCU port

MSDA

Serial Address and Data I/O for
4K-bit MCU port

MWP

Hardware write-protect for 4K-bit
MCU port

Ground

+2.5V to +5.5V power supply

TABLE 1-2:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C):

Tamb = 0°C to +70°C

Industrial (I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High level input voltage
Low level input voltage

.7 V

.3 V

V
V

Input levels on VCLK/DWP pin:

High level input voltage
Low level input voltage

2.0

.2 V

V
V

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt trigger inputs

HYS

.05 V

Note 1

Low level output voltage

OL1

= 3 mA, V

= 2.5V (Note)

Low level output voltage

OL2

= 6 mA, V

= 2.5V

Input leakage current

-10

=.1V to V

Output leakage current

-10

OUT

=.1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

= 5.0V (Note),

Tamb = 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

--
--

3
1

mA
mA

= 5.5V, DSCL or MSCL = 400

kHz

Standby current

CCS

--
--

200

= 3.0V, DSDA or MSDA =

DSCL or MSCL = V

= 5.5V, DSDA or MSDA =

DSCL or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

1999 Microchip Technology Inc.

DS21140D-page 3

24LC41

TABLE 1-3:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS
PORTS)

DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and
MSCL)

CLK

100

400

kHz

Clock high time (DSCL and
MSCL)

HIGH

4000

600

Clock low time (DSCL and
MSCL)

LOW

4700

1300

DSCL, DSDA, MSCL &
MSDA rise time

1000

300

(Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

300

(Note 1)

START condition hold time

STA

4000

600

After this period the first
clock pulse is generated

START condition setup time T

STA

4700

600

Only relevant for repeated
START condition

Data input hold time

DAT

(Note 2)

Data input setup time

DAT

250

100

STOP condition setup time

STO

4000

600

Output valid from clock

3500

900

(Note 2)

Bus free time

BUF

4700

1300

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

250

20 + .1

250

(Note 1), C

100 pF

Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)

(Note 3)

Write cycle time

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

VAA

2000

1000

VCLK/DWP high time

VHIGH

4000

600

VCLK/DWP low time

VLOW

4700

1300

Mode transition time

VHZ

500

Transmit-Only power up
time

VPU

Endurance

cycles

25°C, Vcc = 5.0V, Block
Mode (Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or STOP
conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our website.

24LC41

DS21140D-page 4

1999 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

The DDC Monitor Port operates in two modes, the
Transmit-Only Mode and the bi-directional Mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a com-
mon data line (DSDA). The device enters the Transmit-
Only Mode upon power-up. In this mode, the device
transmits data bits on the DSDA pin in response to a
clock signal on the VCLK/DWP pin. The device will
remain in this mode until a valid high to low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the bi-
directional Mode. The only way to switch the device
back to the Transmit-Only Mode is to remove power
from the device.

2.1.1

TRANSMIT-ONLY MODE

The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional 2-wire protocol for
transmission of the contents of the memory array. This
device requires that it be initialized prior to valid data
being sent in the Transmit-Only Mode (Section 2.1.2).

In this mode, data is transmitted on the DSDA pin in 8-
bit bytes, each followed by a ninth, null bit (Figure 2-1).
The clock source for the Transmit-Only Mode is pro-
vided on the VCLK/DWP pin, and a data bit is output on
the rising edge on this pin. The eight bits in each byte
are transmitted by most significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the output will wrap around to the first location and con-
tinue. The bi-directional Mode Clock (DSCL) pin must
be held high for the device to remain in the Transmit-
Only Mode.

2.1.2

INITIALIZATION PROCEDURE

After V

has stabilized, the device will be in the Trans-

mit-Only Mode. Nine clock cycles on the VCLK/DWP
pin must be given to the device for it to perform internal
sychronization. During this period, the DSDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit of a byte.
The device will power up at an indeterminate byte
address (Figure 2-2).

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High Impedance for 9 clock cycles

VPU

SCL

SDA

VCLK/DWP

Vcc

1999 Microchip Technology Inc.

DS21140D-page 5

24LC41

2.1.3

BI-DIRECTIONAL MODE

The DDC Monitor Port can be switched into the bi-
directional Mode (Figure 2-3) by applying a valid high to
low transition on the bi-directional Mode Clock (DSCL).
When the device has been switched into the bi-direc-
tional Mode, the VCLK/DWP input is disregarded, with
the exception that a logic high level is required to
enable write capability. This mode supports a 2-wire bi-
directional data transmission protocol. In this protocol,
a device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the bi-direc-
tional Mode Clock (DSCL), controls access to the bus
and generates the START and STOP conditions, while
the DDC Monitor Port acts as the slave. Both master
and slave can operate as transmitter or receiver, but the
master device determines which mode is activated.

2.2

Microcontroller Access Port

The Microcontroller Access Port supports a bi-direc-
tional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as trans-
mitter, and a device receiving data as receiver. The bus
has to be controlled by a master device which gener-
ates the serial clock (MSCL), controls the bus access,
and generates the START and STOP conditions, while
the Microcontroller Access Port works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bi-Directional Mode

VHZ

Transmit Only Mode

24LC41

DS21140D-page 6

1999 Microchip Technology Inc.

3.0

BI-DIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the bi-directional bus are identical
for both the DDC Monitor Port (in bi-directional Mode)
and the Microcontroller Access Port The following bus
protocol has been defined:

· Data transfer may be initiated only when the bus

is not busy.

· During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is HIGH determines a
START condition. All commands must be preceded by
a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is HIGH determines a
STOP condition. All operations must be ended with a
STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur, it will replace data in a first in
first out fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit
.

The device that acknowledges has to pull down the
DSDA or MSDA line during the acknowledge clock
pulse in such a way that the DSDA or MSDA line is sta-
ble LOW during the HIGH period of the acknowledge
related clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an
end of data to the slave by not generating an acknowl-
edge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP
condition.

3.6

Device Addressing

A control byte is the first byte received following the
start condition from the master device. The first part of
the control byte consists of a 4-bit control code. This
control code is set as 1010 for both read and write oper-
ations and is the same for both the DDC Monitor Port
and Microcontroller Access Port. The next three bits of
the control byte are block select bits (B1, B2, and B0).
All three of these bits are don't care bits for the DDC
Monitor Port. The B2 and B1 bits are don't care bits for
the Microcontroller Access Port, and the B0 bit is used
by the Microcontroller Access Port to select which of
the two 256 word blocks of memory are to be accessed
(Figure 3-4). The B0 bit is effectively the most signifi-
cant bit of the word address. The last bit of the control
byte defines the operation to be performed. When set
to one, a read operation is selected; when set to zero,
a write operation is selected. Following the start condi-
tion, the device monitors the DSDA or MSDA bus
checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an acknowl-
edge signal on the SDA line. Depending on the state of
the R/W bit, the device will select a read or a write oper-
ation. The DDC Monitor Port and Microcontroller
Access Port can be accessed simultaneously because
they are completely independent of one another.

Note:

The microcontroller access port and the
DDC Monitor Port (in bi-directional Mode)
will not generate any acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Chip Select

R/W

Read

1010

XXB0

Write

1010

XXB0

1999 Microchip Technology Inc.

DS21140D-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MSCL

MSDA

MSCL

DSDA

STA

START

STOP

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

X = Don't care. B0 is don't care for DDC Monitor Port, but is
used by the Microcontroller Access Port to select which of
the two 256 word blocks of memory are to be accessed.

R/W

READ/WRITE

START

SLAVE ADDRESS

24LC41

DS21140D-page 8

1999 Microchip Technology Inc.

4.0

WRITE OPERATION

Write operations are identical for the DDC Monitor Port
(when in bi-directional Mode) and the Microcontroller
Access Port, with the exception of the VCLK/DWP and
MWP pins noted in the next sections. Data can be writ-
ten using either a byte write or page write command.
Write commands for the DDC Monitor Port and the
Microcontroller Access Port are completely indepen-
dent of one another.

4.1

Byte Write

Following the start signal from the master, the slave
address (4-bits), the chip select bits (3-bits) and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the port. After receiving
another acknowledge signal from the port, the master
device will transmit the data word to be written into the
addressed memory location. The port acknowledges
again and the master generates a stop condition. This
initiates the internal write cycle, and during this time,
the port will not generate acknowledge signals
(Figure 4-1).

For the DDC Monitor Port it is required that VCLK/DWP
be held at a logic high level in order to program the
device. This applies to byte write and page write oper-
ation. Note that VCLK/DWP can go low while the device
is in its self-timed program operation and not affect pro-
gramming.

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

4.2

Page Write

The write control byte, word address, and the first data
byte are transmitted to the port in the same way as in a
byte write. But, instead of generating a stop condition,
the master transmits up to eight data bytes to the DDC
Monitor Port or 16 bytes to the Microcontroller Access
Port, which are temporarily stored in the on-chip page
buffer and will be written into the memory after the mas-
ter has transmitted a stop condition. After the receipt of
each word, the three lower order address pointer bits
are internally incremented by one. The higher order 5-
bits of the word address remains constant. If the master
should transmit more than eight words to the DDC
Monitor Port or 16 words to the Microcontroller Access
Port prior to generating the stop condition, the address
counter will roll over and the previously received data
will be overwritten. As with the byte write operation,
once the stop condition is received an internal write
cycle will begin (Figure 4-2).

For the DDC Monitor Port, it is required thatVCLK/DWP
be held at a logic high level in order to program the
device. This applies to byte write and page write oper-
ation. Note that VCLK/DWP can go low while the device
is in its self-timed program operation and not affect pro-
gramming.

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

Note:

Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or `page size') and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.

1999 Microchip Technology Inc.

DS21140D-page 9

24LC41

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
A
R
T

S
T
O
P

BUS ACTIVITY
MASTER

SDA or

BUS ACTIVITY

A
C
K

CONTROL

BYTE

WORD

ADDRESS

DATA

MSDA LINE

VCLK

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS

DATA n

DATA n + 15

S
T
O
P

A
C
K

DATA n + 1

VCLK/DWP

5.0

ACKNOWLEDGE POLLING

Acknowledge polling can be done for both the DDC
Monitor Port (when in bi-directional Mode) and the
Microcontroller Access Port.

Since the port will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize but
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W=0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

24LC41

DS21140D-page 10

1999 Microchip Technology Inc.

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

When using the DDC Monitor Port in the bi-directional
Mode, the VCLK/DWP pin operates as the write protect
control pin. Setting VCLK/DWP high allows normal
write operations, while setting VCLK/DWP low prevents
writing to any location in the array. Connecting the
VCLK/DWP pin to V

would allow the DDC Monitor

Port to operate as a serial ROM, although this configu-
ration would prevent using the device in the Transmit-
Only Mode.

6.2

Microcontroller Access Port

The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V

Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.

7.0

READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read. These operations are identical for
both the DDC Monitor Port (in bi-directional Mode) and
the Microcontroller Access Port and are completely
independent of one another.

7.1

Current Address Read

The port contains an address counter that maintains
the address of the last word accessed, internally incre-
mented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the port issues an acknowledge
and transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a stop
condition and the port discontinues transmission
(Figure 7-1).

7.2

Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
port as part of a write operation. After the word address
is sent, the master generates a start condition following
the acknowledge. This terminates the write operation,
but not before the internal address pointer is set. The
master then issues the control byte again, but with
the R/W bit set to a one. The port then issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does gen-
erate a stop condition and the port discontinues trans-
mission (Figure 7-2).

7.3

Sequential Read

Sequential reads are initiated in the same way as a ran-
dom read except that after the port transmits the first
data byte, and the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the port to transmit the next sequentially
addressed 8-bit word (Figure 7-3).

To provide sequential reads, the port contains an inter-
nal address pointer, which is incremented by one at the
completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.

7.4

Noise Protection

Both the DDC Monitor Port and Microcontroller Access
Port employ a V

threshold detector circuit which dis-

ables the internal erase/write logic, if the V

is below

1.5 volts at nominal conditions.

The DSCL, MSCL, DSDA, and MSDA inputs have
Schmitt trigger and filter circuits which suppress noise
spikes to assure proper device operation even on a
noisy bus.

24LC41

DS21140D-page 12

1999 Microchip Technology Inc.

8.0

PIN DESCRIPTIONS

8.1

DSDA

This pin is used to transfer addresses and data into and
out of the DDC Monitor Port, when the device is in the
bi-directional Mode. In the Transmit-Only Mode, which
only allows data to be read from the device, data is also
transferred on the DSDA pin. This pin is an open drain
terminal, therefore the DSDA bus requires a pullup
resistor to V

(typical 10K

for 100 kHz, 2 K

for

400 kHz).

For normal data transfer in the bi-directional Mode,
DSDA is allowed to change only during DSCL or MSDA
low. Changes during DSCL high are reserved for indi-
cating the START and STOP conditions.

8.2

DSCL

This pin is the clock input for the DDC Monitor Port
while in the bi-directional Mode, and is used to synchro-
nize data transfer to and from the device. It is also used
as the signaling input to switch the device from the
Transmit-Only Mode to the bi-directional Mode. It must
remain high for the chip to continue operation in the
Transmit-Only Mode.

8.3

VCLK/DWP

This pin is the clock input for the DDC Monitor Port
while in the Transmit-Only Mode. In the Transmit-Only
Mode, each bit is clocked out on the rising edge of this
signal. In the bi-directional Mode, a high logic level is
required on this pin to enable write capability.

8.4

MSCL

This pin is the clock input for the Microcontroller Access
Port, and is used to synchronize data transfer to and
from the device.

8.5

MSDA

This pin is used to transfer addresses and data into and
out of the Microcontroller Access Port. This pin is an
open drain terminal, therefore the MSDA bus requires
a pullup resistor to V

(typical 10K

for 100 kHz, 2K

for 400 kHz).

MSDA is allowed to change only during MSCL low.
Changes during MSCL high are reserved for indicating
the START and STOP conditions.

8.6

MWP

This pin is used to write protect the 4K memory array
for the Microcontroller Access Port.

This pin must be connected to either V

or V

If tied to Vss, normal memory operation is enabled
(read/write the entire memory).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

24LC41

1999 Microchip Technology Inc.

DS21140D-page 15

24LC41 Product Identification System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil), 8-lead

Temperature

Blank = 0

C to +70

Range:

= -40

C to +85

Device:

24LC41

Dual Mode, Dual Port I

C Serial EEPROM

24LC41

2002 Microchip Technology Inc.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip's products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,
K

, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company's quality system processes and
procedures are QS-9000 compliant for its
PICmicro

8-bit MCUs, K

code hopping

devices, Serial EEPROMs and microperipheral
products. In addition, Microchip's quality
system for the design and manufacture of
development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro

MCUs.

The PICmicro family meets the specifications contained in the Microchip Data Sheet.

Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable".

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

2002 Microchip Technology Inc.

AMERICAS

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01/18/02

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Document Outline

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Document Outline

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