1999 Microchip Technology Inc.
Preliminary
DS21298B-page 1
MCP3204/3208
FEATURES
12-bit resolution
1 LSB max DNL
1 LSB max INL (MCP3204/3208-B)
2 LSB max INL (MCP3204/3208-C)
4 (MCP3204) or 8 (MCP3208) input channels
Analog inputs programmable as single-ended or
pseudo differential pairs
On-chip sample and hold
SPI
serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at V
DD
= 5V
50ksps max. sampling rate at V
DD
= 2.7V
Low power CMOS technology
- 500 nA typical standby current, 2A max.
- 400 A max. active current at 5V
Industrial temp range: -40C to +85C
Available in PDIP, SOIC and TSSOP packages
APPLICATIONS
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
DESCRIPTION
The Microchip Technology Inc. MCP3204/3208
devices are successive approximation 12-bit Ana-
log-to-Digital (A/D) Converters with on-board sample
and hold circuitry. The MCP3204 is programmable to
provide two pseudo-differential input pairs or four sin-
gle-ended inputs. The MCP3208 is programmable to
provide four pseudo-differential input pairs or eight sin-
gle-ended inputs. Differential Nonlinearity (DNL) is
specified at 1 LSB, and Integral Nonlinearity (INL) is
offered in 1 LSB (MCP3204/3208-B) and 2 LSB
(MCP3204/3208-C) versions. Communication with the
devices is done using a simple serial interface compat-
ible with the SPI protocol. The devices are capable of
conversion rates of up to 100ksps. The MCP3204/3208
devices operate over a broad voltage range (2.7V -
5.5V). Low current design permits operation with typi-
cal standby and active currents of only 500nA and
320A, respectively. The MCP3204 is offered in 14-pin
PDIP, 150mil SOIC and TSSOP packages, and the
MCP3208 is offered in 16-pin PDIP and SOIC pack-
ages.
PACKAGE TYPES
FUNCTIONAL BLOCK DIAGRAM
V
DD
CLK
D
OUT
MC
P3
204
1
2
3
4
14
13
12
11
10
9
8
5
6
7
V
REF
D
IN
CH0
CH1
CH2
CH3
CS/SHDN
DGND
AGND
NC
V
DD
CLK
D
OUT
MC
P3
208
1
2
3
4
16
15
14
13
12
11
10
9
5
6
7
8
V
REF
D
IN
CS/SHDN
DGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
NC
AGND
PDIP, SOIC, TSSOP
PDIP, SOIC
Comparator
Sample
and
Hold
12-Bit SAR
DAC
Control Logic
CS/SHDN
V
REF
V
SS
V
DD
CLK
D
OUT
Shift
Register
CH0
Channel
Mux
Input
CH1
CH7*
*Note: Channels 5-7 available on MCP3208 Only
D
IN
2.7V 4-Channel/8-Channel 12-Bit A/D Converters
with SPI
Serial Interface
MCP3204/3208
DS21298B-page 2
Preliminary
1999 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
DD
.........................................................................7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
DD
+0.6V
Storage temperature ..........................-65C to +150C
Ambient temp. with power applied......-65C to +125C
Soldering temperature of leads (10 seconds) .. +300C
ESD protection on all pins ................................... > 4kV
*Notice: Stresses above those listed under "Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
PIN FUNCTION TABLE
NAME
FUNCTION
V
DD
DGND
AGND
CH0-CH7
CLK
D
IN
D
OUT
CS/SHDN
V
REF
+2.7V to 5.5V Power Supply
Digital Ground
Analog Ground
Analog Inputs
Serial Clock
Serial Data In
Serial Data Out
Chip Select/Shutdown Input
Reference Voltage Input
ELECTRICAL CHARACTERISTICS
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40C to +85C, f
SAMPLE
= 100ksps and
f
CLK
= 20*f
SAMPLE
, unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Conversion Rate
Conversion Time
t
CONV
12
clock
cycles
Analog Input Sample Time
t
S
AMPLE
1.5
clock
cycles
Throughput Rate
f
SAMPLE
100
50
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
0.75
1
1
2
LSB
MCP3204/3208-B
MCP3204/3208-C
Differential Nonlinearity
DNL
0.5
1
LSB
No missing codes over
temperature
Offset Error
1.25
3
LSB
Gain Error
1.25
5
LSB
Dynamic Performance
Total Harmonic Distortion
-82
dB
V
IN
= 0.1V to 4.9V@1kHz
Signal to Noise and Distortion
(SINAD)
72
dB
V
IN
= 0.1V to 4.9V@1kHz
Spurious Free Dynamic
Range
86
dB
V
IN
= 0.1V to 4.9V@1kHz
Reference Input
Voltage Range
0.25
V
DD
V
Note 2
Current Drain
100
0.001
150
3
A
A
CS = V
DD
= 5V
Analog Inputs
Input Voltage Range for
CH0-CH7 in Single-Ended
Mode
V
SS
V
REF
V
Input Voltage Range for IN+ In
pseudo-differential Mode
IN-
V
REF
+IN-
Input Voltage Range for IN- In
pseudo-differential Mode
V
SS
-100
V
SS
+100
mV
Leakage Current
0.001
1
A
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 3
MCP3204/3208
Analog Inputs (Continued)
Switch Resistance
1K
See Figure 4-1
Sample Capacitor
20
pF
See Figure 4-1
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
V
IH
0.7 V
DD
V
Low Level Input Voltage
V
IL
0.3 V
DD
V
High Level Output Voltage
V
OH
4.1
V
I
OH
= -1mA, V
DD
= 4.5V
Low Level Output Voltage
V
OL
0.4
V
I
OL
= 1mA, V
DD
= 4.5V
Input Leakage Current
I
LI
-10
10
A
V
IN
= V
SS
or V
DD
Output Leakage Current
I
LO
-10
10
A
V
OUT
= V
SS
or V
DD
Pin Capacitance
(All Inputs/Outputs)
C
IN
, C
OUT
10
pF
V
DD
= 5.0V (Note 1)
T
AMB
= 25C, f = 1 MHz
Timing Parameters
Clock Frequency
f
CLK
2.0
1.0
MHz
MHz
V
DD
= 5V (Note 3)
V
DD
= 2.7V (Note 3)
Clock High Time
t
HI
250
ns
Clock Low Time
t
LO
250
ns
CS Fall To First Rising CLK
Edge
t
SUCS
100
ns
Data Input Setup Time
t
SU
50
ns
Data Input Hold Time
t
HD
50
ns
CLK Fall To Output Data Valid
t
DO
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
t
EN
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
t
DIS
100
ns
See Test Circuits, Figure 1-2
CS Disable Time
t
CSH
500
ns
D
OUT
Rise Time
t
R
100
ns
See Test Circuits, Figure 1-2
(Note 1)
D
OUT
Fall Time
t
F
100
ns
See Test Circuits, Figure 1-2
(Note 1)
Power Requirements
Operating Voltage
V
DD
2.7
5.5
V
Operating Current
I
DD
320
225
400
A
V
DD
= V
REF
= 5V, D
OUT
unloaded
V
DD
= V
REF
= 2.7V, D
OUT
unloaded
Standby Current
I
DDS
0.5
2
A
CS = V
DD
= 5.0V
Note 1: This parameter is guaranteed by characterization and not 100% tested.
Note 2: See graphs that relate linearity performance to V
REF
levels.
Note 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40C to +85C, f
SAMPLE
= 100ksps and
f
CLK
= 20*f
SAMPLE
, unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
MCP3204/3208
DS21298B-page 4
Preliminary
1999 Microchip Technology Inc.
FIGURE 1-1:
Serial Interface Timing.
FIGURE 1-2:
Test Circuits.
CS
CLK
D
IN
MSB IN
t
SU
t
HD
t
SUCS
t
CSH
t
HI
t
LO
D
OUT
t
EN
t
DO
t
R
t
F
LSB
MSB OUT
t
DIS
NULL BIT
90%
10%
*
Waveform 1 is for an output with internal condi-
tions such that the output is high, unless dis-
abled by the output control.
Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.
Test Point
1.4V
D
OUT
Load circuit for t
R
, t
F
,
t
DO
3K
C
L
= 100pF
Test Point
D
OUT
Load circuit for t
DIS
and t
EN
3K
100pF
t
DIS
Waveform 2
t
DIS
Waveform 1
CS
CLK
D
OUT
t
EN
1
2
B11
Voltage Waveforms for t
EN
t
EN
Waveform
V
DD
V
DD
/2
V
SS
3
4
D
OUT
t
R
Voltage Waveforms for t
R
, t
F
CLK
D
OUT
t
DO
Voltage Waveforms for t
DO
t
F
V
OH
V
OL
Voltage Waveforms for t
DIS
D
OUT
D
OUT
CS
V
IH
T
DIS
Waveform 1*
Waveform 2
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 5
MCP3204/3208
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25C
FIGURE 2-1:
Integral Nonlinearity (INL) vs. Sample
Rate.
FIGURE 2-2:
Integral Nonlinearity (INL) vs. V
REF
.
FIGURE 2-3:
Integral Nonlinearity (INL) vs. Code
(Representative Part).
FIGURE 2-4:
Integral Nonlinearity (INL) vs. Sample
Rate (V
DD
= 2.7V).
FIGURE 2-5:
Integral Nonlinearity (INL) vs. V
REF
(V
DD
= 2.7V).
FIGURE 2-6:
Integral Nonlinearity (INL) vs. Code
(Representative Part, V
DD
= 2.7V).
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
25
50
75
100
125
150
Sample Rate (ksps)
I
N
L (LSB)
Positive INL
Negative INL
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
6
V
REF
(V)
IN
L(
LSB)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
IN
L (
L
SB)
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
10
20
30
40
50
60
70
80
Sample Rate (ksps)
I
N
L (LSB)
Positive INL
Negative INL
V
DD
= V
REF
= 2.7V
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
I
N
L(LSB)
Positive INL
Negative INL
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
IN
L (
L
SB)
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
PDF 
ZIP