2003 Microchip Technology Inc.

DS11195C-page 1

MCP41XXX/42XXX

Features

· 256 taps for each potentiometer
· Potentiometer values for 10 k

, 50 k and

100 k

· Single and dual versions
· SPITM serial interface (mode 0,0 and 1,1)
· ±1 LSB max INL & DNL
· Low power CMOS technology
· 1 µA maximum supply current in static operation
· Multiple devices can be daisy-chained together

(MCP42XXX only)

· Shutdown feature open circuits of all resistors for

maximum power savings

· Hardware shutdown pin available on MCP42XXX

only

· Single supply operation (2.7V - 5.5V)
· Industrial temperature range: -40°C to +85°C
· Extended temperature range: -40°C to +125°C

Block Diagram

Description

The MCP41XXX and MCP42XXX devices are 256-
position, digital potentiometers available in 10 k

50 k

and 100 k resistance versions. The

MCP41XXX is a single-channel device and is offered in
an 8-pin PDIP or SOIC package. The MCP42XXX con-
tains two independent channels in a 14-pin PDIP, SOIC
or TSSOP package. The wiper position of the
MCP41XXX/42XXX varies linearly and is controlled via
an industry-standard SPI interface. The devices con-
sume <1 µA during static operation. A software shut-
down feature is provided that disconnects the "A"
terminal from the resistor stack and simultaneously con-
nects the wiper to the "B" terminal. In addition, the dual
MCP42XXX has a SHDN pin that performs the same
function in hardware. During shutdown mode, the con-
tents of the wiper register can be changed and the
potentiometer returns from shutdown to the new value.
The wiper is reset to the mid-scale position (80h) upon
power-up. The RS (reset) pin implements a hardware
reset and also returns the wiper to mid-scale. The
MCP42XXX SPI interface includes both the SI and SO
pins, allowing daisy-chaining of multiple devices. Chan-
nel-to-channel resistance matching on the MCP42XXX
varies by less than 1%. These devices operate from a
single 2.7 - 5.5V supply and are specified over the
extended and industrial temperature ranges.

Package Types

16-Bit

Shift

SCK

RS SHDN

PB1
PA1

PW1

Resistor

Array 1*

Wiper

PB0

PW0

PA0

Resistor

Array 0

Wiper

Control

Logic

*Potentiometer P1 is only available on the dual

MCP42XXX version.

MCP42XXX

1
2
3
4

5
6
7

PDIP/SOIC/TSSOP

PB1

PA1

PW1

SHDN

PW0

PB0

PA0

SCK

1XXX

1
2
3
4

PDIP/SOIC

PB0

PA0

PW0

SCK

Single/Dual Digital Potentiometer with SPI

Interface

MCP41XXX/42XXX

DS11195C-page 2

2003 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS: 10 k

VERSION

Electrical Characteristics: Unless otherwise indicated, V

= +2.7V to 5.5V, T

= -40°C to +85°C (TSSOP devices are only specified at +25°C and

+85°C). Typical specifications represent values for V

= 5V, V

= 0V, V

= 0V, T

= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat Mode
Nominal Resistance

= +25°C (Note 1)

Rheostat Differential Non Linearity

R-DNL

-1

±1/4

LSB

Note 2

Rheostat Integral Non Linearity

R-INL

-1

±1/4

LSB

Note 2

Rheostat Tempco

800

ppm/°C

Wiper Resistance

100

= 5.5V, I

= 1 mA, code 00h

125

= 2.7V, I

= 1 mA, code 00h

Wiper Current

-1

Nominal Resistance Match

R/R

0.2

MCP42010 only, P0 to P1; T

= +25°C

Potentiometer Divider
Resolution

Bits

Monotonicity

Bits

Differential Non-Linearity

DNL

-1

±1/4

LSB

Note 3

Integral Non-Linearity

INL

-1

±1/4

LSB

Note 3

Voltage Divider Tempco

ppm/°C Code 80h

Full Scale Error

WFSE

-2

-0.7

LSB

Code FFh, V

= 5V, see Figure 2-25

WFSE

-2

-0.7

LSB

Code FFh, V

= 3V, see Figure 2-25

Zero Scale Error

WZSE

+0.7

LSB

Code 00h, V

= 5V, see Figure 2-25

WZSE

+0.7

LSB

Code 00h, V

= 3V, see Figure 2-25

Resistor Terminals
Voltage Range

A,B,W

Note 4

Capacitance (C

or C

)

f = 1 MHz, Code = 80h, see Figure 2-30

Capacitance

5.6

f = 1 MHz, Code = 80h, see Figure 2-30

Dynamic Characteristics (All dynamic characteristics use V

= 5V)

Bandwidth -3dB

MHz

= 0V, Measured at Code 80h,

Output Load = 30

Settling Time

µS

= V

= 0V, ±1% Error Band, Transition

from Code 00h to Code 80h, Output Load = 30 pF

Resistor Noise Voltage

NWB

nV/

Hz V

= Open, Code 80h

, f =1 kHz

Crosstalk

-95

= V

, V

= 0V (Note 5)

Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation
Schmitt Trigger High-Level Input Voltage

0.7V

Schmitt Trigger Low-Level Input Voltage

0.3V

Hysteresis of Schmitt Trigger Inputs

HYS

0.05V

Low-Level Output Voltage

0.40

= 2.1 mA, V

= 5V

High-Level Output Voltage

- 0.5

= -400 µA, V

= 5V

Input Leakage Current

-1

µA

CS = V

, V

= V

or V

, includes V

SHDN=0

Pin Capacitance (All inputs/outputs)

, C

OUT

= 5.0V, T

= +25°C, f

= 1 MHz

Power Requirements
Operating Voltage Range

2.7

5.5

Supply Current, Active

DDA

340

500

µA

= 5.5V, CS = V

, f

SCK

= 10 MHz,

SO = Open, Code FFh (Note 6)

Supply Current, Static

DDS

0.01

µA

CS, SHDN, RS = V

= 5.5V, SO = Open (Note 6)

Power Supply Sensitivity

PSS

0.0015

0.0035

%/%

= 4.5V - 5.5V, V

= 4.5V, Code 80h

PSS

0.0015

0.0035

%/%

= 2.7V - 3.3V, V

= 2.7V, Code 80h

Note

= V

, no connection on wiper.

Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I

= 50 µA for

= 3V and I

= 400 µA for V

= 5V for 10 k

version. See Figure 2-26 for test circuit.

INL and DNL are measured at V

with the device configured in the voltage divider or potentiometer mode. V

= V

and V

= 0V. DNL

specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.

Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.

Measured at V

pin where the voltage on the adjacent V

pin is swinging full-scale.

Supply current is independent of current through the potentiometers.

2003 Microchip Technology Inc.

DS11195C-page 3

MCP41XXX/42XXX

DC CHARACTERISTICS: 50 k

VERSION

Electrical Characteristics: Unless otherwise indicated, V

= +2.7V to 5.5V, T

= -40°C to +85°C (TSSOP devices are only specified at +25°C and

+85°C). Typical specifications represent values for V

= 5V, V

= 0V, V

= 0V, T

= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat Mode
Nominal Resistance

= +25°C (Note 1)

Rheostat Differential Non-Linearity

R-DNL

-1

±1/4

LSB

Note 2

Rheostat Integral Non-Linearity

R-INL

-1

±1/4

LSB

Note 2

Rheostat Tempco

800

ppm/°C

Wiper Resistance

125

175

= 5.5V, I

= 1 mA, code 00h

175

250

= 2.7V, I

= 1 mA, code 00h

Wiper Current

-1

Nominal Resistance Match

R/R

0.2

MCP42050 only, P0 to P1;T

= +25°C

Potentiometer Divider
Resolution

Bits

Monotonicity

Bits

Differential Non-Linearity

DNL

-1

±1/4

LSB

Note 3

Integral Non-Linearity

INL

-1

±1/4

LSB

Note 3

Voltage Divider Tempco

ppm/°C Code 80h

Full-Scale Error

WFSE

-1

-0.25

LSB

Code FFh, V

= 5V, see Figure 2-25

WFSE

-1

-0.35

LSB

Code FFh, V

= 3V, see Figure 2-25

Zero-Scale Error

WZSE

+0.25

LSB

Code 00h, V

= 5V, see Figure 2-25

WZSE

+0.35

LSB

Code 00h, V

= 3V, see Figure 2-25

Resistor Terminals
Voltage Range

A,B,W

Note 4

Capacitance (C

or C

)

f =1 MHz, Code = 80h, see Figure 2-30

Capacitance

5.6

f =1 MHz, Code = 80h, see Figure 2-30

Dynamic Characteristics (All dynamic characteristics use V

= 5V)

Bandwidth -3dB

280

MHz

= 0V, Measured at Code 80h,

Output Load = 30

Settling Time

µS

= V

= 0V, ±1% Error Band, Transition

from Code 00h to Code 80h, Output Load = 30 pF

Resistor Noise Voltage

NWB

nV/

Hz V

= Open, Code 80h

, f =1 kHz

Crosstalk

-95

= V

, V

= 0V (Note 5)

Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage

0.7V

Schmitt Trigger Low-Level Input Voltage

0.3V

Hysteresis of Schmitt Trigger Inputs

HYS

0.05V

Low-Level Output Voltage

0.40

= 2.1 mA, V

= 5V

High-Level Output Voltage

- 0.5

= -400 µA, V

= 5V

Input Leakage Current

-1

µA

CS = V

, V

= V

or V

, includes V

SHDN=0

Pin Capacitance (All inputs/outputs)

, C

OUT

= 5.0V, T

= +25°C, f

= 1 MHz

Power Requirements
Operating Voltage Range

2.7

5.5

Supply Current, Active

DDA

340

500

µA

= 5.5V, CS = V

, f

SCK

= 10 MHz,

SO = Open, Code FFh (Note 6)

Supply Current, Static

DDS

0.01

µA

CS, SHDN, RS = V

= 5.5V, SO = Open (Note 6)

Power Supply Sensitivity

PSS

0.0015

0.0035

%/%

= 4.5V - 5.5V, V

= 4.5V, Code 80h

PSS

0.0015

0.0035

%/%

= 2.7V - 3.3V, V

= 2.7V, Code 80h

Note

= V

, no connection on wiper.

= V

/R for

+3V or +5V for 50 k

version. See Figure 2-26 for test circuit.

INL and DNL are measured at V

with the device configured in the voltage divider or potentiometer mode. V

= V

and V

= 0V. DNL

specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.

Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.

Measured at V

pin where the voltage on the adjacent V

pin is swinging full scale.

Supply current is independent of current through the potentiometers.

MCP41XXX/42XXX

DS11195C-page 4

2003 Microchip Technology Inc.

DC CHARACTERISTICS: 100 k

VERSION

Electrical Characteristics: Unless otherwise indicated, V

= +2.7V to 5.5V, T

= -40°C to +85°C (TSSOP devices are only specified at +25°C and

+85°C). Typical specifications represent values for V

= 5V, V

= 0V, V

= 0V, T

= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat Mode
Nominal Resistance

100

130

= +25°C (Note 1)

Rheostat Differential Non-Linearity

R-DNL

-1

±1/4

LSB

Note 2

Rheostat Integral Non-Linearity

R-INL

-1

±1/4

LSB

Note 2

Rheostat Tempco

800

ppm/°C

Wiper Resistance

125

175

= 5.5V, I

= 1 mA, code 00h

175

250

= 2.7V, I

= 1 mA, code 00h

Wiper Current

-1

Nominal Resistance Match

R/R

0.2

MCP42010 only, P0 to P1;T

= +25°C

Potentiometer Divider
Resolution

Bits

Monotonicity

Bits

Differential Non-Linearity

DNL

-1

±1/4

LSB

Note 3

Integral Non-Linearity

INL

-1

±1/4

LSB

Note 3

Voltage Divider Tempco

ppm/°C Code 80h

Full-Scale Error

WFSE

-1

-0.25

LSB

Code FFh, V

= 5V, see Figure 2-25

WFSE

-1

-0.35

LSB

Code FFh, V

= 3V, see Figure 2-25

Zero-Scale Error

WZSE

+0.25

LSB

Code 00h, V

= 5V, see Figure 2-25

WZSE

+0.35

LSB

Code 00h, V

= 3V, see Figure 2-25

Resistor Terminals
Voltage Range

A,B,W

Note 4

Capacitance (C

or C

)

f =1 MHz, Code = 80h, see Figure 2-30

Capacitance

5.6

f =1 MHz, Code = 80h, see Figure 2-30

Dynamic Characteristics (All dynamic characteristics use V

= 5V.)

Bandwidth -3dB

145

MHz

= 0V, Measured at Code 80h,

Output Load = 30

Settling Time

µS

= V

= 0V, ±1% Error Band, Transition

from Code 00h to Code 80h, Output Load = 30 pF

Resistor Noise Voltage

NWB

nV/

Hz V

= Open, Code 80h

, f =1 kHz

Crosstalk

-95

= V

, V

= 0V (Note 5)

Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage

0.7V

Schmitt Trigger Low-Level Input Voltage

0.3V

Hysteresis of Schmitt Trigger Inputs

HYS

0.05V

Low-Level Output Voltage

0.40

= 2.1 mA, V

= 5V

High-Level Output Voltage

- 0.5

= -400 µA, V

= 5V

Input Leakage Current

-1

µA

CS = V

, V

= V

or V

, includes V

SHDN=0

Pin Capacitance (All inputs/outputs)

, C

OUT

= 5.0V, T

= +25°C, f

= 1 MHz

Power Requirements
Operating Voltage Range

2.7

5.5

Supply Current, Active

DDA

340

500

µA

= 5.5V, CS = V

, f

SCK

= 10 MHz,

SO = Open, Code FFh (Note 6)

Supply Current, Static

DDS

0.01

µA

CS, SHDN, RS = V

= 5.5V, SO = Open (Note 6)

Power Supply Sensitivity

PSS

0.0015

0.0035

%/%

= 4.5V - 5.5V, V

= 4.5V, Code 80h

PSS

0.0015

0.0035

%/%

= 2.7V - 3.3V, V

= 2.7V, Code 80h

Note

= V

, no connection on wiper.

= 50 µA for

= 3V and I

= 400 µA for V

= 5V for 10 k

version. See Figure 2-26 for test circuit.

INL and DNL are measured at V

with the device configured in the voltage divider or potentiometer mode. V

= V

and V

= 0V. DNL

specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.

Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.

Measured at V

pin where the voltage on the adjacent V

pin is swinging full-scale.

Supply current is independent of current through the potentiometers.

2003 Microchip Technology Inc.

DS11195C-page 5

MCP41XXX/42XXX

Absolute Maximum Ratings

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature .....................................-60°C to +150°C
Ambient temp. with power applied ................-60°C to +125°C
ESD protection on all pins

.................................................. 2 kV

Notice: Stresses above those listed under "maximum rat-
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.

AC TIMING CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V

= +2.7V to 5.5V, T

= -40°C to +85°C.

Parameter

Sym

Min.

Typ.

Max.

Units

Conditions

Clock Frequency

CLK

MHz

= 5V (Note 1)

Clock High Time

Clock Low Time

CS Fall to First Rising CLK Edge

CSSR

Data Input Setup Time

Data Input Hold Time

SCK Fall to SO Valid Propagation Delay

= 30 pF (Note 2)

SCK Rise to CS Rise Hold Time

CHS

SCK Rise to CS Fall Delay

CS0

CS Rise to CLK Rise Hold

CS1

100

CS High Time

CSH

Reset Pulse Width

150

Note 2

RS Rising to CS Falling Delay Time

RSCS

150

Note 2

CS rising to RS or SHDN falling delay time

Note 3

CS low time

CSL

100

Note 3

Shutdown Pulse Width

150

Note 3

Note

When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay
time (t

) and data input setup time (t

). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, t

40 ns, t

= 80 ns and t

= 40 ns.

Applies only to the MCP42XXX devices.

Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MCP42050T

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MCP42050T