1999 Microchip Technology Inc.

DS40139E-page 1

Devices included in this Data Sheet:

· PIC12C508

· PIC12C508A

· PIC12CE518

· PIC12C509

· PIC12C509A

· PIC12CE519

· PIC12CR509A

Note:

Throughout this data sheet PIC12C5XX
refers to the PIC12C508, PIC12C509,
PIC12C508A, PIC12C509A,
PIC12CR509A, PIC12CE518 and
PIC12CE519. PIC12CE5XX refers to
PIC12CE518 and PIC12CE519.

High-Performance RISC CPU:

· Only 33 single word instructions to learn

· All instructions are single cycle (1

s) except for

program branches which are two-cycle

· Operating speed: DC - 4 MHz clock input

DC - 1

s instruction cycle

· 12-bit wide instructions

· 8-bit wide data path

· Seven special function hardware registers

· Two-level deep hardware stack

· Direct, indirect and relative addressing modes for

data and instructions

· Internal 4 MHz RC oscillator with programmable

calibration

· In-circuit serial programming

Device

Memory

EPROM

Program

ROM

Program

RAM

Data

EEPROM

Data

PIC12C508

512 x 12

PIC12C508A

512 x 12

PIC12C509

1024 x 12

PIC12C509A

1024 x 12

PIC12CE518

512 x 12

PIC12CE519

1024 x 12

PIC12CR509A

1024 x 12

Peripheral Features:

· 8-bit real time clock/counter (TMR0) with 8-bit

programmable prescaler

· Power-On Reset (POR)

· Device Reset Timer (DRT)

· Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

· Programmable code-protection

· 1,000,000 erase/write cycle EEPROM data

memory

· EEPROM data retention > 40 years

· Power saving SLEEP mode

· Wake-up from SLEEP on pin change

· Internal weak pull-ups on I/O pins

· Internal pull-up on MCLR pin

· Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

- EXTRC: External low-cost RC oscillator

- XT:

Standard crystal/resonator

- LP:

Power saving, low frequency crystal

CMOS Technology:

· Low power, high speed CMOS EPROM/ROM

technology

· Fully static design

· Wide operating voltage range

· Wide temperature range:

- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C

· Low power consumption

- < 2 mA @ 5V, 4 MHz
- 15

A typical @ 3V, 32 KHz

- < 1

A typical standby current

PIC12C5XX

8-Pin, 8-Bit CMOS Microcontrollers

1999 Microchip Technology Inc.

DS40139E-page 3

PIC12C5XX

TABLE OF CONTENTS

1.0

General Description............................................................................................................................................... 4

2.0

PIC12C5XX Device Varieties ................................................................................................................................ 7

3.0

Architectural Overview........................................................................................................................................... 9

4.0

Memory Organization .......................................................................................................................................... 13

5.0

I/O Port ................................................................................................................................................................ 21

6.0

Timer0 Module and TMR0 Register .................................................................................................................... 25

7.0

EEPROM Peripheral Operation ........................................................................................................................... 29

8.0

Special Features of the CPU ............................................................................................................................... 35

9.0

Instruction Set Summary ..................................................................................................................................... 47

10.0 Development Support.......................................................................................................................................... 59
11.0 Electrical Characteristics - PIC12C508/PIC12C509 ............................................................................................ 65
12.0 DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75
13.0 Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/

PIC12CE518/PIC12CE519/
PIC12LCE518/PIC12LCE519/PIC12LCR509A ................................................................................................... 79

14.0 DC and AC Characteristics

PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/
PIC12LCE518/PIC12LCE519/ PIC12LCR509A .................................................................................................. 93

15.0 Packaging Information......................................................................................................................................... 99
Index ........................................................................................................................................................................... 105
PIC12C5XX Product Identification System ................................................................................................................ 109
Sales and Support: ..................................................................................................................................................... 109

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of doc-
ument DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec-
ommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet
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Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time
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We appreciate your assistance in making this a better document.

PIC12C5XX

DS40139E-page 4

1999 Microchip Technology Inc.

1.0

GENERAL DESCRIPTION

The PIC12C5XX from Microchip Technology is a fam-
ily of low-cost, high performance, 8-bit, fully static,
EEPROM/EPROM/ROM-based CMOS microcontrol-
lers. It employs a RISC architecture with only 33 sin-
gle word/single cycle instructions. All instructions are
single cycle (1

s) except for program branches

which take two cycles. The PIC12C5XX delivers per-
formance an order of magnitude higher than its com-
petitors in the same price category. The 12-bit wide
instructions are highly symmetrical resulting in 2:1
code compression over other 8-bit microcontrollers in
its class. The easy to use and easy to remember
instruction set reduces development time signifi-
cantly.

The PIC12C5XX products are equipped with special
features that reduce system cost and power require-
ments. The Power-On Reset (POR) and Device Reset
Timer (DRT) eliminate the need for external reset cir-
cuitry. There are four oscillator configurations to choose
from, including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Power
saving SLEEP mode, Watchdog Timer and code
protection features also improve system cost, power
and reliability.

The PIC12C5XX are available in the cost-effective
One-Time-Programmable (OTP) versions which are
suitable for production in any volume. The customer
can take full advantage of Microchip's price leadership
in OTP microcontrollers while benefiting from the OTP's
flexibility.

The PIC12C5XX products are supported by a full-fea-
tured macro assembler, a software simulator, an in-cir-
cuit emulator, a `C' compiler, fuzzy logic support tools,
a low-cost development programmer, and a full fea-
tured programmer. All the tools are supported on IBM

PC and compatible machines.

1.1

Applications

The PIC12C5XX series fits perfectly in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The EPROM technology makes customizing applica-
tion programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and conve-
nient, while the EEPROM data memory technology
allows for the changing of calibration factors and secu-
rity codes. The small footprint packages, for through
hole or surface mounting, make this microcontroller
series perfect for applications with space limitations.
Low-cost, low-power, high performance, ease of use
and I/O flexibility make the PIC12C5XX series very ver-
satile even in areas where no microcontroller use has
been considered before (e.g., timer functions, replace-
ment of "glue" logic and PLD's in larger systems, copro-
cessor applications).

1999 Microchip Technology Inc.

DS40139E-page 7

PIC12C5XX

2.0

PIC12C5XX DEVICE VARIETIES

A variety of packaging options are available.
Depending on application and production
requirements, the proper device option can be
selected using the information in this section. When
placing orders, please use the PIC12C5XX Product
Identification System at the back of this data sheet to
specify the correct part number.

2.1

UV Erasable Devices

The UV erasable version, offered in ceramic side
brazed package, is optimal for prototype development
and pilot programs.

The UV erasable version can be erased and
reprogrammed to any of the configuration modes.

Microchip's PICSTART

PLUS and PRO MATE

pro-

grammers all support programming of the PIC12C5XX.
Third party programmers also are available; refer to the

Microchip

Third Party Guide

for a list of sources.

2.2

One-Time-Programmable (OTP)
Devices

The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.

The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.

Note:

Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.

2.3

Quick-Turnaround-Production (QTP)
Devices

Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please con-
tact your local Microchip Technology sales office for
more details.

2.4

Serialized Quick-Turnaround
Production (SQTP

) Devices

Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.

Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.

2.5

Read Only Memory (ROM) Device

Microchip offers masked ROM to give the customer a
low cost option for high volume, mature products.

1999 Microchip Technology Inc.

DS40139E-page 9

PIC12C5XX

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC12C5XX family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12C5XX uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (1

s @ 4MHz) except for

program branches.

The table below lists program memory (EPROM), data
memory (RAM), ROM memory, and non-volatile
(EEPROM) for each device.

The PIC12C5XX can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC12C5XX has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of `special optimal situations' make
programming with the PIC12C5XX simple yet efficient.
In addition, the learning curve is reduced significantly.

Device

Memory

EPROM

Program

ROM

Program

RAM

Data

EEPROM

Data

PIC12C508

512 x 12

PIC12C509

1024 x 12

PIC12C508A

512 x 12

PIC12C509A

1024 x 12

PIC12CR509A

1024 x 12

PIC12CE518

512 x 12

25 x 8

16 x 8

PIC12CE519

1024 x 12

41 x 8

16 x 8

The PIC12C5XX device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.

The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.

The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the

SUBWF

and

ADDWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.

1999 Microchip Technology Inc.

DS40139E-page 11

PIC12C5XX

TABLE 3-1:

PIC12C5XX PINOUT DESCRIPTION

Name

DIP

Pin #

SOIC
Pin #

I/O/P
Type

Buffer

Type

Description

GP0

I/O

TTL/ST Bi-directional I/O port/ serial programming data. Can

be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.

GP1

I/O

TTL/ST Bi-directional I/O port/ serial programming clock. Can

be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.

GP2/T0CKI

I/O

Bi-directional I/O port. Can be configured as T0CKI.

GP3/MCLR/V

TTL/ST Input port/master clear (reset) input/programming volt-

age input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/V

must not exceed V

during normal device operation

or the device will enter programming mode. Can be
software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. Weak pull-up
always on if configured as MCLR. ST when in MCLR
mode.

GP4/OSC2

I/O

TTL

Bi-directional I/O port/oscillator crystal output. Con-
nections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, GPIO in other modes).

GP5/OSC1/CLKIN

I/O

TTL/ST Bidirectional IO port/oscillator crystal input/external

clock source input (GPIO in Internal RC mode only,
OSC1 in all other oscillator modes). TTL input when
GPIO, ST input in external RC oscillator mode.

Positive supply for logic and I/O pins

Ground reference for logic and I/O pins

Legend: I = input, O = output, I/O = input/output, P = power, -- = not used, TTL = TTL input,
ST = Schmitt Trigger input

PIC12C5XX

DS40139E-page 12

1999 Microchip Technology Inc.

3.1

Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.

3.2

Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g.,

GOTO

)

then two cycles are required to complete the
instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.

In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

OSC1

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase
clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 03H

Fetch 1

Execute 1

2. MOVWF GPIO

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF GPIO, BIT1

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

1999 Microchip Technology Inc.

DS40139E-page 13

PIC12C5XX

4.0

MEMORY ORGANIZATION

PIC12C5XX memory is organized into program mem-
ory and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one STA-
TUS register bit. For the PIC12C509, PIC12C509A,
PICCR509A and PIC12CE519 with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).

4.1

Program Memory Organization

The PIC12C5XX devices have a 12-bit Program
Counter (PC) capable of addressing a 2K x 12
program memory space.

Only the first 512 x 12 (0000h-01FFh) for the
PIC12C508, PIC12C508A and PIC12CE518 and 1K x
12 (0000h-03FFh) for the PIC12C509, PIC12C509A,
PIC12CR509A, and PIC12CE519 are physically
implemented. Refer to Figure 4-1. Accessing a
location above these boundaries will cause a wrap-
around within the first 512 x 12 space (PIC12C508,
PIC12C508A and PIC12CE518) or 1K x 12 space
(PIC12C509, PIC12C509A, PIC12CR509A and
PIC12CE519). The effective reset vector is at 000h,
(see Figure 4-1). Location 01FFh (PIC12C508,
PIC12C508A and PIC12CE518) or location 03FFh
(PIC12C509, PIC12C509A, PIC12CR509A and
PIC12CE519) contains the internal clock oscillator
calibration value. This value should never be
overwritten.

FIGURE 4-1:

PROGRAM MEMORY MAP
AND STACK

CALL, RETLW

PC<11:0>

Stack Level 1

Stack Level 2

r
y

ace

0000h

7FFh

01FFh
0200h

On-chip Program

Memory

Reset Vector (note 1)

Note 1: Address 0000h becomes the

effective reset vector. Location
01FFh (PIC12C508, PIC12C508A,
PIC12CE518) or location 03FFh
(PIC12C509, PIC12C509A,
PIC12CR509A, PIC12CE519) con-
tains the

MOVLW XX

INTERNAL RC

oscillator calibration value.

512 Word

1024 Word

03FFh
0400h

On-chip Program

Memory

PIC12C5XX

DS40139E-page 14

1999 Microchip Technology Inc.

4.2

Data Memory Organization

Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.

The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.

The general purpose registers are used for data and
control information under command of the instructions.

For the PIC12C508, PIC12C508A and PIC12CE518,
the register file is composed of 7 special function
registers and 25 general purpose registers (Figure 4-
2).

For the PIC12C509, PIC12C509A, PIC12CR509A,
and PIC12CE519 the register file is composed of 7
special function registers, 25 general purpose
registers, and 16 general purpose registers that may
be addressed using a banking scheme (Figure 4-3).

4.2.1

GENERAL PURPOSE REGISTER FILE

The general purpose register file is accessed either
directly or indirectly through the file select register FSR
(Section 4.8).

FIGURE 4-2:

PIC12C508, PIC12C508A AND
PIC12CE518 REGISTER FILE
MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

Note

Not a physical register. See Section 4.8

FIGURE 4-3:

PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

0Fh

10h

Bank 0

Bank 1

3Fh

30h

20h

2Fh

General
Purpose
Registers

Addresses map
back to
addresses
in Bank 0.

Note

Not a physical register. See Section 4.8

FSR<6:5>

1999 Microchip Technology Inc.

DS40139E-page 15

PIC12C5XX

4.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).

The special registers can be classified into two sets.
The special function registers associated with the
"core" functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.

TABLE 4-1:

SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

(2)

N/A

TRIS

--11 1111

N/A

OPTION

Contains control bits to configure Timer0, Timer0/WDT
prescaler, wake-up on change, and weak pull-ups

1111 1111

00h

INDF

Uses contents of FSR to address data memory (not a physical register)

xxxx xxxx

uuuu uuuu

01h

TMR0

8-bit real-time clock/counter

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Low order 8 bits of PC

1111 1111

03h

STATUS

GPWUF

PA0

0001 1xxx

q00q quuu

(3)

04h

FSR
(PIC12C508/
PIC12C508A/
PIC12C518)

Indirect data memory address pointer

111x xxxx

111u uuuu

04h

FSR
(PIC12C509/
PIC12C509A/
PIC12CR509A/
PIC12CE519)

Indirect data memory address pointer

110x xxxx

11uu uuuu

05h

OSCCAL
(PIC12C508/
PIC12C509)

CAL3

CAL2

CAL1

CAL0

0111 ----

uuuu ----

05h

OSCCAL
(PIC12C508A/
PIC12C509A/
PIC12CE518/
PIC12CE519/
PIC12CR509A)

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

1000 00--

uuuu uu--

06h

GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)

GP5

GP4

GP3

GP2

GP1

GP0

--xx xxxx

--uu uuuu

06h

GPIO
(PIC12CE518/
PIC12CE519)

SCL

SDA

GP5

GP4

GP3

GP2

GP1

GP0

11xx xxxx

11uu uuuu

Legend: Shaded boxes = unimplemented or unused,

= unimplemented, read as '0' (if applicable)

= unknown,

= unchanged,

= see the tables in Section 8.7 for possible values.

Note 1:

The upper byte of the Program Counter is not directly accessible. See Section 4.6
for an explanation of how to access these bits.

Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.

If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.

PIC12C5XX

DS40139E-page 16

1999 Microchip Technology Inc.

4.3

STATUS Register

This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bit for
program memories larger than 512 words.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.

For example,

CLRF STATUS

will clear the upper three

bits and set the Z bit. This leaves the STATUS register
as

000u u1uu

(where

= unchanged).

It is recommended, therefore, that only

BCF

BSF

and

MOVWF

instructions be used to alter the STATUS

register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Instruction Set Summary.

FIGURE 4-4:

STATUS REGISTER (ADDRESS:03h)

R/W-0

R-1

R/W-x

GPWUF

PA0

R = Readable bit
W = Writable bit
- n = Value at POR reset

bit7

bit0

bit 7:

GPWUF: GPIO reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset

bit 6:

Unimplemented

bit 5:

PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519
0 = Page 0 (000h - 1FFh) - PIC12C5XX
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended since this may affect upward compatibility with future products.

bit 4:

TO: Time-out bit
1 = After power-up,

CLRWDT

instruction, or

SLEEP

instruction

0 = A WDT time-out occurred

bit 3:

PD: Power-down bit
1 = After power-up or by the

CLRWDT

instruction

0 = By execution of the

SLEEP

instruction

bit 2:

Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1:

DC: Digit carry/borrow bit (for

ADDWF

and

SUBWF

instructions)

ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred

bit 0:

C: Carry/borrow bit (for

ADDWF

SUBWF

and

RRF

RLF

instructions)

ADDWF

SUBWF

RRF or RLF

1 = A carry occurred

1 = A borrow did not occur

Load bit with LSB or MSB, respectively

0 = A carry did not occur

0 = A borrow occurred

1999 Microchip Technology Inc.

DS40139E-page 17

PIC12C5XX

4.4

OPTION Register

The OPTION register is a 8-bit wide, write-only
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.

By executing the

OPTION

instruction, the contents of

the W register will be transferred to the OPTION
register. A RESET sets the OPTION<7:0> bits.

Note:

If TRIS bit is set to `0', the wake-up on
change and pull-up functions are disabled
for that pin; i.e., note that TRIS overrides
OPTION control of GPPU and GPWU.

Note:

If the T0CS bit is set to `1', GP2 is forced to
be an input even if TRIS GP2 = `0'.

FIGURE 4-5:

OPTION REGISTER

W-1

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

W = Writable bit
U

= Unimplemented bit

- n = Value at POR reset
Reference Table 4-1 for
other resets.

bit7

bit0

bit 7:

GPWU: Enable wake-up on pin change (GP0, GP1, GP3)
1 = Disabled
0 = Enabled

bit 6:

GPPU: Enable weak pull-ups (GP0, GP1, GP3)
1 = Disabled
0 = Enabled

bit 5:

T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Transition on internal instruction cycle clock, Fosc/4

bit 4:

T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin

bit 3:

PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0

bit 2-0:

PS2:PS0: Prescaler rate select bits

000

001

010

011

100

101

110

111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Bit Value

Timer0 Rate

WDT Rate

1999 Microchip Technology Inc.

DS40139E-page 19

PIC12C5XX

4.6

Program Counter

As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.

For a

GOTO

instruction, bits 8:0 of the PC are provided

by the

GOTO

instruction word. The PC Latch (PCL) is

mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 4-
8).

For a

CALL

instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-8).

Instructions where the PCL is the destination, or
Modify PCL instructions, include

MOVWF PC, ADDWF

PC,

and

BSF PC,5.

FIGURE 4-8:

LOADING OF PC
BRANCH INSTRUCTIONS -
PIC12C5XX

Note:

Because PC<8> is cleared in the

CALL

instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).

PA0

STATUS

PCL

Instruction Word

GOTO

Instruction

CALL

or Modify PCL Instruction

PA0

STATUS

PCL

Instruction Word

Reset to `0'

4.6.1

EFFECTS OF RESET

The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the oscillator calibration instruction. After
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.

The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.

Therefore, upon a RESET, a

GOTO

instruction will

automatically cause the program to jump to page 0
until the value of the page bits is altered.

4.7

Stack

PIC12C5XX devices have a 12-bit wide L.I.F.O.
hardware push/pop stack.

CALL

instruction will

push

the current value of stack

1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential

CALL

's are executed, only

the most recent two return addresses are stored.

RETLW

instruction will

pop

the contents of stack level

1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential

RETLW

's are executed, the stack will be filled with the

address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.

Upon any reset, the contents of the stack remain
unchanged, however the program counter (PCL) will
also be reset to 0.

Note 1: There are no STATUS bits to indicate

stack overflows or stack underflow condi-
tions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions
that occur from the execution of the

CALL

and

RETLW

instructions.

PIC12C5XX

DS40139E-page 20

1999 Microchip Technology Inc.

4.8

Indirect Data Addressing; INDF and
FSR Registers

The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a

pointer

). This is indirect addressing.

EXAMPLE 4-1:

INDIRECT ADDRESSING

· Register file 07 contains the value 10h
· Register file 08 contains the value 0Ah
· Load the value 07 into the FSR register
· A read of the INDF register will return the value

of 10h

· Increment the value of the FSR register by one

(FSR = 08)

· A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2:

HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING

movlw

0x10

;initialize pointer

movwf

FSR

; to RAM

clrf

INDF

;clear INDF register

incf

FSR,F

;inc pointer

btfsc

FSR,4

;all done?

goto

;NO, clear next

CONTINUE

;YES, continue

The FSR is a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.

The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.

PIC12C508/PIC12C508A/PIC12CE518: Does not
use banking. FSR<7:5> are unimplemented and read
as '1's.

PIC12C509/PIC12C509A/PIC12CR509A/
PIC12CE519: Uses FSR<5>. Selects between bank 0
and bank 1. FSR<7:6> is unimplemented, read as '1' .

FIGURE 4-9:

DIRECT/INDIRECT ADDRESSING

Note 1: For register map detail see Section 4.2.

Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519.

bank

location select

bank select

Indirect Addressing

Direct Addressing

Data
Memory

(1)

0Fh

10h

Bank 0

Bank 1

(2)

(FSR)

00h

1Fh

3Fh

(opcode)

(FSR)

Addresses
map back to
addresses
in Bank 0.

1999 Microchip Technology Inc.

DS40139E-page 21

PIC12C5XX

5.0

I/O PORT

As with any other register, the I/O register can be
written and read under program control. However, read
instructions (e.g.,

MOVF GPIO,W

) always read the I/O

pins independent of the pin's input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers are all
set. See Section 7.0 for SCL and SDA description for
PIC12CE5XX.

5.1

GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O's to
alternate functions. When acting as alternate functions
the pins will read as `0' during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not enabled.

5.2

TRIS Register

The output driver control register is loaded with the
contents of the W register by executing the

TRIS

instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see Figure 4-
5.

The TRIS registers are "write-only" and are set (output
drivers disabled) upon RESET.

Note:

A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.

5.3

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output operations.
For input operations these ports are non-latching. Any
input must be present until read by an input instruction
(e.g.,

MOVF GPIO,W

). The outputs are latched and

remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.

FIGURE 5-1:

EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN

Data
Bus

WR
Port

TRIS `f'

Data

TRIS

RD Port

I/O
pin

(1,3)

W
Reg

Latch

Reset

(2)

Note 1: I/O pins have protection diodes to V

and V

Note 2: See Table 3-1 for buffer type.

Note 3: See Section 7.0 for SCL and SDA

description for PIC12CE5XX

PIC12C5XX

DS40139E-page 22

1999 Microchip Technology Inc.

TABLE 5-1:

SUMMARY OF PORT REGISTERS

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

All Other Resets

N/A

TRIS

--11 1111

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

03H

STATUS

GPWUF

PAO

0001 1xxx

q00q quuu

(1)

06h

GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)

GP5

GP4

GP3

GP2

GP1

GP0

--xx xxxx

--uu uuuu

06h

GPIO
(PIC12CE518/
PIC12CE519)

SCL

SDA

GP5

GP4

GP3

GP2

GP1

GP0

11xx xxxx

11uu uuuu

Legend: Shaded cells not used by Port Registers, read as `0', -- = unimplemented, read as '0',

= unknown,

= unchanged,

q = see tables in Section 8.7 for possible values.

Note 1:

If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

5.4

I/O Programming Considerations

5.4.1

BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed
by write operations. The

BCF

and

BSF

instructions, for

example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a

BSF

operation on bit5 of GPIO will cause

all eight bits of GPIO to be read into the CPU, bit5 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bi-
directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.

Example 5-1 shows the effect of two sequential read-
modify-write instructions (e.g.,

BCF, BSF

, etc.) on an

I/O port.

A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin ("wired-or", "wired-
and"). The resulting high output currents may damage
the chip.

EXAMPLE 5-1:

READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT

;Initial GPIO Settings

; GPIO<5:3> Inputs

; GPIO<2:0> Outputs

;

; GPIO latch GPIO pins

; ---------- ----------

BCF GPIO, 5 ;--01 -ppp --11 pppp

BCF GPIO, 4 ;--10 -ppp --11 pppp

MOVLW 007h ;

TRIS GPIO ;--10 -ppp --11 pppp

;

;Note that the user may have expected the pin

;values to be --00 pppp. The 2nd BCF caused

;GP5 to be latched as the pin value (High).

5.4.2

SUCCESSIVE OPERATIONS ON I/O
PORTS

The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a

NOP

or another

instruction not accessing this I/O port.

1999 Microchip Technology Inc.

DS40139E-page 25

PIC12C5XX

6.0

TIMER0 MODULE AND
TMR0 REGISTER

The Timer0 module has the following features:

· 8-bit timer/counter register, TMR0

- Readable and writable

· 8-bit software programmable prescaler

· Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0
module.

Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.

The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.

A summary of registers associated with the Timer0
module is found in Table 6-1.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

T0CS

(1)

OSC

Programmable

Prescaler

(2)

Sync with

Internal

Clocks

TMR0 reg

PSout

(2 T

delay)

PSout

Data bus

PSA

(1)

PS2, PS1, PS0

(1)

Sync

T0SE

GP2/T0CKI

PIC12C5XX

DS40139E-page 26

1999 Microchip Technology Inc.

FIGURE 6-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

01h

TMR0

Timer0 - 8-bit real-time clock/counter

xxxx xxxx

uuuu uuuu

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

N/A

TRIS

GP5

GP4

GP3

GP2

GP1

GP0

--11 1111

Legend: Shaded cells not used by Timer0,

= unimplemented,

= unknown,

= unchanged,

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC
(Program
Counter)

Instruction

Fetch

Timer0

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

T0+1

T0+2

NT0

NT0+1

NT0+2

MOVWF TMR0

MOVF TMR0,W

Write TMR0
executed

Read TMR0
reads NT0

Read TMR0
reads NT0 + 1

Read TMR0
reads NT0 + 2

Instruction
Executed

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC
(Program
Counter)

Instruction

Fetch

Timer0

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

NT0+1

MOVWF TMR0

MOVF TMR0,W

Write TMR0
executed

Read TMR0
reads NT0

Read TMR0
reads NT0 + 1

T0+1

NT0

Instruction
Execute

1999 Microchip Technology Inc.

DS40139E-page 27

PIC12C5XX

6.1

Using Timer0 with an External Clock

When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (T

OSC

)

synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2T

OSC

(and a small RC delay of 20 ns)

and low for at least 2T

OSC

(and a small RC delay of

20 ns). Refer to the electrical specification of the
desired device.

When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4T

OSC

(and a small RC delay of

40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.

6.1.3

OPTION REGISTER EFFECT ON GP2 TRIS

If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of the TRIS reg-
ister setting.

FIGURE 6-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or

Q3 Q4

Timer0

T0 + 1

T0 + 2

Small pulse
misses sampling

External Clock/Prescaler

Output After Sampling

(3)

Note 1:

2:
3:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input =

4Tosc max.

External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.

Prescaler Output (2)

(1)

PIC12C5XX

DS40139E-page 28

1999 Microchip Technology Inc.

6.2

Prescaler

An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 8.6). For simplicity,
this counter is being referred to as "prescaler"
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>)
determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g.,

CLRF 1,

MOVWF 1, BSF 1,x,

etc.) will clear the prescaler.

When assigned to WDT, a

CLRWDT

instruction will

clear the prescaler along with the WDT. The prescaler
is neither readable nor writable. On a RESET, the
prescaler contains all '0's.

6.2.1

SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control
(i.e., it can be changed "on the fly" during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.

EXAMPLE 6-1:

CHANGING PRESCALER
(TIMER0

WDT)

1.CLRWDT

;Clear WDT

2.CLRF

TMR0

;Clear TMR0 & Prescaler

3.MOVLW

'00xx1111'b ;These 3 lines (5, 6, 7)

4.OPTION

; are required only if

; desired

5.CLRWDT

;PS<2:0> are 000 or 001

6.MOVLW

'00xx1xxx'b ;Set Postscaler to

7.OPTION

; desired WDT rate

To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A

CLRWDT

instruction should be executed before

switching the prescaler.

EXAMPLE 6-2:

CHANGING PRESCALER
(WDT

TIMER0)

CLRWDT

;Clear WDT and

;prescaler

MOVLW

'xxxx0xxx'

;Select TMR0, new

;prescale value and

;clock source

OPTION

FIGURE 6-5:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

( = Fosc/4)

Sync

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

MUX

Watchdog

Timer

PSA

WDT

Time-Out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

PSA

WDT Enable bit

Data Bus

PSA

T0CS

U
X

T0SE

GP2/T0CKI

1999 Microchip Technology Inc.

DS40139E-page 29

PIC12C5XX

7.0

EEPROM PERIPHERAL
OPERATION

This section applies to PIC12CE518 and
PIC12CE519 only.

The PIC12CE518 and PIC12CE519 each have 16
bytes of EEPROM data memory. The EEPROM mem-
ory has an endurance of 1,000,000 erase/write cycles
and a data retention of greater than 40 years. The
EEPROM data memory supports a bi-directional 2-wire
bus and data transmission protocol. These two-wires
are serial data (SDA) and serial clock (SCL), that are
mapped to bit6 and bit7, respectively, of the GPIO reg-
ister (SFR 06h). Unlike the GP0-GP5 that are con-
nected to the I/O pins, SDA and SCL are only
connected to the internal EEPROM peripheral. For
most applications, all that is required is calls to the fol-
lowing functions:

; Byte_Write: Byte write routine

;

Inputs: EEPROM Address

EEADDR

;

EEPROM Data

EEDATA

;

Outputs:

Return 01 in W if OK, else

return 00 in W

;

; Read_Current: Read EEPROM at address

currently held by EE device.

;

Inputs: NONE

;

Outputs:

EEPROM Data

EEDATA

;

Return 01 in W if OK, else

return 00 in W

;

; Read_Random: Read EEPROM byte at supplied

address

;

Inputs: EEPROM Address

EEADDR

;

Outputs:

EEPROM Data

EEDATA

;

Return 01 in W if OK,

else return 00 in W

The code for these functions is available on our website
www.microchip.com. The code will be accessed by
either including the source code FL51XINC.ASM or by
linking FLASH5IX.ASM.

It is very important to check the return codes when
using these calls, and retry the operation if unsuccess-
ful. Unsuccessful return codes occur when the EE data
memory is busy with the previous write, which can take
up to 4 mS.

7.0.1

SERIAL DATA

SDA is a bi-directional pin used to transfer addresses
and data into and data out of the device.

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.

The EEPROM interface is a 2-wire bus protocol con-
sisting of data (SDA) and a clock (SCL). Although
these lines are mapped into the GPIO register, they are
not accessible as external pins; only to the internal
EEPROM peripheral. SDA and SCL operation is also
slightly different than GPO-GP5 as listed below.

Namely, to avoid code overhead in modifying the TRIS
register, both SDA and SCL are always outputs. To
read data from the EEPROM peripheral requires out-
putting a `1' on SDA placing it in high-Z state, where
only the internal 100K pull-up is active on the SDA line.

SDA:

Built-in 100K (typical) pull-up to VDD
Open-drain (pull-down only)
Always an output
Outputs a `1' on reset

SCL:

Full CMOS output
Always an output
Outputs a `1' on reset

The following example requires:

· Code Space: 77 words

· RAM Space: 5 bytes (4 are overlayable)

· Stack Levels:1 (The call to the function itself. The

functions do not call any lower level functions.)

· Timing:

- WRITE_BYTE takes 328 cycles

- READ_CURRENT takes 212 cycles

- READ_RANDOM takes 416 cycles.

· IO Pins: 0 (No external IO pins are used)

This code must reside in the lower half of a page. The
code achieves it's small size without additional calls
through the use of a sequencing table. The table is a
list of procedures that must be called in order. The
table uses an ADDWF PCL,F instruction, effectively a
computed goto, to sequence to the next procedure.
However the ADDWF PCL,F instruction yields an 8 bit
address, forcing the code to reside in the first 256
addresses of a page.

1999 Microchip Technology Inc.

DS40139E-page 31

PIC12C5XX

7.0.2

SERIAL CLOCK

This SCL input is used to synchronize the data transfer
from and to the device.

7.1

BUS CHARACTERISTICS

The following bus protocol is to be used with the
EEPROM data memory.

· Data transfer may be initiated only when the bus

is not busy.

During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 7-3).

7.1.1

BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

7.1.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

7.1.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

7.1.4

DATA VALID (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

7.1.5

ACKNOWLEDGE

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 7-4).

Note:

Acknowledge bits are not generated if an
internal programming cycle is in progress.

1999 Microchip Technology Inc.

DS40139E-page 33

PIC12C5XX

7.3

WRITE OPERATIONS

7.3.1

BYTE WRITE

Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don't cares. The address byte is acknowledgeable and
the master device will then transmit the data word to be
written into the addressed memory location. The mem-
ory acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge sig-
nals (Figure 7-7). After a byte write command, the inter-
nal address counter will not be incremented and will
point to the same address location that was just written.
If a stop bit is transmitted to the device at any point in
the write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a stop bit is sent before a
full eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a V

threshold detector

circuit which disables the internal erase/write logic if the
V

is below minimum VDD.

Byte write operations must be preceded and immedi-
ately followed by a bus not busy bus cycle where both
SDA and SCL are held high.

7.4

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-6 for
flow diagram.

FIGURE 7-6:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

FIGURE 7-7:

BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

X = Don't Care Bit

PIC12C5XX

DS40139E-page 34

1999 Microchip Technology Inc.

7.5

READ OPERATIONS

Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

7.5.1

CURRENT ADDRESS READ

It contains an address counter that maintains the
address of the last word accessed, internally incre-
mented by one. Therefore, if the previous read access
was to address n, the next current address read opera-
tion would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
device discontinues transmission (Figure 7-8).

7.5.2

RANDOM READ

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the

device as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. It will then issue an
acknowledge and transmits the eight bit data word. The
master will not acknowledge the transfer but does gen-
erate a stop condition and the device discontinues
transmission (Figure 7-9). After this command, the
internal address counter will point to the address loca-
tion following the one that was just read.

7.5.3

SEQUENTIAL READ

Sequential reads are initiated in the same way as a ran-
dom read except that after the device transmits the first
data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 7-10).

To provide sequential reads, it contains an internal
address pointer which is incremented by one at the
completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

FIGURE 7-8:

CURRENT ADDRESS READ

FIGURE 7-9:

RANDOM READ

FIGURE 7-10: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

S
T
A
R
T

DATA

A
C
K

N
O

A
C
K

0 X X X 1

X = Don't Care Bit

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

N
O

A
C
K

X X X X

S 1

0 X X X 0

S 1

0 X X X 1

X = Don't Care Bit

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A
C
K

1999 Microchip Technology Inc.

DS40139E-page 35

PIC12C5XX

8.0

SPECIAL FEATURES OF THE
CPU

What sets a microcontroller apart from other
processors are special circuits to deal with the needs
of real-time applications. The PIC12C5XX family of
microcontrollers has a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:

· Oscillator selection

· Reset

- Power-On Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from SLEEP on pin change

· Watchdog Timer (WDT)

· SLEEP

· Code protection

· ID locations

· In-circuit Serial Programming

The PIC12C5XX has a Watchdog Timer which can be
shut off only through configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
XT or LP selectable oscillator options, there is always
an 18 ms (nominal) delay provided by the Device
Reset Timer (DRT), intended to keep the chip in reset
until the crystal oscillator is stable. If using INTRC or
EXTRC there is an 18 ms delay only on V

power-up.

With this timer on-chip, most applications need no
external reset circuitry.

The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRC oscillator option saves system cost while
the LP crystal option saves power. A set of
configuration bits are used to select various options.

8.1

Configuration Bits

The PIC12C5XX configuration word consists of 12
bits. Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.

FIGURE 8-1:

CONFIGURATION WORD FOR PIC12C5XX

MCLRE

WDTE FOSC1 FOSC0

CONFIG

Address

(1)

FFFh

bit11

bit0

bit 11-5: Unimplemented

bit 4:

MCLRE: MCLR enable bit.
1 = MCLR pin enabled
0 = MCLR tied to V

, (Internally)

bit 3:

CP: Code protection bit.
1 = Code protection off
0 = Code protection on

bit 2:

WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled

bit 1-0:

FOSC1:FOSC0: Oscillator selection bits
11 = EXTRC - external RC oscillator
10 = INTRC - internal RC oscillator
01 = XT oscillator
00 = LP oscillator

Note 1:

Refer to the PIC12C5XX Programming Specifications to determine how to access the
configuration word. This register is not user addressable during device operation.

PIC12C5XX

DS40139E-page 36

1999 Microchip Technology Inc.

8.2

Oscillator Configurations

8.2.1

OSCILLATOR TYPES

The PIC12C5XX can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1:FOSC0) to select one of
these four modes:

· LP:

Low Power Crystal

· XT:

Crystal/Resonator

· INTRC: Internal 4 MHz Oscillator

· EXTRC: External Resistor/Capacitor

8.2.2

CRYSTAL OSCILLATOR / CERAMIC
RESONATORS

In XT or LP modes, a crystal or ceramic resonator is
connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 8-2). The
PIC12C5XX oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT or LP modes, the device
can have an external clock source drive the GP5/
OSC1/CLKIN pin (Figure 8-3).

FIGURE 8-2:

CRYSTAL OPERATION (OR
CERAMIC RESONATOR) (XT
OR LP OSC
CONFIGURATION)

FIGURE 8-3:

EXTERNAL CLOCK INPUT
OPERATION (XT OR LP OSC
CONFIGURATION)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF approximate value = 10 M

(1)

XTAL

OSC2

OSC1

(3)

SLEEP

To internal

logic

(2)

PIC12C5XX

Clock from
ext. system

OSC1

OSC2

Open

PIC12C5XX

TABLE 8-1:

CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C5XX

TABLE 8-2:

CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR -
PIC12C5XX

Osc

Type

Resonator

Freq

Cap. Range

4.0 MHz

30 pF

These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.

Osc

Type

Resonator

Freq

Cap.Range

Cap. Range

32 kHz

(1)

15 pF

200 kHz

1 MHz
4 MHz

47-68 pF

15 pF
15 pF

47-68 pF

15 pF
15 pF

Note 1: For V

> 4.5V, C1 = C2

30 pF is

recommended.

These values are for design guidance only. Rs may
be required to avoid overdriving crystals with low
drive level specification. Since each crystal has its
own characteristics, the user should consult the crys-
tal manufacturer for appropriate values of external
components.

1999 Microchip Technology Inc.

DS40139E-page 37

PIC12C5XX

8.2.3

EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT

Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.

Figure 8-4 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 k

resistor

provides the negative feedback for stability. The 10 k

potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.

FIGURE 8-4:

EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT

Figure 8-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330

resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 8-5:

EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

CLKIN

To Other
Devices

PIC12C5XX

330

74AS04

CLKIN

To Other
Devices

XTAL

330

74AS04

0.1

PIC12C5XX

8.2.4

EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.

Figure 8-6 shows how the R/C combination is
connected to the PIC12C5XX. For Rext values below
2.2 k

, the oscillator operation may become unstable,

or stop completely. For very high Rext values
(e.g., 1 M

) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping
Rext between 3 k

and 100 k

Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.

The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).

Also, see the Electrical Specifications sections for
variation of oscillator frequency due to V

for given

Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and V

values.

FIGURE 8-6:

EXTERNAL RC OSCILLATOR
MODE

Rext

Cext

OSC1

Internal
clock

PIC12C5XX

PIC12C5XX

DS40139E-page 38

1999 Microchip Technology Inc.

8.2.5

INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, see "Electri-
cal Specifications" section for information on variation
over voltage and temperature.

In addition, a calibration instruction is programmed into
the top of memory which contains the calibration value
for the internal RC oscillator. This location is never code
protected regardless of the code protect settings. This
value is programmed as a

MOVLW XX

instruction where

XX is the calibration value, and is placed at the reset
vector. This will load the W register with the calibration
value upon reset and the PC will then roll over to the
users program at address 0x000. The user then has the
option of writing the value to the OSCCAL Register
(05h) or ignoring it.

OSCCAL, when written to with the calibration value, will
"trim" the internal oscillator to remove process variation
from the oscillator frequency. .

For the PIC12C508A, PIC12C509A, PIC12CE518,
PIC12CE519, and PIC12CR509A, bits <7:2>, CAL5-
CAL0 are used for calibration. Adjusting CAL5-0 from
000000 to 111111 yields a higher clock speed. Note
that bits 1 and 0 of OSCCAL are unimplemented and
should be written as 0 when modifying OSCCAL for
compatibility with future devices.

For the PIC12C508 and PIC12C509, the upper 4 bits of
the register are used. Writing a larger value in this loca-
tion yields a higher clock speed.

8.3

RESET

The device differentiates between various kinds of
reset:

a) Power on reset (POR)

b) MCLR reset during normal operation

c) MCLR reset during SLEEP

d) WDT time-out reset during normal operation

e) WDT time-out reset during SLEEP

f) Wake-up from SLEEP on pin change

Note:

Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be read prior to
erasing the part. so it can be repro-
grammed correctly later.

Some registers are not reset in any way; they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to "reset state" on power-
on reset (POR), MCLR, WDT or wake-up on pin
change reset during normal operation. They are not
affected by a WDT reset during SLEEP or MCLR reset
during SLEEP, since these resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD, and GPWUF bits. They are set or cleared
differently in different reset situations. These bits are
used in software to determine the nature of reset. See
Table 8-3 for a full description of reset states of all
registers.

1999 Microchip Technology Inc.

DS40139E-page 39

PIC12C5XX

TABLE 8-3:

RESET CONDITIONS FOR REGISTERS

TABLE 8-4:

RESET CONDITION FOR SPECIAL REGISTERS

Register

Address

Power-on Reset

MCLR Reset

WDT time-out

Wake-up on Pin Change

W (PIC12C508/509)

qqqq xxxx

(1)

qqqq uuuu

(1)

W (PIC12C508A/509A/
PIC12CE518/519/
PIC12CE509A)

qqqq qqxx

(1)

qqqq qquu

(1)

INDF

00h

xxxx xxxx

uuuu uuuu

TMR0

01h

xxxx xxxx

uuuu uuuu

02h

1111 1111

STATUS

03h

0001 1xxx

q00q quuu

(2,3)

FSR (PIC12C508/
PIC12C508A/
PIC12CE518)

04h

111x xxxx

111u uuuu

FSR (PIC12C509/
PIC12C509A/
PIC12CE519/
PIC12CR509A)

04h

110x xxxx

11uu uuuu

OSCCAL
(PIC12C508/509)

05h

0111 ----

uuuu ----

OSCCAL
(PIC12C508A/509A/
PIC12CE518/512/
PIC12CR509A)

05h

1000 00--

uuuu uu--

GPIO
(PIC12C508/PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)

06h

--xx xxxx

--uu uuuu

GPIO
(PIC12CE518/
PIC12CE519)

06h

11xx xxxx

11uu uuuu

OPTION

1111 1111

TRIS

--11 1111

Legend:

= unchanged,

= unknown,

= unimplemented bit, read as `0',

= value depends on condition.

Note 1:

Bits <7:2> of W register contain oscillator calibration values due to

MOVLW XX

instruction at top of memory.

Note 2:

See Table 8-7 for reset value for specific conditions

Note 3:

If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.

STATUS Addr: 03h

PCL Addr: 02h

Power on reset

0001 1xxx

1111 1111

MCLR reset during normal operation

000u uuuu

1111 1111

MCLR reset during SLEEP

0001 0uuu

1111 1111

WDT reset during SLEEP

0000 0uuu

1111 1111

WDT reset normal operation

0000 uuuu

1111 1111

Wake-up from SLEEP on pin change

1001 0uuu

1111 1111

Legend:

= unchanged,

= unknown,

= unimplemented bit, read as `0'.

PIC12C5XX

DS40139E-page 40

1999 Microchip Technology Inc.

8.3.1

MCLR ENABLE

This configuration bit when unprogrammed (left in the
`1' state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V

, and the pin is assigned to be a GPIO. See

Figure 8-7. When pin GP3/MCLR/V

is configured as

MCLR, the internal pull-up is always on.

FIGURE 8-7:

MCLR SELECT

8.4

Power-On Reset (POR)

The PIC12C5XX family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.

The on-chip POR circuit holds the chip in reset until
V

has reached a high enough level for proper opera-

tion. To take advantage of the internal POR, program
the GP3/MCLR/V

pin as MCLR and tie through a

resistor to V

or program the pin as GP3. An internal

weak pull-up resistor is implemented using a transistor.
Refer to Table 11-1 for the pull-up resistor ranges. This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
V

is specified. See Electrical Specifications for

details.

When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.

A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 8-8.

GP3/MCLR/V

MCLRE

INTERNAL MCLR

WEAK
PULL-UP

The Power-On Reset circuit and the Device Reset
Timer (Section 8.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.

A power-up example where MCLR is held low is
shown in Figure 8-9. V

is allowed to rise and

stabilize before bringing MCLR high. The chip will
actually come out of reset T

DRT

msec after MCLR

goes high.

In Figure 8-10, the on-chip Power-On Reset feature is
being used (MCLR and V

are tied together or the

pin is programmed to be GP3.). The V

is stable

before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 8-
11 depicts a problem situation where V

rises too

slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and V

) actually

reach their full value, is too long. In this situation, when
the start-up timer times out, V

has not reached the

(min) value and the chip is, therefore, not

guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-10).

For additional information refer to Application Notes
"

Power-Up Considerations"

- AN522 and "

Power-up

Trouble Shooting

" - AN607.

Note:

When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, tempera-
ture, etc.) must be meet to ensure opera-
tion. If these conditions are not met, the
device must be held in reset until the oper-
ating conditions are met.

PIC12C5XX

DS40139E-page 42

1999 Microchip Technology Inc.

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V

): SLOW V

RISE TIME

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

DRT

When V

rises slowly, the T

DRT

time-out expires long before V

has reached its final value. In

this example, the chip will reset properly if, and only if, V1

min.

8.5

Device Reset Timer (DRT)

In the PIC12C5XX, DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)

The DRT operates on an internal RC oscillator. The
processor is kept in RESET as long as the DRT is
active. The DRT delay allows V

to rise above V

min., and for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (V

MCLR)

level. Thus, programming GP3/MCLR/V

as MCLR

and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the GP3/
MCLR/V

pin as a general purpose input.

The Device Reset time delay will vary from chip to chip
due to V

, temperature, and process variation. See

AC parameters for details.

The DRT will also be triggered upon a Watchdog
Timer time-out. This is particularly important for
applications using the WDT to wake from SLEEP
mode automatically.

8.6

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a

SLEEP

instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.

The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.

The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 8.1). Refer to the PIC12C5XX Programming
Specifications to determine how to access the
configuration word.

TABLE 8-5:

DRT (DEVICE RESET TIMER
PERIOD)

Oscillator

Configuration

POR Reset

Subsequent

Resets

IntRC &
ExtRC

18 ms (typical)

300 µs (typical)

XT & LP

18 ms (typical)

1999 Microchip Technology Inc.

DS40139E-page 43

PIC12C5XX

8.6.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, V

and part-to-

part process variations (see DC specs).

Under worst case conditions (V

= Min., Temperature

= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.

8.6.2

WDT PROGRAMMING CONSIDERATIONS

The

CLRWDT

instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.

The

SLEEP

instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.

FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 8-6:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer,

= unimplemented, read as '0',

= unchanged

From Timer0 Clock Source
(Figure 8-5)

To Timer0 (Figure 8-4)

Postscaler

WDT Enable

Configuration Bit

PSA

WDT

Time-out

PS2:PS0

PSA

MUX

8 - to - 1 MUX

Postscaler

Watchdog

Timer

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

PIC12C5XX

DS40139E-page 44

1999 Microchip Technology Inc.

8.7

Time-Out Sequence, Power Down,
and Wake-up from SLEEP Status Bits
(TO/PD/GPWUF)

The TO, PD, and GPWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset.

8.8

Reset on Brown-Out

A brown-out is a condition where device power (V

)

dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.

To reset PIC12C5XX devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 8-13 , Figure 8-14 and
Figure 8-15

FIGURE 8-13: BROWN-OUT PROTECTION

CIRCUIT 1

TABLE 8-7:

TO/PD/GPWUF STATUS
AFTER RESET

GPWUF

RESET caused by

WDT wake-up from
SLEEP

WDT time-out (not from
SLEEP)

MCLR wake-up from
SLEEP

Power-up

MCLR not during SLEEP

Wake-up from SLEEP on
pin change

Legend: u = unchanged
Note 1: The TO, PD, and GPWUF bits maintain

their status (u) until a reset occurs. A low-
pulse on the MCLR input does not change
the TO, PD, and GPWUF status bits.

This circuit will activate reset when V

goes below

Vz + 0.7V (where Vz = Zener voltage).

*Refer to Figure 8-7 and Table 11-1 for internal
weak pull-up on MCLR.

33k

10k

40k*

MCLR

PIC12C5XX

FIGURE 8-14: BROWN-OUT PROTECTION

CIRCUIT 2

FIGURE 8-15: BROWN-OUT PROTECTION

CIRCUIT 3

This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when V

is below a certain level such that:

*Refer to Figure 8-7 and Table 11-1 for internal
weak pull-up on MCLR.

R1 + R2

= 0.7V

40k*

MCLR

PIC12C5XX

This brown-out protection circuit employs
Microchip Technology's MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX family of
supervisors provide push-pull and open collector
outputs with both high and low active reset pins.
There are 7 different trip point selections to
accomodate 5V and 3V systems.

MCLR

PIC12C5XX

Vss

RST

MCP809

bypass

capacitor

1999 Microchip Technology Inc.

DS40139E-page 45

PIC12C5XX

8.9

Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).

8.9.1

SLEEP

The Power-Down mode is entered by executing a

SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the

SLEEP

instruction was executed (driving

high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.

For lowest current consumption while powered down,
the T0CKI input should be at V

or V

and the GP3/

MCLR/V

pin must be at a logic high level (V

IHMC

) if

MCLR is enabled.

8.9.2

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of
the following events:

An external reset input on GP3/MCLR/V

pin,

when configured as MCLR.

A Watchdog Timer time-out reset (if WDT was
enabled).

A change on input pin GP0, GP1, or GP3/
MCLR/V

when wake-up on change is

enabled.

These events cause a device reset. The TO, PD, and
GPWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when

SLEEP

is invoked.

The GPWUF bit indicates a change in state while in
SLEEP at pins GP0, GP1, or GP3 (since the last time
there was a file or bit operation on GP port).

The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.

Caution: Right before entering SLEEP, read the

input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before
reentering SLEEP, a wake up will occur
immediately even if no pins change while
in SLEEP mode.

8.10

Program Verification/Code Protection

If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.

The first 64 locations can be read by the PIC12C5XX
regardless of the code protection bit setting.

The last memory location cannot be read if code pro-
tection is enabled on the PIC12C508/509.

The last memory location can be read regardless of the
code protection bit setting on the PIC12C508A/509A/
CR509A/CE518/CE519.

8.11

ID Locations

Four memory locations are designated as ID locations
where the user can store checksum or other code-
identification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.

Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as '0's.

1999 Microchip Technology Inc.

DS40139E-page 47

PIC12C5XX

9.0

INSTRUCTION SET SUMMARY

Each PIC12C5XX instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC12C5XX
instruction set summary in Table 9-2 groups the
instructions into byte-oriented, bit-oriented, and literal
and control operations. Table 9-1 shows the opcode
field descriptions.

For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.

The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.

For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.

TABLE 9-1:

OPCODE FIELD
DESCRIPTIONS

Field

Description

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.

Destination select;

d = 0 (store result in W)
d = 1 (store result in file register 'f')

Default is d = 1

label

Label name

TOS

Top of Stack

Program Counter

WDT

Watchdog Timer Counter

Time-Out bit

Power-Down bit

dest

Destination, either the W register or the specified
register file location

[ ]

Options

( )

Contents

Assigned to

< >

In the set of

talics

User defined term (font is courier)

All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1

s. If a conditional test is

true or the program counter is changed as a result of
an instruction, the instruction execution time is 2

Figure 9-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:

0xhhh

where 'h' signifies a hexadecimal digit.

FIGURE 9-1:

GENERAL FORMAT FOR
INSTRUCTIONS

Byte-oriented file register operations

11 6 5 4 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f
f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address
f = 5-bit file register address

Literal and control operations (except

GOTO

)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations -

GOTO

instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

PIC12C5XX

DS40139E-page 48

1999 Microchip Technology Inc.

TABLE 9-2:

INSTRUCTION SET SUMMARY

Mnemonic,

Operands

Description

Cycles

12-Bit Opcode

Status

Affected Notes

MSb

LSb

ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF

f,d
f,d
f

f, d
f, d
f, d
f, d
f, d
f, d
f, d
f

f, d
f, d
f, d
f, d
f, d

Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f

1
1
1
1
1
1

1(2)

1
1
1
1
1
1
1
1
1

0001

0000

0010

0000

0010

0011

0001

0010

0000

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

10df

11df

00df

001f

0000

01df

00df

10df

ffff

0000

ffff

0000

ffff

C,DC,Z

Z
Z
Z
Z
Z

None

Z
Z

None
None

C
C

C,DC,Z

None

1,2,4

2,4

2,4
2,4
2,4
2,4
2,4
2,4
1,4

2,4
2,4

1,2,4

2,4
2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF
BSF
BTFSC
BTFSS

f, b
f, b
f, b
f, b

Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set

1
1

1 (2)
1 (2)

0100

0101

0110

0111

bbbf

ffff

None
None
None
None

2,4
2,4

LITERAL AND CONTROL OPERATIONS

ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW

k
k
k
k
k
k

k

f
k

AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W

1
2
1
2
1
1
1
2
1
1
1

1110

1001

0000

101k

1101

1100

0000

1000

0000

1111

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0100

kkkk

0010

kkkk

0011

0fff

kkkk

None

None
None
None

None

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for

GOTO

(Section 4.6)

2: When an I/O register is modified as a function of itself (e.g.

MOVF GPIO, 1

), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.

3: The instruction

TRIS f

, where f = 6 causes the contents of the W register to be written to the tristate latches of

GPIO. A '1' forces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

1999 Microchip Technology Inc.

DS40139E-page 49

PIC12C5XX

ADDWF

Add W and f

Syntax:

[

label

] ADDWF f,d

Operands:

[0,1]

Operation:

(W) + (f)

(dest)

Status Affected:

C, DC, Z

Encoding:

0001

11df

ffff

Description:

Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'

Words:

Cycles:

Example:

ADDWF

FSR, 0

Before Instruction

0x17

FSR =

0xC2

After Instruction

0xD9

FSR =

0xC2

ANDLW

And literal with W

Syntax:

[

label

] ANDLW k

Operands:

255

Operation:

(W).AND. (k)

(W)

Status Affected:

Encoding:

1110

kkkk

Description:

The contents of the W register are
AND'ed with the eight-bit literal 'k'. The
result is placed in the W register

Words:

Cycles:

Example:

ANDLW

0x5F

Before Instruction

0xA3

After Instruction

W =

0x03

ANDWF

AND W with f

Syntax:

[

label

] ANDWF f,d

Operands:

[0,1]

Operation:

(W) .AND. (f)

(dest)

Status Affected:

Encoding:

0001

01df

ffff

Description:

The contents of the W register are
AND'ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'

Words:

Cycles:

Example:

ANDWF

FSR,

Before Instruction

0x17

FSR =

0xC2

After Instruction

0x17

FSR =

0x02

BCF

Bit Clear f

Syntax:

[

label

] BCF f,b

Operands:

Operation:

(f<b>)

Status Affected:

None

Encoding:

0100

bbbf

ffff

Description:

Bit 'b' in register 'f' is cleared.

Words:

Cycles:

Example:

BCF

FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

PIC12C5XX

DS40139E-page 50

1999 Microchip Technology Inc.

BSF

Bit Set f

Syntax:

[

label

] BSF f,b

Operands:

Operation:

(f<b>)

Status Affected:

None

Encoding:

0101

bbbf

ffff

Description:

Bit 'b' in register 'f' is set.

Words:

Cycles:

Example:

BSF

FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC

Bit Test f, Skip if Clear

Syntax:

[

label

] BTFSC f,b

Operands:

Operation:

skip if (f<b>) = 0

Status Affected:

None

Encoding:

0110

bbbf

ffff

Description:

If bit 'b' in register 'f' is 0 then the next
instruction is skipped.

If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.

Words:

Cycles:

1(2)

Example:

HERE

FALSE

TRUE

BTFSC

GOTO

FLAG,1

PROCESS_CODE

Before Instruction

address

(HERE)

After Instruction

if FLAG<1>

address

(TRUE)

;

if FLAG<1>

address

(FALSE)

BTFSS

Bit Test f, Skip if Set

Syntax:

[

label

] BTFSS f,b

Operands:

b < 7

Operation:

skip if (f<b>) = 1

Status Affected:

None

Encoding:

0111

bbbf

ffff

Description:

If bit 'b' in register 'f' is '1' then the next
instruction is skipped.

If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and an NOP is
executed instead, making this a 2 cycle
instruction.

Words:

Cycles:

1(2)

Example:

HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE

Before Instruction

address

(HERE)

After Instruction

If FLAG<1>

address

(FALSE)

;

if FLAG<1>

address

(TRUE)

1999 Microchip Technology Inc.

DS40139E-page 51

PIC12C5XX

CALL

Subroutine Call

Syntax:

[

label

] CALL k

Operands:

255

Operation:

(PC) + 1

Top of Stack;

PC<7:0>;

(STATUS<6:5>)

PC<10:9>;

PC<8>

Status Affected:

None

Encoding:

1001

kkkk

Description:

Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from STA-
TUS<6:5>, PC<8> is cleared.

CALL

a two cycle instruction.

Words:

Cycles:

Example:

HERE

CALL THERE

Before Instruction

PC =

address

(HERE)

After Instruction

PC =

address

(THERE)

TOS =

address

(HERE + 1)

CLRF

Clear f

Syntax:

[

label

] CLRF f

Operands:

Operation:

00h

(f);

Status Affected:

Encoding:

0000

011f

ffff

Description:

The contents of register 'f' are cleared
and the Z bit is set.

Words:

Cycles:

Example:

CLRF

FLAG_REG

Before Instruction

FLAG_REG

0x5A

After Instruction

FLAG_REG

0x00

CLRW

Clear W

Syntax:

[

label

] CLRW

Operands:

None

Operation:

00h

(W);

Status Affected:

Encoding:

0000

0100

0000

Description:

The W register is cleared. Zero bit (Z)
is set.

Words:

Cycles:

Example:

CLRW

Before Instruction

0x5A

After Instruction

0x00

CLRWDT

Clear Watchdog Timer

Syntax:

[

label

] CLRWDT

Operands:

None

Operation:

00h

WDT;

WDT prescaler (if assigned);

TO;

Status Affected:

TO, PD

Encoding:

0000

0100

Description:

The

CLRWDT

instruction resets the

WDT. It also resets the prescaler, if the
prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
set.

Words:

Cycles:

Example:

CLRWDT

Before Instruction

WDT counter =

After Instruction

WDT counter =

0x00

WDT prescale =

PIC12C5XX

DS40139E-page 52

1999 Microchip Technology Inc.

COMF

Complement f

Syntax:

[

label

] COMF f,d

Operands:

[0,1]

Operation:

(f)

(dest)

Status Affected:

Encoding:

0010

01df

ffff

Description:

The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
the W register. If 'd' is 1 the result is
stored back in register 'f'.

Words:

Cycles:

Example:

COMF

REG1,0

Before Instruction

REG1

0x13

After Instruction

REG1

0x13

0xEC

DECF

Decrement f

Syntax:

[

label

] DECF f,d

Operands:

[0,1]

Operation:

(f) 1

(dest)

Status Affected:

Encoding:

0000

11df

ffff

Description:

Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.

Words:

Cycles:

Example:

DECF CNT,

Before Instruction

CNT

0x01

After Instruction

CNT

0x00

DECFSZ

Decrement f, Skip if 0

Syntax:

[

label

] DECFSZ f,d

Operands:

[0,1]

Operation:

(f) 1

d; skip if result = 0

Status Affected:

None

Encoding:

0010

11df

ffff

Description:

The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.

If the result is 0, the next instruction,
which is already fetched, is discarded
and an NOP is executed instead mak-
ing it a two cycle instruction.

Words:

Cycles:

1(2)

Example:

HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE ·

Before Instruction

address

(HERE)

After Instruction

CNT

CNT - 1;

if CNT

address

(CONTINUE)

;

if CNT

address

(HERE+1)

GOTO

Unconditional Branch

Syntax:

[

label

] GOTO k

Operands:

511

Operation:

PC<8:0>;

STATUS<6:5>

PC<10:9>

Status Affected:

None

Encoding:

101k

kkkk

Description:

GOTO

is an unconditional branch. The

9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>.

GOTO

is a

two cycle instruction.

Words:

Cycles:

Example:

GOTO THERE

After Instruction

PC =

address

(THERE)

1999 Microchip Technology Inc.

DS40139E-page 53

PIC12C5XX

INCF

Increment f

Syntax:

[

label

] INCF f,d

Operands:

[0,1]

Operation:

(f) + 1

(dest)

Status Affected:

Encoding:

0010

10df

ffff

Description:

The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.

Words:

Cycles:

Example:

INCF

CNT,

Before Instruction

CNT

0xFF

After Instruction

CNT

0x00

INCFSZ

Increment f, Skip if 0

Syntax:

[

label

] INCFSZ f,d

Operands:

[0,1]

Operation:

(f) + 1

(dest), skip if result = 0

Status Affected:

None

Encoding:

0011

11df

ffff

Description:

The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.

If the result is 0, then the next instruc-
tion, which is already fetched, is dis-
carded and an NOP is executed
instead making it a two cycle instruc-
tion.

Words:

Cycles:

1(2)

Example:

HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE ·

Before Instruction

address

(HERE)

After Instruction

CNT

CNT + 1;

if CNT

address

(CONTINUE)

;

if CNT

address

(HERE +1)

IORLW

Inclusive OR literal with W

Syntax:

[

label

] IORLW k

Operands:

255

Operation:

(W) .OR. (k)

(W)

Status Affected:

Encoding:

1101

kkkk

Description:

The contents of the W register are
OR'ed with the eight bit literal 'k'. The
result is placed in the W register.

Words:

Cycles:

Example:

IORLW

0x35

Before Instruction

0x9A

After Instruction

0xBF

IORWF

Inclusive OR W with f

Syntax:

[

label

] IORWF f,d

Operands:

[0,1]

Operation:

(W).OR. (f)

(dest)

Status Affected:

Encoding:

0001

00df

ffff

Description:

Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.

Words:

Cycles:

Example:

IORWF

RESULT, 0

Before Instruction

RESULT =

0x13

0x91

After Instruction

RESULT =

0x13

0x93

1999 Microchip Technology Inc.

DS40139E-page 55

PIC12C5XX

OPTION

Load OPTION Register

Syntax:

[

label

] OPTION

Operands:

None

Operation:

(W)

OPTION

Status Affected:

None

Encoding:

0000

0010

Description:

The content of the W register is loaded
into the OPTION register.

Words:

Cycles:

Example

OPTION

Before Instruction

0x07

After Instruction

OPTION = 0x07

RETLW

Return with Literal in W

Syntax:

[

label

] RETLW k

Operands:

255

Operation:

(W);

TOS

Status Affected:

None

Encoding:

1000

kkkk

Description:

The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.

Words:

Cycles:

Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

· ;W now has table

· ;value.

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

RETLW kn ; End of table

Before Instruction

0x07

After Instruction

value of k8

RLF

Rotate Left f through Carry

Syntax:

[

label

] RLF f,d

Operands:

[0,1]

Operation:

See description below

Status Affected:

Encoding:

0011

01df

ffff

Description:

The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.

Words:

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

1110 0110

After Instruction

REG1

1110 0110

1100 1100

RRF

Rotate Right f through Carry

Syntax:

[

label

] RRF f,d

Operands:

[0,1]

Operation:

See description below

Status Affected:

Encoding:

0011

00df

ffff

Description:

The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.

Words:

Cycles:

Example:

RRF

REG1,0

Before Instruction

REG1

1110 0110

After Instruction

REG1

1110 0110

0111 0011

1999 Microchip Technology Inc.

DS40139E-page 57

PIC12C5XX

SWAPF

Swap Nibbles in f

Syntax:

[

label

] SWAPF f,d

Operands:

[0,1]

Operation:

(f<3:0>)

(dest<7:4>);

(f<7:4>)

(dest<3:0>)

Status Affected:

None

Encoding:

0011

10df

ffff

Description:

The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.

Words:

Cycles:

Example

SWAPF

REG1,

Before Instruction

REG1

0xA5

After Instruction

REG1

0xA5

0X5A

TRIS

Load TRIS Register

Syntax:

[

label

] TRIS

Operands:

f =

Operation:

(W)

TRIS register f

Status Affected:

None

Encoding:

0000

0fff

Description:

TRIS register 'f' (f = 6) is loaded with the
contents of the W register

Words:

Cycles:

Example

TRIS

GPIO

Before Instruction

0XA5

After Instruction

TRIS

0XA5

Note:

f = 6 for PIC12C5XX only.

XORLW

Exclusive OR literal with W

Syntax:

[

label

]

XORLW k

Operands:

255

Operation:

(W) .XOR. k

(

Status Affected:

Encoding:

1111

kkkk

Description:

The contents of the W register are
XOR'ed with the eight bit literal 'k'. The
result is placed in the W register.

Words:

Cycles:

Example:

XORLW

0xAF

Before Instruction

0xB5

After Instruction

0x1A

XORWF

Exclusive OR W with f

Syntax:

[

label

] XORWF f,d

Operands:

[0,1]

Operation:

(W) .XOR. (f)

(

dest)

Status Affected:

Encoding:

0001

10df

ffff

Description:

Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.

Words:

Cycles:

Example

XORWF

REG,1

Before Instruction

REG

0xAF

0xB5

After Instruction

REG

0x1A

0xB5

1999 Microchip Technology Inc.

DS40139E-page 59

PIC12C5XX

10.0

DEVELOPMENT SUPPORT

10.1

Development Tools

The PICmicro

microcontrollers are supported with a

full range of hardware and software development tools:

· MPLABTM-ICE

Real-Time In-Circuit Emulator

· ICEPIC

Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

· PRO MATE

II Universal Programmer

· PICSTART

Plus Entry-Level Prototype

Programmer

· SIMICE

· PICDEM-1 Low-Cost Demonstration Board

· PICDEM-2 Low-Cost Demonstration Board

· PICDEM-3 Low-Cost Demonstration Board

· MPASM Assembler

· MPLAB

SIM Software Simulator

· MPLAB-C17 (C Compiler)

· Fuzzy Logic Development System

(

fuzzy

TECH

MP)

· K

Evaluation Kits and Programmer

10.2

MPLAB-ICE: High Performance
Universal In-Circuit Emulator with
MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro

microcontrollers (MCUs). MPLAB-ICE is

supplied with the MPLAB Integrated Development
Environment (IDE), which allows editing, "make" and
download, and source debugging from a single envi-
ronment.

Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support all new Microchip micro-
controllers.

The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows

3.x or

Windows 95 environment were chosen to best make
these features available to you, the end user.

MPLAB-ICE is available in two versions.
MPLAB-ICE 1000 is a basic, low-cost emulator system
with simple trace capabilities. It shares processor mod-
ules with the MPLAB-ICE 2000. This is a full-featured
emulator system with enhanced trace, trigger, and data
monitoring features. Both systems will operate across
the entire operating speed range of the PICmicro

MCU.

10.3

ICEPIC: Low-Cost PICmicro

In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible
machines ranging from 386 through Pentium

based

machines under Windows 3.x, Windows 95, or Win-
dows NT environment. ICEPIC features real time, non-
intrusive emulation.

10.4

PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.

The PRO MATE II has programmable V

and V

supplies which allows it to verify programmed memory
at V

min and V

max for maximum reliability. It has

an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
gram PIC12CXXX, PIC14C000, PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.

10.5

PICSTART Plus Entry Level
Development System

The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is not
recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.

PIC12C5XX

DS40139E-page 60

1999 Microchip Technology Inc.

10.6

SIMICE Entry-Level Hardware
Simulator

SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip's simulator MPLABTM-SIM. Both SIM-
ICE and MPLAB-SIM run under Microchip Technol-
ogy's MPLAB Integrated Development Environment
(IDE) software. Specifically, SIMICE provides hardware
simulation for Microchip's PIC12C5XX, PIC12CE5XX,
and PIC16C5X families of PICmicro

8-bit microcon-

trollers. SIMICE works in conjunction with MPLAB-SIM
to provide non-real-time I/O port emulation. SIMICE
enables a developer to run simulator code for driving
the target system. In addition, the target system can
provide input to the simulator code. This capability
allows for simple and interactive debugging without
having to manually generate MPLAB-SIM stimulus
files. SIMICE is a valuable debugging tool for entry-
level system development.

10.7

PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip's microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.

10.8

PICDEM-2 Low-Cost PIC16CXX
Demonstration Board

The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I

C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.9

PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board

The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.

1999 Microchip Technology Inc.

DS40139E-page 61

PIC12C5XX

10.10

MPLAB Integrated Development
Environment Software

The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:

· A full featured editor
· Three operating modes

- editor
- emulator
- simulator

· A project manager
· Customizable tool bar and key mapping
· A status bar with project information
· Extensive on-line help

MPLAB allows you to:

· Edit your source files (either assembly or `C')
· One touch assemble (or compile) and download

to PICmicro

tools (automatically updates all

project information)

· Debug using:

- source files
- absolute listing file

The ability to use MPLAB with Microchip's simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.

10.11

Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.

MPASM allows full symbolic debugging from MPLAB-
ICE, Microchip's Universal Emulator System.

MPASM has the following features to assist in develop-
ing software for specific use applications.

· Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

· Macro assembly capability.

· Produces all the files (Object, Listing, Symbol, and

special) required for symbolic debug with
Microchip's emulator systems.

· Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support
programming of the PICmicro

. Directives are helpful

in making the development of your assemble source
code shorter and more maintainable.

10.12

Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro

series microcontrollers

on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.

MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPASM. The Software Simulator
offers the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.

10.13

MPLAB-C17 Compiler

The MPLAB-C17 Code Development System is a
complete ANSI `C' compiler and integrated develop-
ment environment for Microchip's PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.

For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.

10.14

Fuzzy Logic Development System
(

fuzzyTECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version,

fuzzy

TECH-MP, Edition for imple-

menting more complex systems.

Both versions include Microchip's

fuzzy

LAB

demon-

stration board for hands-on experience with fuzzy logic
systems implementation.

10.15

SEEVAL

Evaluation and

Programming System

The SEEVAL SEEPROM Designer's Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials

and secure serials.

The Total Endurance

Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.

1999 Microchip Technology Inc.

DS40139E-page 63

PIC12C5XX

TABLE 10-1:

DEVELOPMENT TOOLS FROM MICROCHIP

PIC

000

PIC

16C

PIC

16C

I
C1

7XX

I
C1

I
C

17C

PIC

17C

200

300

301

ulat

or Prod

ucts

TM-I

I
C

Low

-C

ost

I
n

-C

ircu

it E

l
at

ftwar

e Tools

t
e

l
o

r
o

i
l
e

f
u

-M

l
ore

r
/E

diti

i
c

.
To

t
a

l
En

r
a

f
t
w

Pro

gra

mmer

I
CS

ers

v. K

i
t

O M

i
v

r
sa

r
a

mme

r
a

mme

mo Bo

ards

r
s K

i
t

I
C

-
1

-
2

-
3

l
ua

tion

Kit

r
an

ond

er K

i
t

1999 Microchip Technology Inc.

DS40139E-page 65

PIC12C5XX

11.0

ELECTRICAL CHARACTERISTICS - PIC12C508/PIC12C509

Absolute Maximum Ratings

Ambient Temperature under bias ........................................................................................................... 40°C to +125°C

Storage Temperature ............................................................................................................................. 65°C to +150°C

Voltage on V

with respect to V

.................................................................................................................0 to +7.5 V

Voltage on MCLR with respect to V

...............................................................................................................0 to +14 V

Voltage on all other pins with respect to V

............................................................................... 0.6 V to (V

+ 0.6 V)

Total Power Dissipation

(1)

.................................................................................................................................... 700 mW

Max. Current out of V

pin .................................................................................................................................. 200 mA

Max. Current into V

pin ..................................................................................................................................... 150 mA

Input Clamp Current, I

< 0 or V

> V

)

.................................................................................................................... ±

20 mA

Output Clamp Current, I

< 0 or V

> V

)

............................................................................................................. ±

20 mA

Max. Output Current sunk by any I/O pin ................................................................................................................ 25 mA

Max. Output Current sourced by any I/O pin........................................................................................................... 25 mA

Max. Output Current sourced by I/O port (GPIO) ................................................................................................. 100 mA

Max. Output Current sunk by I/O port (GPIO )...................................................................................................... 100 mA

Note 1: Power Dissipation is calculated as follows: P

DIS

= V

x {I

} +

{(V

-V

) x I

} +

x I

)

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC12C5XX

DS40139E-page 66

1999 Microchip Technology Inc.

11.1

DC CHARACTERISTICS:

PIC12C508/509 (Commercial, Industrial, Extended)

DC Characteristics
Power Supply Pins

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial)

+85

C (industrial)

+125

C (extended)

Parm

No.

Characteristic

Sym

Min

Typ

(1)

Max

Units

Conditions

D001

Supply Voltage

2.5

3.0

5.5

OSC

= DC to 4 MHz (Commercial/

Industrial)
F

OSC

= DC to 4 MHz (Extended)

D002

RAM Data Retention

Voltage

(2)

1.5*

Device in SLEEP mode

D003

Start Voltage to

ensure Power-on Reset

POR

See section on Power-on Reset for details

D004

Rise Rate to ensure

Power-on Reset

VDD

0.05

V/ms

See section on Power-on Reset for details

D010

D010C

D010A

Supply Current

(3)

.78

1.1

2.4

µA

XT and EXTRC options

(4)

OSC

= 4 MHz, V

= 5.5V

INTRC Option
F

OSC

= 4 MHz, V

= 5.5V

LP O

PTION

, Commercial Temperature

OSC

= 32 kHz, V

= 3.0V, WDT disabled

LP O

PTION

, Industrial Temperature

OSC

= 32 kHz, V

= 3.0V, WDT disabled

LP O

PTION

, Extended Temperature

OSC

= 32 kHz, V

= 3.0V, WDT disabled

D020
D021
D021B

Power-Down Current

(5)

--
--
--

0.25
0.25

4
5

= 3.0V, Commercial WDT disabled

= 3.0V, Industrial WDT disabled

= 3.0V, Extended WDT disabled

D022

WDT

--
--
--

3.75
3.75
3.75

8
9

= 3.0V, Commercial

= 3.0V, Industrial

= 3.0V, Extended

* These parameters are characterized but not tested.

Note 1: Data in the Typical ("Typ") column is based on characterization results at 25

C. This data is for design

guidance only and is not tested.

2: This is the limit to which V

can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as

bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an
impact on the current consumption.

a) The test conditions for all I

measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
V

, T0CKI = V

, MCLR = V

; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

= V

/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current

is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

1999 Microchip Technology Inc.

DS40139E-page 67

PIC12C5XX

11.2

DC CHARACTERISTICS:

PIC12C508/509 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)
Operating temperature

0°C

+70°C (commercial)

40°C

+85°C (industrial)

40°C

+125°C (extended)

Operating voltage V

range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage
I/O ports

D030

with TTL buffer

0.8V

4.5

5.5V

0.15V

otherwise

D031

with Schmitt Trigger buffer

0.15V

D032

MCLR, GP2/T0CKI (in EXTRC mode)

0.15V

D033

OSC1 (EXTRC)

(1)

0.15V

D033

OSC1 (in XT and LP)

0.3V

Note1

Input High Voltage
I/O ports

D040

with TTL buffer

2.0V

4.5

5.5V

D040A

0.25V

0.8V

otherwise

D041

with Schmitt Trigger buffer

0.85V

For entire V

range

D042

MCLR/GP2/T0CKI

0.85V

D042A OSC1 (XT and LP)

0.7V

Note1

D043

OSC1 (in EXTRC mode)

0.85V

D070

GPIO weak pull-up current

PUR

250

400

= 5V, V

= V

Input Leakage Current

(2, 3)

For V

5.5V

D060

I/O ports

-1

0.5

Vss

Pin at hi-impedance

D061

MCLR, GP2/T0CKI

130

0.5

250

= V

+ 0.25V

(2)

= V

D063

OSC1

-3

0.5

Vss

XT and LP options

Output Low Voltage

D080

I/O ports/CLKOUT

0.6

= 8.7 mA, V

= 4.5V

Output High Voltage

D090

I/O ports/CLKOUT

(3)

- 0.7

= -5.4 mA, V

= 4.5V

Capacitive Loading Specs on
Output Pins

D100

OSC2 pin

OSC2

In XT and LP modes when
external clock is used to drive
OSC1.

D101

All I/O pins

Data in "Typ" column is at 5V, 25

C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C5XX be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

PIC12C5XX

DS40139E-page 70

1999 Microchip Technology Inc.

11.4

Timing Diagrams and Specifications

FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12C508/C509

TABLE 11-2:

EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509

AC Characteristics

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial),

+85

C (industrial),

+125

C (extended)

Operating Voltage V

range is described in Section 11.1

Parameter

No.

Sym

Characteristic

Min

Typ

(1)

Max

Units

Conditions

OSC

External CLKIN Frequency

(2)

MHz

XT osc mode

200

kHz

LP osc mode

Oscillator Frequency

(2)

0.1

MHz

XT osc mode

200

kHz

LP osc mode

OSC

External CLKIN Period

(2)

250

EXTRC osc mode

250

XT osc mode

LP osc mode

Oscillator Period

(2)

250

EXTRC osc mode

250

10,000

XT osc mode

LP osc mode

Tcy

Instruction Cycle Time

(3)

4/F

OSC

TosL, TosH Clock in (OSC1) Low or High Time

50*

XT oscillator

LP oscillator

TosR, TosF Clock in (OSC1) Rise or Fall Time

25*

XT oscillator

50*

LP oscillator

* These parameters are characterized but not tested.

Note 1: Data in the Typical ("Typ") column is at 5V, 25

C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.

3: Instruction cycle period (T

) equals four times the input oscillator time base period.

OSC1

PIC12C5XX

DS40139E-page 72

1999 Microchip Technology Inc.

TABLE 11-4:

TIMING REQUIREMENTS - PIC12C508/C509

FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509

AC Characteristics

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial)

+85

C (industrial)

+125

C (extended)

Operating Voltage V

range is described in Section 11.1

Parameter

No.

Sym

Characteristic

Min

Typ

(1)

Max

Units

TosH2ioV

OSC1

(Q1 cycle) to Port out valid

(3)

100*

TosH2ioI

OSC1

(Q2 cycle) to Port input invalid

(I/O in hold time)

TBD

TioV2osH

Port input valid to OSC1

(I/O in setup time)

TBD

TioR

Port output rise time

(2, 3)

25**

TioF

Port output fall time

(2, 3)

25**

* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical ("Typ") column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.
3: See Figure 11-1 for loading conditions.

MCLR

Internal

POR

DRT

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

(Note 2)

2: Runs in MCLR or WDT reset only in XT and LP modes.

1999 Microchip Technology Inc.

DS40139E-page 79

PIC12C5XX

13.0

ELECTRICAL CHARACTERISTICS - PIC12C508A/PIC12C509A/
PIC12LC508A/PIC12LC509A/PIC12CR509A/PIC12CE518/PIC12CE519/
PIC12LCE518/PIC12LCE519/PIC12LCR509A

Absolute Maximum Ratings

Ambient Temperature under bias ........................................................................................................... 40°C to +125°C

Storage Temperature ............................................................................................................................. 65°C to +150°C

Voltage on V

with respect to V

.................................................................................................................0 to +7.0 V

Voltage on MCLR with respect to V

...............................................................................................................0 to +14 V

Voltage on all other pins with respect to V

............................................................................... 0.3 V to (V

+ 0.3 V)

Total Power Dissipation

(1)

.................................................................................................................................... 700 mW

Max. Current out of V

pin .................................................................................................................................. 200 mA

Max. Current into V

pin ..................................................................................................................................... 150 mA

Input Clamp Current, I

< 0 or V

> V

)

.................................................................................................................... ±

20 mA

Output Clamp Current, I

< 0 or V

> V

)

............................................................................................................. ±

20 mA

Max. Output Current sunk by any I/O pin ................................................................................................................ 25 mA

Max. Output Current sourced by any I/O pin........................................................................................................... 25 mA

Max. Output Current sourced by I/O port (GPIO) ................................................................................................. 100 mA

Max. Output Current sunk by I/O port (GPIO )...................................................................................................... 100 mA

Note 1: Power Dissipation is calculated as follows: P

DIS

= V

x {I

} +

{(V

-V

) x I

} +

x I

)

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

PIC12C5XX

DS40139E-page 80

1999 Microchip Technology Inc.

13.1

DC CHARACTERISTICS:

PIC12C508A/509A (Commercial, Industrial, Extended)
PIC12CE518/519 (Commercial, Industrial, Extended)
PIC12CR509A (Commercial, Industrial, Extended)

DC Characteristics
Power Supply Pins

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial)

+85

C (industrial)

+125

C (extended)

Parm

No.

Characteristic

Sym

Min

Typ

(1)

Max

Units

Conditions

D001

Supply Voltage

3.0

5.5

OSC

= DC to 4 MHz (Commercial/

Industrial, Extended)

D002

RAM Data Retention

Voltage

(2)

1.5*

Device in SLEEP mode

D003

Start Voltage to ensure

Power-on Reset

POR

See section on Power-on Reset for details

D004

Rise Rate to ensure

Power-on Reset

VDD

0.05*

V/ms

See section on Power-on Reset for details

D010

D010C

D010A

Supply Current

(3)

0.8

1.4

µA

XT and EXTRC options (Note 4)
F

OSC

= 4 MHz, V

= 5.5V

INTRC Option
F

OSC

= 4 MHz, V

= 5.5V

LP O

PTION

, Commercial Temperature

OSC

= 32 kHz, V

= 3.0V, WDT disabled

LP O

PTION

, Industrial Temperature

OSC

= 32 kHz, V

= 3.0V, WDT disabled

LP O

PTION

, Extended Temperature

OSC

= 32 kHz, V

= 3.0V, WDT disabled

D020
D021
D021B

Power-Down Current

(5)

--
--
--

0.25
0.25

4
5

= 3.0V, Commercial WDT disabled

= 3.0V, Industrial WDT disabled

= 3.0V, Extended WDT disabled

D022

Power-Down Current

WDT

--
--
--

2.2
2.2

5
6

= 3.0V, Commercial

= 3.0V, Industrial

= 3.0V, Extended

Supply Current

(3)

During read/write to
EEPROM peripheral

0.1

0.2

FOSC = 4 MHz, Vdd = 5.5V,
SCL = 400kHz

* These parameters are characterized but not tested.

Note 1: Data in the Typical ("Typ") column is based on characterization results at 25

C. This data is for design guid-

ance only and is not tested.

2: This is the limit to which V

can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the
current consumption.

a) The test conditions for all I

measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
V

, T0CKI = V

, MCLR = V

; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

= V

/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

or V

1999 Microchip Technology Inc.

DS40139E-page 81

PIC12C5XX

13.2

DC CHARACTERISTICS:

PIC12LC508A/509A (Commercial, Industrial)
PIC12LCE518/519 (Commercial, Industrial)
PIC12LCR509A (Commercial, Industrial)

DC Characteristics
Power Supply Pins

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial)

+85

C (industrial)

Parm

No.

Characteristic

Sym

Min Typ

(1)

Max

Units

Conditions

D001

Supply Voltage

2.5

5.5

OSC

= DC to 4 MHz (Commercial/

Industrial)

D002

RAM Data Retention

Voltage

(2)

1.5*

Device in SLEEP mode

D003

Start Voltage to ensure

Power-on Reset

POR

See section on Power-on Reset for details

D004

Rise Rate to ensure

Power-on Reset

VDD

0.05*

V/ms

See section on Power-on Reset for details

D010

D010C

D010A

Supply Current

(3)

0.4

0.8

XT and EXTRC options (Note 4)
F

OSC

= 4 MHz, V

= 2.5V

INTRC Option
F

OSC

= 4 MHz, V

= 2.5V

LP O

PTION

, Commercial Temperature

OSC

= 32 kHz, V

= 2.5V, WDT disabled

LP O

PTION

, Industrial Temperature

OSC

= 32 kHz, V

= 2.5V, WDT disabled

D020
D021
D021B

Power-Down Current

(5)

--
--

0.2
0.2

3
4

= 2.5V, Commercial

= 2.5V, Industrial

WDT

2.0
2.0

4
5

mA
mA

= 2.5V, Commercial

= 2.5V, Industrial

* These parameters are characterized but not tested.

Note 1: Data in the Typical ("Typ") column is based on characterization results at 25

C. This data is for design

guidance only and is not tested.

2: This is the limit to which V

can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as

bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an
impact on the current consumption.

a) The test conditions for all I

measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
V

, T0CKI = V

, MCLR = V

; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

= V

/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current

is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

PIC12C5XX

DS40139E-page 82

1999 Microchip Technology Inc.

13.3

DC CHARACTERISTICS:

PIC12C508A/509A (Commercial, Industrial, Extended)
PIC12C518/519 (Commercial, Industrial, Extended)
PIC12CR509A (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)
Operating temperature

0°C

+70°C (commercial)

40°C

+85°C (industrial)

40°C

+125°C (extended)

Operating voltage V

range as described in DC spec Section 13.1 and

Section 13.2.

Param

No.

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage
I/O ports

D030

with TTL buffer

0.8V

For 4.5V

5.5V

0.15V

otherwise

D031

with Schmitt Trigger buffer

0.2V

D032

MCLR, GP2/T0CKI (in EXTRC mode)

0.2V

D033

OSC1 (in EXTRC mode)

0.2V

Note 1

D033

OSC1 (in XT and LP)

0.3V

Note 1

Input High Voltage
I/O ports

D040

with TTL buffer

0.25V

0.8V

4.5V

5.5V

D040A

2.0V

otherwise

D041

with Schmitt Trigger buffer

0.8V

For entire V

range

D042

MCLR, GP2/T0CKI

0.8V

D042A OSC1 (XT and LP)

0.7V

Note 1

D043

OSC1 (in EXTRC mode)

0.9V

D070

GPIO weak pull-up current (Note 4)

PUR

250

400

= 5V, V

= V

MCLR pull-up current

= 5V, V

= V

Input Leakage Current (Notes 2, 3)

D060

I/O ports

Vss

, Pin at hi-

impedance

D061

T0CKI

Vss

D063

OSC1

Vss

, XT and LP osc

configuration

Output Low Voltage

D080

I/O ports

0.6

= 8.5 mA, V

= 4.5V,

C to +85

D080A

0.6

= 7.0 mA, V

= 4.5V,

C to +125

Output High Voltage

D090

I/O ports (Note 3)

- 0.7

= -3.0 mA, V

= 4.5V,

C to +85

D090A

- 0.7

= -2.5 mA, V

= 4.5V,

C to +125

Capacitive Loading Specs on
Output Pins

D100

OSC2 pin

COSC2

In XT and LP modes when exter-
nal clock is used to drive OSC1.

D101

All I/O pins

Data in "Typ" column is at 5V, 25

C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12C5XX be driven with external clock in RC mode.

The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.

Negative current is defined as coming out of the pin.

This spec. applies when GP3/MCLR is configured as MCLR. The leakage current of the MCLR circuit is higher than the
standard I/O logic.

1999 Microchip Technology Inc.

DS40139E-page 83

PIC12C5XX

13.4

DC CHARACTERISTICS:

PIC12LC508A/509A (Commercial, Industrial)
PIC12LC518/519 (Commercial, Industrial)
PIC12LCR509A (Commercial, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)
Operating temperature

0°C

+70°C (commercial)

40°C

+85°C (industrial)

Operating voltage V

range as described in DC spec Section 13.1 and

Section 13.2.

Param

No.

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage
I/O ports

D030

with TTL buffer

0.8V

For 4.5V

5.5V

0.15V

otherwise

D031

with Schmitt Trigger buffer

0.2V

D032

MCLR, GP2/T0CKI (in EXTRC mode)

0.2V

D033

OSC1 (in EXTRC mode)

0.2V

Note 1

D033

OSC1 (in XT and LP)

0.3V

Note 1

Input High Voltage
I/O ports

D040

with TTL buffer

0.25V

0.8V

4.5V

5.5V

D040A

2.0V

otherwise

D041

with Schmitt Trigger buffer

0.8V

For entire V

range

D042

MCLR, GP2/T0CKI

0.8V

D042A

OSC1 (XT and LP)

0.7V

Note 1

D043

OSC1 (in EXTRC mode)

0.9V

D070

GPIO weak pull-up current (Note 4)

PUR

250

400

= 5V, V

= V

MCLR pull-up current

= 5V, V

= V

Input Leakage Current (Notes 2, 3)

D060

I/O ports

Vss

, Pin at hi-imped-

ance

D061

T0CKI

Vss

D063

OSC1

Vss

, XT and LP osc

configuration

Output Low Voltage

D080

I/O ports

0.6

= 8.5 mA, V

= 4.5V,

C to +85

D080A

0.6

= 7.0 mA, V

= 4.5V,

C to +125

Output High Voltage

D090

I/O ports (Note 3)

- 0.7

= -3.0 mA, V

= 4.5V,

C to +85

D090A

- 0.7

= -2.5 mA, V

= 4.5V,

C to +125

Capacitive Loading Specs on
Output Pins

D100

OSC2 pin

COSC

In XT and LP modes when exter-
nal clock is used to drive OSC1.

D101

All I/O pins

Data in "Typ" column is at 5V, 25

C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12C5XX be driven with external clock in RC mode.

Negative current is defined as coming out of the pin.

This spec. applies when GP3/MCLR is configured as MCLR. The leakage current of the MCLR circuit is higher than the
standard I/O logic.

PIC12C5XX

DS40139E-page 86

1999 Microchip Technology Inc.

13.6

Timing Diagrams and Specifications

FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC12C508A, PIC12C509A, PIC12CR509A,

PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A,
PIC12LCE518 and PIC12LCE519

TABLE 13-2:

EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508A, PIC12C509A,
PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A,
PIC12LCE518 and PIC12LCE519

AC Characteristics

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial),

+85

C (industrial),

+125

C (extended)

Operating Voltage V

range is described in Section 13.1

Parameter

No.

Sym

Characteristic

Min

Typ

(1)

Max

Units

Conditions

OSC

External CLKIN Frequency

(2)

MHz

XT osc mode

200

kHz

LP osc mode

Oscillator Frequency

(2)

MHz

EXTRC osc mode

0.1

MHz

XT osc mode

200

kHz

LP osc mode

OSC

External CLKIN Period

(2)

250

XT osc mode

LP osc mode

Oscillator Period

(2)

250

EXTRC osc mode

250

10,000

XT osc mode

LP osc mode

Tcy

Instruction Cycle Time

(3)

4/F

OSC

TosL, TosH Clock in (OSC1) Low or High Time

50*

XT oscillator

LP oscillator

TosR, TosF Clock in (OSC1) Rise or Fall Time

25*

XT oscillator

50*

LP oscillator

* These parameters are characterized but not tested.

Note 1: Data in the Typical ("Typ") column is at 5V, 25

C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard oper-

3: Instruction cycle period (T

) equals four times the input oscillator time base period.

OSC1

PIC12C5XX

DS40139E-page 88

1999 Microchip Technology Inc.

FIGURE 13-3: I/O TIMING - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A,

PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

TABLE 13-4:

TIMING REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519,
PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial)

+85

C (industrial)

+125

C (extended)

Operating Voltage V

range is described in Section 13.1

Parameter

No.

Sym

Characteristic

Min

Typ

(1)

Max

Units

TosH2ioV

OSC1

(Q1 cycle) to Port out valid

(3)

100*

TosH2ioI

OSC1

(Q2 cycle) to Port input invalid

(I/O in hold time)

TBD

TioV2osH

Port input valid to OSC1

(I/O in setup time)

TBD

TioR

Port output rise time

(2, 3)

25**

TioF

Port output fall time

(2, 3)

25**

* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical ("Typ") column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.
3: See Figure 13-1 for loading conditions.

OSC1

I/O Pin

(input)

I/O Pin

(output)

20, 21

Old Value

New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

1999 Microchip Technology Inc.

DS40139E-page 89

PIC12C5XX

FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -

PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A,
PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

TABLE 13-5:

RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508A,
PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A,
PIC12LCR509A, PIC12LCE518 and PIC12LCE519

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature

+70

C (commercial)

+85

C (industrial)

+125

C (extended)

Operating Voltage V

range is described in Section 13.1

Parameter

No.

Sym

Characteristic

Min

Typ

(1)

Max

Units

Conditions

TmcL

MCLR Pulse Width (low)

2000*

= 5 V

Twdt

Watchdog Timer Time-out Period
(No Prescaler)

18*

30*

= 5 V (Commercial)

DRT

Device Reset Timer Period

(2)

18*

30*

= 5 V (Commercial)

Tio

I/O Hi-impedance from MCLR Low

2000*

* These parameters are characterized but not tested.

Note 1: Data in the Typical ("Typ") column is at 5V, 25

C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 2: See Table 13-6.

MCLR

Internal

POR

DRT

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

(Note 2)

2: Runs in MCLR or WDT reset only in XT and LP modes.

PIC12C5XX

DS40139E-page 90

1999 Microchip Technology Inc.

TABLE 13-6:

DRT (DEVICE RESET TIMER PERIOD) - PIC12C508A, PIC12C509A, PIC12CE518,
PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and
PIC12LCE519

FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519,

PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519

TABLE 13-7:

TIMER0 CLOCK REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518,
PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and
PIC12LCE519

Oscillator Configuration

POR Reset

Subsequent Resets

IntRC & ExtRC

18 ms (typical)

(1)

300 µs (typical)

(1)

XT & LP

18 ms (typical)

(1)

18 ms (typical)

(1)

Note 1:

Data in the Typical ("Typ") column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

AC Characteristics

Standard Operating Conditions (unless otherwise specified)
Operating Temperature

+70

C (commercial)

+85

C (industrial)

+125

C (extended)

Operating Voltage V

range is described in Section 13.1.

Parameter

No.

Sym Characteristic

Min

Typ

(1)

Max Units Conditions

Tt0H

T0CKI High Pulse Width - No Prescaler

0.5 T

+ 20*

- With Prescaler

10*

Tt0L

T0CKI Low Pulse Width - No Prescaler

0.5 T

+ 20*

- With Prescaler

10*

Tt0P

T0CKI Period

20 or T

+ 40*

Whichever is greater.
N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

Note 1:

Data in the Typical ("Typ") column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

T0CKI

1999 Microchip Technology Inc.

DS40139E-page 91

PIC12C5XX

TABLE 13-8:

EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX

ONLY

AC Characteristics

Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0

+70

C, Vcc = 3.0V to 5.5V (commercial)

+85

C, Vcc = 3.0V to 5.5V (industrial)

+125

C, Vcc = 4.5V to 5.5V (extended)

Operating Voltage V

range is described in Section 13.1

Parameter

Symbol

Min

Max

Units

Conditions

Clock frequency

CLK

--
--
--

100
100
400

kHz

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

Clock high time

HIGH

4000
4000

600

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

Clock low time

LOW

4700
4700
1300

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

SDA and SCL rise time
(Note 1)

--
--
--

1000
1000

300

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

SDA and SCL fall time

300

(Note 1)

START condition hold time

STA

4000
4000

600

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

START condition setup time

STA

4700
4700

600

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

Data input hold time

DAT

(Note 2)

Data input setup time

DAT

250
250
100

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

STOP condition setup time

STO

4000
4000

600

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

Output valid from clock
(Note 2)

--
--
--

3500
3500

900

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

Bus free time: Time the bus must
be free before a new transmis-
sion can start

BUF

4700
4700
1300

--
--
--

4.5V

Vcc

5.5V (E Temp range)

3.0V

Vcc

4.5V

Vcc

5.5V

Output fall time from V

minimum to V

maximum

20+0.1

250

(Note 1), CB

100 pF

Input filter spike suppression
(SDA and SCL pins)

(Notes 1, 3)

Write cycle time

Endurance

cycles

C, V

= 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on Microchip's website.

1999 Microchip Technology Inc.

DS40139E-page 105

PIC12C5XX

INDEX

ALU ....................................................................................... 9
Applications........................................................................... 4
Architectural Overview .......................................................... 9
Assembler

MPASM Assembler..................................................... 61

Block Diagram

On-Chip Reset Circuit ................................................. 41
Timer0......................................................................... 25
TMR0/WDT Prescaler ................................................. 28
Watchdog Timer.......................................................... 43

Brown-Out Protection Circuit .............................................. 44

CAL0 bit .............................................................................. 18
CAL1 bit .............................................................................. 18
CAL2 bit .............................................................................. 18
CAL3 bit .............................................................................. 18
CALFST bit ......................................................................... 18
CALSLW bit ........................................................................ 18
Carry ..................................................................................... 9
Clocking Scheme ................................................................ 12
Code Protection ............................................................ 35, 45
Configuration Bits................................................................ 35
Configuration Word ............................................................. 35

DC and AC Characteristics ........................................... 75, 93
Development Support ......................................................... 59
Development Tools ............................................................. 59
Device Varieties .................................................................... 7
Digit Carry ............................................................................. 9

EEPROM Peripheral Operation .......................................... 29
Errata .................................................................................... 3

Family of Devices.................................................................. 5
Features ................................................................................ 1
FSR ..................................................................................... 20
Fuzzy Logic Dev. System (

fuzzyTECH

-MP) .................... 61

I/O Interfacing ..................................................................... 21
I/O Ports .............................................................................. 21
I/O Programming Considerations........................................ 22
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 59
ID Locations .................................................................. 35, 45
INDF.................................................................................... 20
Indirect Data Addressing..................................................... 20
Instruction Cycle ................................................................. 12
Instruction Flow/Pipelining .................................................. 12
Instruction Set Summary..................................................... 48

KeeLoq

Evaluation and Programming Tools.................... 62

Loading of PC ..................................................................... 19

Memory Organization.......................................................... 13

Data Memory .............................................................. 14
Program Memory ........................................................ 13

MPLAB Integrated Development Environment Software .... 61

OPTION Register................................................................ 17
OSC selection..................................................................... 35
OSCCAL Register............................................................... 18
Oscillator Configurations..................................................... 36
Oscillator Types

HS............................................................................... 36
LP ............................................................................... 36
RC .............................................................................. 36
XT ............................................................................... 36

Package Marking Information............................................. 99
Packaging Information........................................................ 99
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 60
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 60
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 60
PICSTART

Plus Entry Level Development System ......... 59

POR

Device Reset Timer (DRT) ................................... 35, 42
PD............................................................................... 44
Power-On Reset (POR).............................................. 35
TO............................................................................... 44

PORTA ............................................................................... 21
Power-Down Mode ............................................................. 45
Prescaler ............................................................................ 28
PRO MATE

II Universal Programmer .............................. 59

Program Counter ................................................................ 19

Q cycles .............................................................................. 12

RC Oscillator....................................................................... 37
Read Modify Write .............................................................. 22
Register File Map................................................................ 14
Registers

Special Function ......................................................... 15

Reset .................................................................................. 35
Reset on Brown-Out ........................................................... 44

SEEVAL

Evaluation and Programming System .............. 61

SLEEP .......................................................................... 35, 45
Software Simulator (MPLAB-SIM) ...................................... 61
Special Features of the CPU .............................................. 35
Special Function Registers ................................................. 15
Stack................................................................................... 19
STATUS ............................................................................... 9
STATUS Register ............................................................... 16

Timer0

Switching Prescaler Assignment ................................ 28
Timer0 ........................................................................ 25
Timer0 (TMR0) Module .............................................. 25
TMR0 with External Clock .......................................... 27

Timing Diagrams and Specifications ............................ 70, 86
Timing Parameter Symbology and Load Conditions .... 69, 85
TRIS Registers ................................................................... 21

Wake-up from SLEEP......................................................... 45
Watchdog Timer (WDT)................................................ 35, 42

Period ......................................................................... 43
Programming Considerations ..................................... 43

WWW, On-Line Support ....................................................... 3

Zero bit ................................................................................. 9

1999 Microchip Technology Inc.

DS40139E-page 107

PIC12C5XX

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-602-786-7302 for the rest of the world.

Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

FlexROM, MPLAB and fuzzy-

LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.

All other trademarks mentioned herein are the property of
their respective companies.

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.

The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your
favorite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-
vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:

· Latest Microchip Press Releases

· Technical Support Section with Frequently Asked

Questions

· Design Tips

· Device Errata

· Job Postings

· Microchip Consultant Program Member Listing

· Links to other useful web sites related to

Microchip Products

· Conferences for products, Development Sys-

tems, technical information and more

· Listing of seminars and events

981103

1999 Microchip Technology Inc.

DS40139E-page 109

PIC12C5XX

PIC12C5XX Product Identification System

Please contact your local sales office for exact ordering procedures.

Sales and Support:

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Pattern:

Special Requirements

Package:

= 150 mil SOIC

= 208 mil SOIC

= 300 mil PDIP

= 300 mil Windowed Ceramic Side Brazed

Temperature
Range:

= 0

C to +70

= -40

C to +85

= -40

C to +125

Frequency
Range:

= 4 MHz

Device

PIC12C508
PIC12C509
PIC12C508T (Tape & reel for SOIC only)
PIC12C509T (Tape & reel for SOIC only)
PIC12C508A
PIC12C509A
PIC12C508AT (Tape & reel for SOIC only)
PIC12C509AT (Tape & reel for SOIC only)
PIC12LC508A
PIC12LC509A
PIC12LC508AT (Tape & reel for SOIC only)
PIC12LC509AT (Tape & reel for SOIC only)
PIC12CR509A
PIC12CR509AT (Tape & reel for SOIC only)
PIC12LCR509A
PIC12LCR509AT (Tape & reel for SOIC only)
PIC12CE518
PIC12CE518T (Tape & reel for SOIC only)
PIC12CE519
PIC12CE519T (Tape & reel for SOIC only)
PIC12LCE518
PIC12LCE518T (Tape & reel for SOIC only)
PIC12LCE519
PIC12LCE519T (Tape & reel for SOIC only)

PART NO. -XX X /XX XXX

Examples

PIC12C508A-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal V

limits

PIC12C508A-04I/SM
Industrial Temp., SOIC
package, 4 MHz, normal
V

limits

PIC12C509-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal V

limits

2002 Microchip Technology Inc.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip's products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,
K

, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company's quality system processes and
procedures are QS-9000 compliant for its
PICmicro

8-bit MCUs, K

code hopping

devices, Serial EEPROMs and microperipheral
products. In addition, Microchip's quality
system for the design and manufacture of
development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro

MCUs.

The PICmicro family meets the specifications contained in the Microchip Data Sheet.

Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable".

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

2002 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com

Rocky Mountain

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Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456

Atlanta

500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307

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Westford, MA 01886
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Chicago

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Tel: 630-285-0071 Fax: 630-285-0075

Dallas

4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924

Detroit

Tri-Atria Office Building
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Tel: 248-538-2250 Fax: 248-538-2260

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2767 S. Albright Road
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Tel: 765-864-8360 Fax: 765-864-8387

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Tel: 949-263-1888 Fax: 949-263-1338

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Tel: 408-436-7950 Fax: 408-436-7955

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Tel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFIC

Australia

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Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

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Rm. 2401, 24th Floor,
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Tel: 86-28-6766200 Fax: 86-28-6766599

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EUROPE

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Tel: 44 118 921 5869 Fax: 44-118 921-5820

01/18/02

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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PIC12CE518-04I/SM

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PIC12CE518-04I/SM