Document Outline

• Special Microcontroller Features:
• Flexible Oscillator Structure:
• Peripheral Highlights:
• External Memory Bus (PIC18F8XJ10/8XJ15 only):
• Pin Diagrams
• Pin Diagrams (Continued)
• Table of Contents
• 1.0 Device Overview
  • 1.1 Core Features
    • 1.1.1 nanoWatt Technology
    • 1.1.2 Oscillator Options and Features
    • 1.1.3 Expanded Memory
    • 1.1.4 External Memory Bus
    • 1.1.5 Extended Instruction Set
    • 1.1.6 Easy Migration
  • 1.2 Other Special Features
  • 1.3 Details on Individual Family Members
    • TABLE 1-1: Device Features for the PIC18F87J10 Family (64-pin Devices)
    • TABLE 1-2: Device Features for the PIC18F87J10 Family (80-pin Devices)
    • FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-pin) Block Diagram
    • FIGURE 1-2: PIC18F8XJ10/8XJ15 (80-pin) Block Diagram
    • TABLE 1-3: PIC18F6XJ10/6XJ15 Pinout I/O Descriptions
    • TABLE 1-4: PIC18F8XJ10/8XJ15 Pinout I/O Descriptions
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators (HS Modes)
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)
    • TABLE 2-1: Capacitor Selection for Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
  • 2.3 External Clock Input (EC Modes)
    • FIGURE 2-2: External Clock Input Operation (EC Configuration)
    • FIGURE 2-3: External Clock Input Operation (HS OSC Configuration)
  • 2.4 PLL Frequency Multiplier
    • FIGURE 2-4: PLL Block Diagram
    • Register 2-1: OSCTUNE: PLL Control Register
  • 2.5 Internal Oscillator Block
  • 2.6 Clock Sources and Oscillator Switching
    • FIGURE 2-5: PIC18F87J10 Family Clock Diagram
    • 2.6.1 Oscillator Control Register
    • 2.6.2 Oscillator Transitions
      • Register 2-2: OSCCON: Oscillator Control Register
  • 2.7 Effects of Power-Managed Modes on the Various Clock Sources
  • 2.8 Power-up Delays
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
• 3.0 Power-Managed Modes
  • 3.1 Selecting Power-Managed Modes
    • 3.1.1 Clock Sources
    • 3.1.2 Entering Power-Managed Modes
      • TABLE 3-1: Power-Managed Modes
    • 3.1.3 Clock Transitions and Status Indicators
    • 3.1.4 Multiple Sleep Commands
  • 3.2 Run Modes
    • 3.2.1 PRI_RUN Mode
    • 3.2.2 SEC_RUN Mode
      • FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode
      • FIGURE 3-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)
    • 3.2.3 RC_RUN Mode
      • FIGURE 3-3: Transition Timing to RC_RUN Mode
      • FIGURE 3-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode
  • 3.3 Sleep Mode
  • 3.4 Idle Modes
    • FIGURE 3-5: Transition Timing for Entry to Sleep Mode
    • FIGURE 3-6: Transition Timing for Wake From Sleep (HSPLL)
    • 3.4.1 PRI_IDLE Mode
    • 3.4.2 SEC_IDLE Mode
      • FIGURE 3-7: Transition Timing for Entry to Idle Mode
      • FIGURE 3-8: Transition Timing for Wake From Idle to Run Mode
    • 3.4.3 RC_IDLE Mode
  • 3.5 Exiting Idle and Sleep Modes
    • 3.5.1 Exit By Interrupt
    • 3.5.2 Exit By WDT Time-out
    • 3.5.3 Exit By Reset
    • 3.5.4 Exit Without an Oscillator Start-up Delay
• 4.0 Reset
  • 4.1 RCON Register
    • FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
    • Register 4-1: RCON: Reset Control Register
  • 4.2 Master Clear (MCLR)
  • 4.3 Power-on Reset (POR)
  • 4.4 Brown-out Reset (BOR)
    • FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
    • 4.4.1 Detecting BOR
  • 4.5 Power-up Timer (PWRT)
    • 4.5.1 Time-out Sequence
      • FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)
      • FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
      • FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
      • FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)
  • 4.6 Reset State of Registers
    • TABLE 4-1: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • TABLE 4-2: Initialization Conditions for All Registers
• 5.0 Memory Organization
  • 5.1 Program Memory Organization
    • FIGURE 5-1: Memory Maps for PIC18F87J10 Family Devices
    • 5.1.1 Hard Memory Vectors
      • FIGURE 5-2: Hard Vector and Configuration Word Locations for PIC18F87J10 Family Devices
    • 5.1.2 Flash Configuration Words
      • TABLE 5-1: Flash Configuration Word for PIC18F87J10 Family Devices
    • 5.1.3 PIC18F8XJ10/8XJ15 Program Memory Modes
      • Register 5-1: CONFIG3L: Configuration Register 3 Low
    • 5.1.4 Extended Microcontroller Mode and Address Shifting
      • FIGURE 5-3: Memory Maps for PIC18F87J10 Family Program Memory Modes
      • TABLE 5-2: Memory Access for PIC18F8XJ10/8XJ15 Program Memory Modes
    • 5.1.5 Program Counter
    • 5.1.6 Return Address Stack
      • FIGURE 5-4: Return Address Stack and Associated Registers
      • Register 5-2: STKPTR: Stack Pointer Register
    • 5.1.7 Fast Register Stack
      • EXAMPLE 5-1: Fast Register Stack Code Example
    • 5.1.8 Look-up Tables in Program Memory
      • EXAMPLE 5-2: Computed GOTO Using an Offset Value
  • 5.2 PIC18 Instruction Cycle
    • 5.2.1 Clocking Scheme
    • 5.2.2 Instruction Flow/Pipelining
      • FIGURE 5-5: Clock/Instruction Cycle
      • EXAMPLE 5-3: Instruction Pipeline Flow
    • 5.2.3 Instructions in Program Memory
      • FIGURE 5-6: Instructions in Program Memory
    • 5.2.4 Two-Word Instructions
      • EXAMPLE 5-4: Two-Word Instructions
  • 5.3 Data Memory Organization
    • 5.3.1 Bank Select Register
      • FIGURE 5-7: Data Memory Map for PIC18FX5J10/X5J15/X6J10 Devices
      • FIGURE 5-8: Data Memory Map for PIC18FX6J15/X7J10 Devices
      • FIGURE 5-9: Use of the Bank Select Register (Direct Addressing)
    • 5.3.2 Access Bank
    • 5.3.3 General Purpose Register File
    • 5.3.4 Special Function Registers
      • TABLE 5-3: Special Function Register Map for PIC18F87J10 Family Devices
      • TABLE 5-4: Register File Summary (PIC18F87J10 Family)
    • 5.3.5 STATUS Register
      • Register 5-3: STATUS Register
  • 5.4 Data Addressing Modes
    • 5.4.1 Inherent and Literal Addressing
    • 5.4.2 Direct Addressing
    • 5.4.3 Indirect Addressing
      • EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing
      • FIGURE 5-10: Indirect Addressing
  • 5.5 Program Memory and the Extended Instruction Set
  • 5.6 Data Memory and the Extended Instruction Set
    • 5.6.1 Indexed Addressing with Literal Offset
    • 5.6.2 Instructions Affected By Indexed Literal Offset Mode
      • FIGURE 5-11: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extend...
    • 5.6.3 Mapping the Access Bank in Indexed Literal Offset Mode
    • 5.6.4 BSR in Indexed Literal Offset Mode
      • FIGURE 5-12: Remapping the Access Bank with Indexed Literal Offset Addressing
• 6.0 Program Memory
  • 6.1 Table Reads and Table Writes
    • FIGURE 6-1: Table Read and Table Write Operations
  • 6.2 Control Registers
    • 6.2.1 Table Latch Register (TABLAT)
    • 6.2.2 Table Pointer Register (TBLPTR)
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions
  • 6.3 Reading the Flash Program Memory
    • FIGURE 6-2: Reads from Program Memory
    • EXAMPLE 6-1: Reading a Flash Program Memory Word
  • 6.4 Writing to Program Memory Space (PIC18F8XJ10/8XJ15 Devices Only)
    • 6.4.1 Write Verify
    • 6.4.2 Unexpected Termination of Write Operation
  • 6.5 Erasing External Memory (PIC18F8XJ10/8XJ15 Devices Only)
  • 6.6 Writing and Erasing On-Chip Program Memory (ICSP Mode)
  • 6.7 Flash Program Operation During Code Protection
    • TABLE 6-2: Registers Associated with Flash Program Memory
• 7.0 External Memory Bus
  • TABLE 7-1: PIC18F8XJ10/8XJ15 External Bus � I/O Port Functions
  • 7.1 External Memory Bus Control
    • Register 7-1: MEMCON: External Memory Bus Control Register
  • 7.2 Address and Data Width
    • 7.2.1 Address Shifting on the External Bus
    • 7.2.2 21-Bit Addressing
      • TABLE 7-2: Address and Data Lines for Different Address and Data Widths
  • 7.3 Wait States
  • 7.4 Port Pin Weak Pull-ups
  • 7.5 Program Memory Modes and the External Memory Bus
  • 7.6 16-bit Data Width Modes
    • 7.6.1 16-Bit Byte Write Mode
      • FIGURE 7-1: 16-Bit Byte Write Mode Example
    • 7.6.2 16-Bit Word Write Mode
      • FIGURE 7-2: 16-Bit Word Write Mode Example
    • 7.6.3 16-Bit Byte Select Mode
      • FIGURE 7-3: 16-Bit Byte Select Mode Example
    • 7.6.4 16-Bit Mode Timing
      • FIGURE 7-4: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)
      • FIGURE 7-5: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)
  • 7.7 8-bit Mode
    • FIGURE 7-6: 8-Bit Multiplexed Mode Example
    • 7.7.1 8-Bit Mode Timing
      • FIGURE 7-7: External Memory Bus Timing For TBLRD (Extended Microcontroller Mode)
      • FIGURE 7-8: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)
  • 7.8 Operation in Power-Managed Modes
• 8.0 8 X 8 Hardware Multiplier
  • 8.1 Introduction
  • 8.2 Operation
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
    • TABLE 8-1: Performance Comparison for Various Multiply Operations
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
• 9.0 Interrupts
  • FIGURE 9-1: PIC18F87J10 family Interrupt Logic
  • 9.1 INTCON Registers
    • Register 9-1: INTCON: Interrupt Control Register
    • Register 9-2: INTCON2: Interrupt Control Register 2
    • Register 9-3: INTCON3: Interrupt Control Register 3
  • 9.2 PIR Registers
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
    • Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3
  • 9.3 PIE Registers
    • Register 9-7: PIE1: Peripheral Interrupt Enable Register 1
    • Register 9-8: PIE2: Peripheral Interrupt Enable Register 2
    • Register 9-9: PIE3: Peripheral Interrupt Enable Register 3
  • 9.4 IPR Registers
    • Register 9-10: IPR1: Peripheral Interrupt Priority Register 1
    • Register 9-11: IPR2: Peripheral Interrupt Priority Register 2
    • Register 9-12: IPR3: Peripheral Interrupt Priority Register 3
  • 9.5 RCON Register
    • Register 9-13: RCON: Reset Control Register
  • 9.6 INTn Pin Interrupts
  • 9.7 TMR0 Interrupt
  • 9.8 PORTB Interrupt-on-Change
  • 9.9 Context Saving During Interrupts
    • EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM
• 10.0 I/O Ports
  • FIGURE 10-1: Generic I/O Port Operation
  • 10.1 I/O Port Pin Capabilities
    • 10.1.1 Pin Output Drive
      • TABLE 10-1: Output Drive Levels
    • 10.1.2 Input Pins and Voltage Considerations
      • TABLE 10-2: Input Voltage Levels
  • 10.2 PORTA, TRISA and LATA Registers
    • EXAMPLE 10-1: Initializing PORTA
    • TABLE 10-3: PORTA Functions
    • TABLE 10-4: Summary of Registers Associated with PORTA
  • 10.3 PORTB, TRISB and LATB Registers
    • EXAMPLE 10-2: Initializing PORTB
    • TABLE 10-5: PORTB Functions
    • TABLE 10-6: Summary of Registers Associated with PORTB
  • 10.4 PORTC, TRISC and LATC Registers
    • EXAMPLE 10-3: Initializing PORTC
    • TABLE 10-7: PORTC Functions
    • TABLE 10-8: Summary of Registers Associated with PORTC
  • 10.5 PORTD, TRISD and LATD Registers
    • EXAMPLE 10-4: Initializing PORTD
    • TABLE 10-9: PORTD Functions
    • TABLE 10-10: Summary of Registers Associated with PORTD
  • 10.6 PORTE, TRISE and LATE Registers
    • EXAMPLE 10-5: Initializing PORTE
    • TABLE 10-11: PORTE Functions
    • TABLE 10-12: Summary of Registers Associated with PORTE
  • 10.7 PORTF, LATF and TRISF Registers
    • EXAMPLE 10-6: Initializing PORTF
    • TABLE 10-13: PORTF Functions
    • TABLE 10-14: Summary of Registers Associated with PORTF
  • 10.8 PORTG, TRISG and LATG Registers
    • EXAMPLE 10-7: Initializing PORTG
    • TABLE 10-15: PORTG Functions
    • TABLE 10-16: Summary of Registers Associated with PORTG
  • 10.9 PORTH, LATH and TRISH Registers
    • EXAMPLE 10-8: Initializing PORTH
    • TABLE 10-17: PORTH Functions
    • TABLE 10-18: Summary of Registers Associated with PORTH
  • 10.10 PORTJ, TRISJ and LATJ Registers
    • EXAMPLE 10-9: Initializing PORTJ
    • TABLE 10-19: PORTJ Functions
    • TABLE 10-20: Summary of Registers Associated with PORTJ
  • 10.11 Parallel Slave Port
    • FIGURE 10-2: PORTD and PORTE Block Diagram (Parallel Slave Port)
    • Register 10-1: PSPCON: Parallel Slave Port Control Register
    • FIGURE 10-3: Parallel Slave Port Write Waveforms
    • FIGURE 10-4: Parallel Slave Port Read Waveforms
    • TABLE 10-21: Registers Associated with Parallel Slave Port
• 11.0 Timer0 Module
  • Register 11-1: T0CON: Timer0 Control Register
  • 11.1 Timer0 Operation
  • 11.2 Timer0 Reads and Writes in 16-Bit Mode
    • FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)
    • FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)
  • 11.3 Prescaler
    • 11.3.1 Switching Prescaler Assignment
  • 11.4 Timer0 Interrupt
    • TABLE 11-1: Registers Associated with Timer0
• 12.0 Timer1 Module
  • Register 12-1: T1CON: Timer1 Control Register
  • 12.1 Timer1 Operation
    • FIGURE 12-1: Timer1 Block Diagram
    • FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
  • 12.2 Timer1 16-Bit Read/Write Mode
  • 12.3 Timer1 Oscillator
    • FIGURE 12-3: External Components for the Timer1 LP Oscillator
    • TABLE 12-1: Capacitor Selection for the Timer Oscillator(2,3,4)
    • 12.3.1 Using Timer1 as a Clock Source
    • 12.3.2 Low-Power Timer1 Option
    • 12.3.3 Timer1 Oscillator Layout Considerations
      • FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring
  • 12.4 Timer1 Interrupt
  • 12.5 Resetting Timer1 Using the ECCP Special Event Trigger
  • 12.6 Using Timer1 as a Real-Time Clock
    • EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
• 13.0 Timer2 Module
  • 13.1 Timer2 Operation
    • Register 13-1: T2CON: Timer2 Control Register
  • 13.2 Timer2 Interrupt
  • 13.3 Timer2 Output
    • FIGURE 13-1: Timer2 Block Diagram
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
• 14.0 Timer3 Module
  • Register 14-1: T3CON: Timer3 Control Register
  • 14.1 Timer3 Operation
    • FIGURE 14-1: Timer3 Block Diagram
    • FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
  • 14.2 Timer3 16-Bit Read/Write Mode
  • 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source
  • 14.4 Timer3 Interrupt
  • 14.5 Resetting Timer3 Using the ECCP Special Event Trigger
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
• 15.0 Timer4 Module
  • 15.1 Timer4 Operation
    • Register 15-1: T4CON: Timer4 Control Register
  • 15.2 Timer4 Interrupt
  • 15.3 Output of TMR4
    • FIGURE 15-1: Timer4 Block Diagram
    • TABLE 15-1: Registers Associated with Timer4 as a Timer/Counter
• 16.0 Capture/Compare/PWM (CCP) Modules
  • Register 16-1: CCPxCON: CCP Control Register (CCP4 and CCP5)
  • 16.1 CCP Module Configuration
    • 16.1.1 CCP Modules and Timer Resources
      • TABLE 16-1: CCP Mode � Timer Resource
    • 16.1.2 ECCP2 Pin Assignment
      • FIGURE 16-1: CCP and Timer Interconnect Configurations
  • 16.2 Capture Mode
    • 16.2.1 CCP Pin Configuration
    • 16.2.2 Timer1/Timer3 Mode Selection
    • 16.2.3 Software Interrupt
    • 16.2.4 CCP Prescaler
      • EXAMPLE 16-1: Changing Between Capture Prescalers (CCP5 Shown)
      • FIGURE 16-2: Capture Mode Operation Block Diagram
  • 16.3 Compare Mode
    • 16.3.1 CCP Pin Configuration
    • 16.3.2 Timer1/Timer3 Mode Selection
    • 16.3.3 Software Interrupt Mode
      • FIGURE 16-3: Compare Mode Operation Block Diagram
      • TABLE 16-2: Registers Associated with Capture, Compare, Timer1 and Timer3
  • 16.4 PWM Mode
    • FIGURE 16-4: Simplified PWM Block Diagram
    • FIGURE 16-5: PWM Output
    • 16.4.1 PWM Period
      • EQUATION 16-1:
    • 16.4.2 PWM Duty Cycle
      • EQUATION 16-2:
      • EQUATION 16-3:
    • 16.4.3 Setup for PWM Operation
      • TABLE 16-3: Example PWM Frequencies and Resolutions at 40 MHz
      • TABLE 16-4: Registers Associated with PWM, Timer2 and Timer4
• 17.0 Enhanced Capture/ Compare/PWM (ECCP) Module
  • Register 17-1: CCPxCON: Enhanced CCP Control Register (ECCP1/ECCP2/ECCP3)
  • 17.1 ECCP Outputs and Configuration
    • 17.1.1 ECCP1/ECCP3 Outputs and Program Memory Mode
    • 17.1.2 ECCP2 Outputs and Program Memory Modes
    • 17.1.3 Use of CCP4 and CCP5 with ECCP1 and ECCP3
    • 17.1.4 ECCP Modules and Timer Resources
      • TABLE 17-1: Pin Configurations for ECCP1
      • TABLE 17-2: Pin Configurations for ECCP2
      • TABLE 17-3: Pin Configurations for ECCP3
  • 17.2 Capture and Compare Modes
    • 17.2.1 Special Event Trigger
  • 17.3 Standard PWM Mode
  • 17.4 Enhanced PWM Mode
    • 17.4.1 PWM Period
      • EQUATION 17-1:
      • FIGURE 17-1: Simplified Block Diagram of the Enhanced PWM Module
    • 17.4.2 PWM Duty Cycle
      • EQUATION 17-2:
      • EQUATION 17-3:
    • 17.4.3 PWM Output Configurations
      • TABLE 17-4: Example PWM Frequencies and Resolutions at 40 MHz
      • FIGURE 17-2: PWM Output Relationships (Active-High State)
      • FIGURE 17-3: PWM Output Relationships (Active-Low State)
    • 17.4.4 Half-Bridge Mode
      • FIGURE 17-4: Half-bridge PWM Output
      • FIGURE 17-5: Examples of Half-Bridge Output Mode Applications
    • 17.4.5 Full-Bridge Mode
      • FIGURE 17-6: Full-Bridge PWM Output
      • FIGURE 17-7: Example of Full-Bridge Application
      • FIGURE 17-8: PWM Direction Change
      • FIGURE 17-9: PWM Direction Change at Near 100% Duty Cycle
    • 17.4.6 Programmable Dead-Band Delay
    • 17.4.7 Enhanced PWM Auto-Shutdown
      • Register 17-2: ECCPxDEL: PWM Configuration Register
      • Register 17-3: ECCPxAS: Enhanced CCP Auto-Shutdown Control Register
    • 17.4.8 Start-up Considerations
      • FIGURE 17-10: PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled)
      • FIGURE 17-11: PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled)
    • 17.4.9 Setup for PWM Operation
    • 17.4.10 Effects of a Reset
      • TABLE 17-5: Registers Associated with ECCP Modules and Timer1 to Timer4
• 18.0 Master Synchronous Serial Port (MSSP) Module
  • 18.1 Master SSP (MSSP) Module Overview
  • 18.2 Control Registers
  • 18.3 SPI Mode
    • FIGURE 18-1: MSSP Block Diagram (SPI�Mode)
    • 18.3.1 Registers
      • Register 18-1: SSPxSTAT: MSSPx Status Register (SPI Mode)
      • Register 18-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)
    • 18.3.2 Operation
      • EXAMPLE 18-1: Loading the SSP1BUF (SSP1SR) Register
    • 18.3.3 Enabling SPI I/O
    • 18.3.4 Typical Connection
      • FIGURE 18-2: SPI� Master/Slave Connection
    • 18.3.5 Master Mode
      • FIGURE 18-3: SPI� Mode Waveform (Master Mode)
    • 18.3.6 Slave Mode
    • 18.3.7 Slave Select Synchronization
      • FIGURE 18-4: Slave Synchronization Waveform
      • FIGURE 18-5: SPI� Mode Waveform (Slave Mode with CKE = 0)
      • FIGURE 18-6: SPI� Mode Waveform (Slave Mode with CKE = 1)
    • 18.3.8 Operation in Power-Managed Modes
    • 18.3.9 Effects of a Reset
    • 18.3.10 Bus Mode Compatibility
      • TABLE 18-1: SPI� Bus Modes
    • 18.3.11 SPI Clock Speed and Module Interactions
      • TABLE 18-2: Registers Associated with SPI� Operation
  • 18.4 I2C Mode
    • FIGURE 18-7: MSSP Block Diagram (I2C� Mode)
    • 18.4.1 Registers
      • Register 18-3: SSPxSTAT: MSSPx Status Register (I2C Mode) 
      • Register 18-4: SSPxCON1: MSSPx Control Register 1 (I2C Mode) 
      • Register 18-5: SSPxCON2: MSSPx Control Register 2 (I2C Mode)
    • 18.4.2 Operation
    • 18.4.3 Slave Mode
      • FIGURE 18-8: I2C� Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)
      • FIGURE 18-9: I2C� Slave Mode Timing (Transmission, 7-bit Address)
      • FIGURE 18-10: I2C� Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)
      • FIGURE 18-11: I2C� Slave Mode Timing (Transmission, 10-bit Address)
    • 18.4.4 Clock Stretching
      • FIGURE 18-12: Clock Synchronization Timing
      • FIGURE 18-13: I2C� Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)
      • FIGURE 18-14: I2C� Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)
    • 18.4.5 General Call Address Support
      • FIGURE 18-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)
    • 18.4.6 Master Mode
      • FIGURE 18-16: MSSP Block Diagram (I2C� Master Mode)
    • 18.4.7 Baud Rate
      • FIGURE 18-17: Baud Rate Generator Block Diagram
      • TABLE 18-3: I2C� Clock Rate w/BRG
      • FIGURE 18-18: Baud Rate Generator Timing with Clock Arbitration
    • 18.4.8 I2C Master Mode Start Condition Timing
      • FIGURE 18-19: First Start Bit Timing
    • 18.4.9 I2C Master Mode Repeated Start Condition Timing
      • FIGURE 18-20: Repeated Start Condition Waveform
    • 18.4.10 I2C Master Mode Transmission
    • 18.4.11 I2C Master Mode Reception
      • FIGURE 18-21: I2C� Master Mode Waveform (Transmission, 7 or 10-bit Address)
      • FIGURE 18-22: I2C� Master Mode Waveform (Reception, 7-bit Address)
    • 18.4.12 Acknowledge Sequence Timing
    • 18.4.13 Stop Condition Timing
      • FIGURE 18-23: Acknowledge Sequence Waveform
      • FIGURE 18-24: Stop Condition Receive or Transmit Mode
    • 18.4.14 Sleep Operation
    • 18.4.15 Effects of a Reset
    • 18.4.16 Multi-Master Mode
    • 18.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
      • FIGURE 18-25: Bus Collision Timing for Transmit and Acknowledge
      • FIGURE 18-26: Bus Collision During Start Condition (SDAx Only)
      • FIGURE 18-27: Bus Collision During Start Condition (SCLx = 0)
      • FIGURE 18-28: BRG Reset Due to SDAx Arbitration During Start Condition
      • FIGURE 18-29: Bus Collision During a Repeated Start Condition (Case 1)
      • FIGURE 18-30: Bus Collision During Repeated Start Condition (Case 2)
      • FIGURE 18-31: Bus Collision During a Stop Condition (Case 1)
      • FIGURE 18-32: Bus Collision During a Stop Condition (Case 2)
      • TABLE 18-4: Registers Associated with I2C� Operation
• 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
  • Register 19-1: TXSTAx: Transmit Status and Control Register
  • Register 19-2: RCSTAx: Receive Status and Control Register
  • Register 19-3: BAUDCONx: Baud Rate Control Register
  • 19.1 Baud Rate Generator (BRG)
    • 19.1.1 Operation In Power-Managed Modes
    • 19.1.2 Sampling
      • TABLE 19-1: Baud Rate Formulas
      • EXAMPLE 19-1: Calculating Baud Rate Error
      • TABLE 19-2: Registers Associated with Baud Rate Generator
      • TABLE 19-3: Baud Rates for Asynchronous Modes
    • 19.1.3 Auto-Baud Rate Detect
      • TABLE 19-4: BRG Counter Clock Rates
      • FIGURE 19-1: Automatic Baud Rate Calculation
      • FIGURE 19-2: BRG Overflow Sequence
  • 19.2 EUSART Asynchronous Mode
    • 19.2.1 EUSART Asynchronous Transmitter
      • FIGURE 19-3: EUSART Transmit Block Diagram
      • FIGURE 19-4: Asynchronous Transmission
      • FIGURE 19-5: Asynchronous Transmission (Back to Back)
      • TABLE 19-5: Registers Associated with Asynchronous Transmission
    • 19.2.2 EUSART Asynchronous Receiver
    • 19.2.3 Setting Up 9-bit Mode with Address Detect
      • FIGURE 19-6: EUSART Receive Block Diagram
      • FIGURE 19-7: Asynchronous Reception
      • TABLE 19-6: Registers Associated with Asynchronous Reception
    • 19.2.4 Auto-Wake-up on Sync Break Character
      • FIGURE 19-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation
      • FIGURE 19-9: Auto-Wake-up Bit (WUE) Timings During Sleep
    • 19.2.5 Break Character Sequence
    • 19.2.6 Receiving a Break Character
      • FIGURE 19-10: Send Break Character Sequence
  • 19.3 EUSART Synchronous Master Mode
    • 19.3.1 EUSART Synchronous Master Transmission
      • FIGURE 19-11: Synchronous Transmission
      • FIGURE 19-12: Synchronous Transmission (Through TXEN)
      • TABLE 19-7: Registers Associated with Synchronous Master Transmission
    • 19.3.2 EUSART Synchronous Master Reception
      • FIGURE 19-13: Synchronous Reception (Master Mode, SREN)
      • TABLE 19-8: Registers Associated with Synchronous Master Reception
  • 19.4 EUSART Synchronous Slave Mode
    • 19.4.1 EUSART Synchronous Slave Transmission
      • TABLE 19-9: Registers Associated with Synchronous Slave Transmission
    • 19.4.2 EUSART Synchronous Slave Reception
      • TABLE 19-10: Registers Associated with Synchronous Slave Reception
• 20.0 10-Bit Analog-to-Digital Converter (A/D) Module
  • Register 20-1: ADCON0: A/D Control Register 0
  • Register 20-2: ADCON1: A/D Control Register 1
  • Register 20-3: ADCON2: A/D Control Register 2
  • FIGURE 20-1: A/D Block Diagram
  • FIGURE 20-2: Analog Input Model
  • 20.1 A/D Acquisition Requirements
    • EQUATION 20-1: Acquisition Time
    • EQUATION 20-2: A/D Minimum Charging Time
    • EQUATION 20-3: Calculating the Minimum Required Acquisition Time
  • 20.2 Selecting and Configuring Automatic Acquisition Time
  • 20.3 Selecting the A/D Conversion Clock
    • TABLE 20-1: Tad vs. Device Operating Frequencies
  • 20.4 Configuring Analog Port Pins
  • 20.5 A/D Conversions
  • 20.6 Use of the ECCP2 Trigger
    • FIGURE 20-3: A/D Conversion Tad Cycles (ACQT2:ACQT0 = 000, Tacq = 0)
    • FIGURE 20-4: A/D Conversion Tad Cycles (ACQT2:ACQT0 = 010, Tacq = 4 Tad)
  • 20.7 A/D Converter Calibration
  • 20.8 Operation in Power-Managed Modes
    • TABLE 20-2: Summary of A/D Registers
• 21.0 Comparator Module
  • Register 21-1: CMCON: Comparator Module Control Register
  • 21.1 Comparator Configuration
    • FIGURE 21-1: Comparator I/O Operating Modes
  • 21.2 Comparator Operation
  • 21.3 Comparator Reference
    • FIGURE 21-2: Single Comparator
    • 21.3.1 External Reference Signal
    • 21.3.2 Internal Reference Signal
  • 21.4 Comparator Response Time
  • 21.5 Comparator Outputs
    • FIGURE 21-3: Comparator Output Block Diagram
  • 21.6 Comparator Interrupts
  • 21.7 Comparator Operation During Sleep
  • 21.8 Effects of a Reset
  • 21.9 Analog Input Connection Considerations
    • FIGURE 21-4: Comparator Analog Input Model
    • TABLE 21-1: Registers Associated with Comparator Module
• 22.0 Comparator Voltage Reference Module
  • 22.1 Configuring the Comparator Voltage Reference
    • Register 22-1: CVRCON: Comparator Voltage Reference Control Register
    • FIGURE 22-1: Comparator Voltage Reference Block Diagram
  • 22.2 Voltage Reference Accuracy/Error
  • 22.3 Operation During Sleep
  • 22.4 Effects of a Reset
  • 22.5 Connection Considerations
    • FIGURE 22-2: Comparator Voltage Reference Output Buffer Example
    • TABLE 22-1: Registers Associated with Comparator Voltage Reference
• 23.0 Special Features of the CPU
  • 23.1 Configuration Bits
    • 23.1.1 Considerations for Configuring the PIC18F87J10 family Devices
      • TABLE 23-1: Configuration Bits and Device IDs
      • Register 23-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)
      • Register 23-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
      • Register 23-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
      • Register 23-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
      • Register 23-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)
      • Register 23-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
      • Register 23-7: Device ID Register 1 for PIC18F87J10 Family Devices
      • Register 23-8: Device ID Register 2 for PIC18F87J10 Family Devices
  • 23.2 Watchdog Timer (WDT)
    • 23.2.1 Control Register
      • FIGURE 23-1: WDT Block Diagram
      • Register 23-9: WDTCON: Watchdog Timer Control Register
      • TABLE 23-2: Summary of Watchdog Timer Registers
  • 23.3 On-Chip Voltage Regulator
    • 23.3.1 On-Chip Regulator and BOR
    • 23.3.2 Power-up Requirements
      • FIGURE 23-2: Connections for the On-Chip Regulator
  • 23.4 Two-Speed Start-up
    • 23.4.1 Special Considerations for Using Two-Speed Start-up
      • FIGURE 23-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)
  • 23.5 Fail-Safe Clock Monitor
    • FIGURE 23-4: FSCM Block Diagram
    • 23.5.1 FSCM and the Watchdog Timer
    • 23.5.2 Exiting Fail-Safe Operation
      • FIGURE 23-5: FSCM Timing Diagram
    • 23.5.3 FSCM Interrupts in Power-Managed Modes
    • 23.5.4 POR or Wake-up From Sleep
  • 23.6 Program Verification and Code Protection
    • 23.6.1 Configuration Register Protection
  • 23.7 In-Circuit Serial Programming
  • 23.8 In-Circuit Debugger
    • TABLE 23-3: Debugger Resources
• 24.0 Instruction Set Summary
  • 24.1 Standard Instruction Set
    • TABLE 24-1: Opcode Field Descriptions
    • FIGURE 24-1: General Format for Instructions
    • TABLE 24-2: PIC18F87J10 family Instruction Set
    • 24.1.1 Standard Instruction Set
  • 24.2 Extended Instruction Set
    • 24.2.1 Extended Instruction Syntax
      • TABLE 24-3: Extensions to the PIC18 Instruction Set
    • 24.2.2 Extended Instruction Set
    • 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode
    • 24.2.4 Considerations When Enabling the Extended Instruction Set
    • 24.2.5 Special Considerations with Microchip MPLAB� IDE Tools
• 25.0 Development Support
  • 25.1 MPLAB Integrated Development Environment Software
  • 25.2 MPASM Assembler
  • 25.3 MPLAB C17 and MPLAB C18 C Compilers
  • 25.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 25.5 MPLAB C30 C Compiler
  • 25.6 MPLAB ASM30 Assembler, Linker and Librarian
  • 25.7 MPLAB SIM Software Simulator
  • 25.8 MPLAB SIM30 Software Simulator
  • 25.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
  • 25.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
  • 25.11 MPLAB ICD 2 In-Circuit Debugger
  • 25.12 PRO MATE II Universal Device Programmer
  • 25.13 MPLAB PM3 Device Programmer
  • 25.14 PICSTART Plus Development Programmer
  • 25.15 PICDEM 1 PICmicro Demonstration Board
  • 25.16 PICDEM.net Internet/Ethernet Demonstration Board
  • 25.17 PICDEM 2 Plus Demonstration Board
  • 25.18 PICDEM 3 PIC16C92X Demonstration Board
  • 25.19 PICDEM 4 8/14/18-Pin Demonstration Board
  • 25.20 PICDEM 17 Demonstration Board
  • 25.21 PICDEM 18R PIC18C601/801 Demonstration Board
  • 25.22 PICDEM LIN PIC16C43X Demonstration Board
  • 25.23 PICkitTM 1 Flash Starter Kit
  • 25.24 PICDEM USB PIC16C7X5 Demonstration Board
  • 25.25 Evaluation and Programming Tools
• 26.0 Electrical Characteristics
  • Absolute Maximum Ratings(�)
    • FIGURE 26-1: PIC18F87J10 family Voltage-frequency Graph (Industrial)
  • 26.1 DC Characteristics: Supply Voltage, PIC18F87J10 Family (Industrial)
  • 26.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial)
  • 26.3 DC Characteristics: PIC18F87J10 Family (Industrial)
    • TABLE 26-1: Memory Programming Requirements
    • TABLE 26-2: Comparator Specifications
    • TABLE 26-3: Voltage Reference Specifications
    • TABLE 26-4: Internal Voltage Regulator Specifications
  • 26.4 AC (Timing) Characteristics
    • 26.4.1 Timing Parameter Symbology
    • 26.4.2 Timing Conditions
      • TABLE 26-5: Temperature and Voltage Specifications � AC
      • FIGURE 26-2: Load Conditions for Device Timing Specifications
    • 26.4.3 Timing Diagrams and Specifications
      • FIGURE 26-3: External Clock Timing (All Modes Except PLL)
      • TABLE 26-6: External Clock Timing Requirements
      • TABLE 26-7: PLL Clock Timing Specifications (Vdd = 2.5V to 3.6V)
      • TABLE 26-8: AC Characteristics: Internal RC Accuracy PIC18F87J10 family (Industrial)
      • FIGURE 26-4: CLKO and I/O Timing
      • TABLE 26-9: CLKO and I/O Timing Requirements
      • FIGURE 26-5: Program Memory Read Timing Diagram
      • TABLE 26-10: CLKO and I/O Timing Requirements
      • FIGURE 26-6: Program Memory Write Timing Diagram
      • TABLE 26-11: Program Memory Write Timing Requirements
      • FIGURE 26-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
      • FIGURE 26-8: Brown-out Reset Timing
      • TABLE 26-12: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...
      • FIGURE 26-9: Timer0 and Timer1 External Clock Timings
      • TABLE 26-13: Timer0 and Timer1 External Clock Requirements
      • FIGURE 26-10: Capture/Compare/PWM Timings (Including ECCP Modules)
      • TABLE 26-14: Capture/Compare/PWM Requirements (Including ECCP Modules)
      • TABLE 26-15: Parallel Slave Port Requirements
      • FIGURE 26-11: Example SPI� Master Mode Timing (CKE=0)
      • TABLE 26-16: Example SPI� Mode Requirements (Master Mode, Cke=0)
      • FIGURE 26-12: Example SPI� Master Mode Timing (CKE=1)
      • TABLE 26-17: Example SPI� Mode Requirements (Master Mode, CKE=1)
      • FIGURE 26-13: Example SPI� Slave Mode Timing (CKE=0)
      • TABLE 26-18: Example SPI� Mode Requirements (Slave Mode Timing, CKE=0)
      • FIGURE 26-14: Example SPI� Slave Mode Timing (CKE=1)
      • TABLE 26-19: Example SPI� Slave Mode Requirements (CKE=1)
      • FIGURE 26-15: I2C� Bus Start/Stop Bits Timing
      • TABLE 26-20: I2C� Bus Start/Stop Bits Requirements (Slave Mode)
      • FIGURE 26-16: I2C� Bus Data Timing
      • TABLE 26-21: I2C� Bus Data Requirements (Slave Mode)
      • FIGURE 26-17: Master SSP I2C� Bus Start/Stop Bits Timing Waveforms
      • TABLE 26-22: Master SSP I2C� Bus Start/Stop Bits Requirements
      • FIGURE 26-18: Master SSP I2C� Bus Data Timing
      • TABLE 26-23: Master SSP I2C� Bus Data Requirements
      • FIGURE 26-19: EUSART Synchronous Transmission (Master/Slave) Timing
      • TABLE 26-24: EUSART Synchronous Transmission Requirements
      • FIGURE 26-20: EUSART Synchronous Receive (Master/Slave) Timing
      • TABLE 26-25: EUSART Synchronous Receive Requirements
      • TABLE 26-26: A/D Converter Characteristics: PIC18F87J10 family (Industrial)
      • FIGURE 26-21: A/D Conversion Timing
      • TABLE 26-27: A/D Conversion Requirements
• 27.0 Packaging Information
  • 27.1 Package Marking Information
  • 27.2 Package Details
    • 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
    • 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
• Appendix A: Migration Between High-End Device Families
  • TABLE A-1: Notable Differences Between PIC18F8722 and PIC18F87J10 Families
  • A.1 Power Requirement Differences
  • A.2 Pin Differences
  • A.3 Oscillator Differences
  • A.4 Peripherals
• Index
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