Document Outline

• High-Performance RISC CPU:
• External Memory Interface (PIC18F8X8X Devices Only):
• Peripheral Features:
• Analog Features:
• ECAN Module Features:
• Special Microcontroller Features:
• CMOS Technology:
• Pin Diagrams
• Table of Contents
• 1.0 Device Overview
  • TABLE 1-1: PIC18F6585/8585/6680/8680 Device Features
  • FIGURE 1-1: PIC18F6X8X Block Diagram
  • FIGURE 1-2: PIC18F8X8X Block Diagram
  • TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS 
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS, XT or LP Configuration)
    • TABLE 2-1: Capacitor Selection for Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
    • FIGURE 2-2: External Clock Input Operation (HS, XT or LP OSC Configuration)
  • 2.3 RC Oscillator
    • FIGURE 2-3: RC Oscillator Mode
  • 2.4 External Clock Input
    • FIGURE 2-4: External Clock Input Operation (EC Configuration)
    • FIGURE 2-5: External Clock Input Operation (ECIO Configuration)
  • 2.5 Phase Locked Loop (PLL)
    • FIGURE 2-6: PLL Block Diagram
  • 2.6 Oscillator Switching Feature
    • FIGURE 2-7: Device Clock Sources
    • 2.6.1 System clock switch bit
      • Register 2-1: OSCCON Register
    • 2.6.2 Oscillator Transitions
      • FIGURE 2-8: Timing Diagram For Transition From OSC1 to Timer1 Oscillator
      • FIGURE 2-9: Timing For Transition Between Timer1 and OSC1 (HS, XT, LP)
      • FIGURE 2-10: Timing For Transition Between Timer1 and OSC1 (HS with PLL ACTIVE, SCS1 = 1)
      • FIGURE 2-11: Timing For Transition Between Timer1 and OSC1 (EC with PLL ACTIVE, SCS1 = 1)
      • FIGURE 2-12: Timing For Transition Between Timer1 and OSC1 (RC, EC)
  • 2.7 Effects of Sleep Mode on the On-Chip Oscillator
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
  • 2.8 Power-up Delays
• 3.0 Reset
  • FIGURE 3-1: Simplified Block Diagram of On-chip Reset Circuit
  • 3.1 Power-on Reset (POR)
    • FIGURE 3-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  • 3.2 Power-up Timer (PWRT)
  • 3.3 Oscillator Start-up Timer (OST)
  • 3.4 PLL Lock Time-out
  • 3.5 Brown-out Reset (BOR)
  • 3.6 Time-out Sequence
    • TABLE 3-1: Time-out in Various Situations
    • Register 3-1: RCON Register Bits and Positions
    • TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • TABLE 3-3: Initialization Conditions for All Registers
    • FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd VIA 1 KW RESISTOR)
    • FIGURE 3-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1
    • FIGURE 3-5: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2
    • FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd VIA 1 KW RESISTOR)
    • FIGURE 3-7: Time-out Sequence on POR w/ PLL Enabled (MCLR tied to Vdd VIA 1 KW RESISTOR)
• 4.0 Memory Organization
  • 4.1 Program Memory Organization
    • 4.1.1 PIC18F8X8X Program Memory Modes
      • FIGURE 4-1: Internal Program Memory Map and Stack for PIC18F6585/8585
      • FIGURE 4-2: Internal Program Memory Map and Stack for PIC18F6680/8680
      • TABLE 4-1: Memory Access for PIC18F8X8X Program Memory Modes
      • Register 4-1: CONFIG3L CONFIGURATION BYTE
      • FIGURE 4-3: Memory Maps for PIC18F8X8X Program Memory Modes
  • 4.2 Return Address Stack
    • 4.2.1 Top-Of-Stack Access
    • 4.2.2 Return Stack Pointer (STKPTR)
      • Register 4-2: STKPTR Register
      • FIGURE 4-4: Return Address Stack and Associated Registers
    • 4.2.3 PUSH and POP instructions
    • 4.2.4 Stack Full/Underflow Resets
  • 4.3 Fast Register Stack
    • EXAMPLE 4-1: Fast Register Stack Code Example
  • 4.4 PCL, PCLATH and PCLATU
  • 4.5 Clocking Scheme/Instruction Cycle
    • FIGURE 4-5: Clock/Instruction Cycle
  • 4.6 Instruction Flow/Pipelining
    • EXAMPLE 4-2: Instruction Pipeline Flow
  • 4.7 Instructions in Program Memory
    • FIGURE 4-6: Instructions in Program memory
    • 4.7.1 Two-Word Instructions
      • EXAMPLE 4-3: Two-Word Instructions
  • 4.8 Look-up Tables
    • 4.8.1 Computed GOTO
    • 4.8.2 Table reads/Table writes
  • 4.9 Data Memory Organization
    • 4.9.1 General purpose Register File
    • 4.9.2 Special Function Registers
      • FIGURE 4-7: Data Memory Map for PIC18FXX80/XX85 Devices
      • TABLE 4-2: Special Function Register Map
      • TABLE 4-3: Register File Summary
  • 4.10 Access Bank
  • 4.11 Bank Select Register (BSR)
    • FIGURE 4-8: Direct Addressing
  • 4.12 Indirect Addressing, INDF and FSR Registers
    • EXAMPLE 4-4: How to Clear RAM (Bank 1) Using Indirect Addressing
    • 4.12.1 Indirect Addressing Operation
      • FIGURE 4-9: Indirect Addressing Operation
      • FIGURE 4-10: Indirect Addressing
  • 4.13 Status Register
    • Register 4-3: Status Register
  • 4.14 RCON Register
    • Register 4-4: RCON Register
• 5.0 Flash Program Memory
  • 5.1 Table Reads and Table Writes
    • FIGURE 5-1: Table Read Operation
    • FIGURE 5-2: Table Write Operation
  • 5.2 Control Registers
    • 5.2.1 EECON1 AND EECON2 REGISTERS
      • Register 5-1: EECON1 Register (Address FA6h)
    • 5.2.2 TABLAT � Table Latch Register
    • 5.2.3 TBLPTR � Table Pointer Register
    • 5.2.4 TABLE POINTER BOUNDARIES
      • TABLE 5-1: Table Pointer Operations with TBLRD and TBLWT Instructions
      • FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
  • 5.3 Reading the Flash Program Memory
    • FIGURE 5-4: Reads from Flash Program Memory
    • EXAMPLE 5-1: READING A Flash PROGRAM MEMORY WORD
  • 5.4 Erasing Flash Program Memory
    • 5.4.1 Flash PROGRAM MEMORY ERASE SEQUENCE
      • EXAMPLE 5-2: ERasing a Flash PROGRAM MEMORY row
  • 5.5 Writing to Flash Program Memory
    • FIGURE 5-5: TABLE WRITES to Flash PROGRAM MEMORY
    • 5.5.1 Flash Program memory write sequence
      • EXAMPLE 5-3: writing to Flash PROGRAM MEMORY
      • EXAMPLE 5-3: writing to Flash PROGRAM MEMORY (CONTINUED)
    • 5.5.2 Write verify
    • 5.5.3 unexpected termination of write operation
    • 5.5.4 protection against spurious writes
  • 5.6 Flash Program Operation During Code Protection
    • TABLE 5-2: Registers Associated with program Flash Memory
• 6.0 External Memory Interface
  • 6.1 Program Memory Modes and the External Memory Interface
    • Register 6-1: MEMCON Register
    • TABLE 6-1: PIC18F8x8X External Bus � I/O Port Functions
  • 6.2 16-bit Mode
    • 6.2.1 16-bit BYTE WRITE Mode
      • FIGURE 6-1: 16-BIT BYTE WRITE MODE EXAMPLE
    • 6.2.2 16-bit word WRITE Mode
      • FIGURE 6-2: 16-bit Word Write ModE EXAMPLE
    • 6.2.3 16-bit byte select Mode
      • FIGURE 6-3: 16-bit Byte Select Mode EXAMPLE
    • 6.2.4 16-bit Mode TIMING
      • FIGURE 6-4: EXTERNAL PROGRAM MEMORY BUS TIMING (16-BIT MODE)
• 7.0 Data EEPROM Memory
  • 7.1 EEADRH:EEADR
  • 7.2 EECON1 and EECON2 Registers
    • Register 7-1: EECON1 Register (Address FA6h)
  • 7.3 Reading the Data EEPROM Memory
    • EXAMPLE 7-1: Data EEPROM Read
  • 7.4 Writing to the Data EEPROM Memory
    • EXAMPLE 7-2: Data EEPROM Write
  • 7.5 Write Verify
  • 7.6 Protection Against Spurious Write
  • 7.7 Operation During Code-Protect
  • 7.8 Using the Data EEPROM
    • EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
    • TABLE 7-1: Registers Associated with DATA EEPROM Memory
• 8.0 8 X 8 Hardware Multiplier
  • 8.1 Introduction
  • 8.2 Operation
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
    • TABLE 8-1: Performance Comparison
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
• 9.0 Interrupts
  • FIGURE 9-1: Interrupt Logic
  • 9.1 INTCON Registers
    • Register 9-1: INTCON Register
    • Register 9-2: INTCON2 Register
    • Register 9-3: INTCON3 Register
  • 9.2 PIR Registers
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
    • Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3
  • 9.3 PIE Registers
    • Register 9-7: PIE1: Peripheral Interrupt Enable Register 1
    • Register 9-8: PIE2: Peripheral Interrupt Enable Register 2
    • Register 9-9: PIE3: Peripheral Interrupt Enable Register 3
  • 9.4 IPR Registers
    • Register 9-10: IPR1: Peripheral Interrupt Priority Register 1
    • Register 9-11: IPR2: Peripheral Interrupt Priority Register 2
    • Register 9-12: IPR3: Peripheral Interrupt Priority Register 3
  • 9.5 RCON Register
    • Register 9-13: RCON Register
  • 9.6 INT0 Interrupt
  • 9.7 TMR0 Interrupt
  • 9.8 PORTB Interrupt-on-Change
  • 9.9 Context Saving During Interrupts
    • EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM
• 10.0 I/O Ports
  • FIGURE 10-1: Simplified Block Diagram of PORT/LAT/TRIS Operation
  • 10.1 PORTA, TRISA and LATA Registers
    • EXAMPLE 10-1: Initializing PORTA
    • FIGURE 10-2: Block Diagram of RA3:RA0 and RA5 Pins
    • FIGURE 10-3: Block Diagram of RA4/T0CKI Pin
    • FIGURE 10-4: Block Diagram of RA6 PIN (When Enabled as I/O)
    • TABLE 10-1: PORTA Functions
    • TABLE 10-2: Summary of Registers Associated with PORTA
  • 10.2 PORTB, TRISB and LATB Registers
    • EXAMPLE 10-2: Initializing PORTB
    • FIGURE 10-5: Block Diagram of RB7:RB4 Pins
    • FIGURE 10-6: Block Diagram of RB2:RB0 Pins
    • FIGURE 10-7: Block Diagram of RB3 PIN
    • TABLE 10-3: PORTB Functions
    • TABLE 10-4: Summary of Registers Associated with PORTB
  • 10.3 PORTC, TRISC and LATC Registers
    • EXAMPLE 10-3: Initializing PORTC
    • FIGURE 10-8: PORTC Block Diagram (Peripheral Output Override)
    • TABLE 10-5: PORTC Functions
    • TABLE 10-6: Summary of Registers Associated with PORTC
  • 10.4 PORTD, TRISD and LATD Registers
    • EXAMPLE 10-4: Initializing PORTD
    • FIGURE 10-9: PORTD Block Diagram in I/O Port Mode
    • FIGURE 10-10: PortD BLOCK DIAGRAM IN System Bus Mode (PIC18F8X8X only)
    • TABLE 10-7: PORTD Functions
    • TABLE 10-8: Summary of Registers Associated with PORTD
  • 10.5 PORTE, TRISE and LATE Registers
    • EXAMPLE 10-5: Initializing PORTE
    • FIGURE 10-11: PortE Block Diagram IN I/O MODE
    • FIGURE 10-12: PORTE BLOCK DIAGRAM IN System Bus Mode (PIC18F8X8X only)
    • TABLE 10-9: PORTE Functions
    • TABLE 10-10: Summary of Registers Associated with PORTE
  • 10.6 PORTF, LATF and TRISF Registers
    • EXAMPLE 10-6: Initializing PORTF
    • FIGURE 10-13: PORTF RF1/AN6/C2OUT AND RF2/AN7/C1OUT PINS Block Diagram
    • FIGURE 10-14: RF6:RF3 and RF0 Pins Block Diagram
    • FIGURE 10-15: RF7 Pin Block Diagram
    • TABLE 10-11: PORTF Functions
    • TABLE 10-12: Summary of Registers Associated with PORTF
  • 10.7 PORTG, TRISG and LATG Registers
    • EXAMPLE 10-7: Initializing PORT
    • FIGURE 10-16: RG0/CANTX1 PIN BLOCK DIAGRAM
    • FIGURE 10-17: RG1/CANTX2 PIN BLOCK DIAGRAM
    • FIGURE 10-18: RG2/CANRX PIN BLOCK DIAGRAM
    • FIGURE 10-19: RG3 PIN BLOCK DIAGRAM
    • FIGURE 10-20: RG4/P1D PIN BLOCK DIAGRAM
    • FIGURE 10-21: RG5/MCLR/Vpp PIN BLOCK DIAGRAM
    • TABLE 10-13: PORTG Functions
    • TABLE 10-14: Summary of Registers Associated with PORTG
  • 10.8 PORTH, LATH and TRISH Registers
    • EXAMPLE 10-8: Initializing PORTH
    • FIGURE 10-22: RH3:RH0 PINS Block Diagram in i/o mode
    • FIGURE 10-23: RH7:RH4 PINS Block Diagram in I/O Mode
    • FIGURE 10-24: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
    • TABLE 10-15: PORTH Functions
    • TABLE 10-16: Summary of Registers Associated with PORTH
  • 10.9 PORTJ, TRISJ and LATJ Registers
    • EXAMPLE 10-9: Initializing PORTJ
    • FIGURE 10-25: PORTJ Block Diagram IN I/O MODE
    • FIGURE 10-26: RJ5:RJ0 Pins Block Diagram IN SYSTEM BUS MODE
    • FIGURE 10-27: RJ7:RJ6 PINS Block Diagram In System Bus Mode
    • TABLE 10-17: PORTJ Functions
    • TABLE 10-18: Summary of Registers Associated with PORTJ
  • 10.10 Parallel Slave Port (PSP)
    • FIGURE 10-28: PORTD and PORTE Block Diagram (Parallel Slave Port)
    • Register 10-1: PSPCON Register
    • FIGURE 10-29: Parallel Slave Port Write Waveforms
    • FIGURE 10-30: Parallel Slave Port Read Waveforms
    • TABLE 10-19: Registers Associated with Parallel Slave Port
• 11.0 Timer0 Module
  • Register 11-1: T0CON: Timer0 Control Register
  • FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode
  • FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode
  • 11.1 Timer0 Operation
  • 11.2 Prescaler
    • 11.2.1 Switching Prescaler Assignment
  • 11.3 Timer0 Interrupt
  • 11.4 16-Bit Mode Timer Reads and Writes
    • TABLE 11-1: Registers Associated with Timer0
• 12.0 Timer1 Module
  • Register 12-1: T1CON: Timer1 Control Register
  • 12.1 Timer1 Operation
    • FIGURE 12-1: Timer1 Block Diagram
    • FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode
  • 12.2 Timer1 Oscillator
    • TABLE 12-1: Capacitor Selection for the alternate Oscillator
  • 12.3 Timer1 Interrupt
  • 12.4 Resetting Timer1 Using a CCP Trigger Output
  • 12.5 Timer1 16-Bit Read/Write Mode
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
• 13.0 Timer2 Module
  • 13.1 Timer2 Operation
    • Register 13-1: T2CON: Timer2 Control Register
  • 13.2 Timer2 Interrupt
  • 13.3 Output of TMR2
    • FIGURE 13-1: Timer2 Block Diagram
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
• 14.0 Timer3 Module
  • Register 14-1: T3CON: Timer3 Control Register
  • 14.1 Timer3 Operation
    • FIGURE 14-1: Timer3 Block Diagram
    • FIGURE 14-2: Timer3 Block Diagram Configured in 16-bit READ/WRITE Mode
  • 14.2 Timer1 Oscillator
  • 14.3 Timer3 Interrupt
  • 14.4 Resetting Timer3 Using a CCP Trigger Output
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
• 15.0 Capture/Compare/PWM (CCP) Modules
  • Register 15-1: CCP1CON Register
  • Register 15-2: CCP2CON Register
  • 15.1 CCP Module
    • TABLE 15-1: CCP Mode � Timer Resource
  • 15.2 Capture Mode
    • 15.2.1 CCP pin Configuration
    • 15.2.2 Timer1/Timer3 Mode Selection
      • TABLE 15-2: Interaction of CCP Modules
    • 15.2.3 Software Interrupt
    • 15.2.4 CCP Prescaler
    • 15.2.5 CAN Message Time-Stamp
      • EXAMPLE 15-1: Changing Between Capture Prescalers
      • FIGURE 15-1: Capture Mode Operation Block Diagram
  • 15.3 Compare Mode
    • 15.3.1 CCP Pin Configuration
    • 15.3.2 timer1/Timer3 Mode Selection
    • 15.3.3 Software Interrupt Mode
    • 15.3.4 Special Event Trigger
      • FIGURE 15-2: Compare Mode Operation Block Diagram
      • TABLE 15-3: Registers associated with Capture, compare, Timer1 and Timer3
  • 15.4 PWM Mode
    • FIGURE 15-3: Simplified PWM Block Diagram
    • FIGURE 15-4: PWM Output
    • 15.4.1 PWM period
      • EQUATION 15-1:
    • 15.4.2 PWM Duty Cycle
      • EQUATION 15-2:
      • EQUATION 15-3:
    • 15.4.3 Setup for PWM Operation
      • TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz
      • TABLE 15-5: Registers associated with PWM and Timer2
• 16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
  • Register 16-1: CCP1CON Register
  • 16.1 ECCP Outputs
    • TABLE 16-1: Pin Assignments for Various ECCP Modes
    • FIGURE 16-1: Compare Mode Operation Block Diagram
  • 16.2 Enhanced PWM Mode
    • 16.2.1 PWM period
      • EQUATION 16-1:
    • 16.2.2 PWM Duty Cycle
      • EQUATION 16-2:
      • EQUATION 16-3:
    • 16.2.3 PWM OUTPUT CONFIGURATIONS
      • TABLE 16-2: Example PWM Frequencies and Resolutions at 40 MHz
      • FIGURE 16-2: Simplified Block Diagram of the Enhanced PWM Module
      • FIGURE 16-3: PWM Output Relationships (Active-High State)
      • FIGURE 16-4: PWM Output Relationships (Active-LOW State)
    • 16.2.4 Half-Bridge mode
      • FIGURE 16-5: Half-Bridge PWM OUTPUT
      • FIGURE 16-6: EXAMPLES OF Half-Bridge OUTPUT MODE APPLICATIONS
    • 16.2.5 Full-Bridge Mode
      • FIGURE 16-7: Full-Bridge PWM OUTPUT
      • FIGURE 16-8: EXAMPLE OF Full-Bridge APPLICATION
      • FIGURE 16-9: PWM Direction Change
      • FIGURE 16-10: PWM Direction Change at Near 100% Duty Cycle
    • 16.2.6 Programmable Dead-Band Delay
    • 16.2.7 Enhanced PWM Auto-Shutdown
      • Register 16-2: ECCP1DEL: ECCP1 Delay Register
      • Register 16-3: ECCP1AS: Enhanced CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER
    • 16.2.8 Start-up Considerations
      • FIGURE 16-11: PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled)
      • FIGURE 16-12: PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled)
    • 16.2.9 SETUP FOR PWM OPERATION
    • 16.2.10 Effects of a Reset
      • TABLE 16-3: Registers associated with PWM and Timer2
• 17.0 Master Synchronous Serial Port (MSSP) Module
  • 17.1 Master SSP (MSSP) Module Overview
  • 17.2 Control Registers
  • 17.3 SPI Mode
    • FIGURE 17-1: MSSP Block Diagram (SPIMode)
    • 17.3.1 Registers
      • Register 17-1: SSPSTAT: MSSP Status REGISTER (SPI MODE)
      • Register 17-2: SSPCON1: MSSP Control Register 1 (SPI Mode)
    • 17.3.2 Operation
      • EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register
    • 17.3.3 Enabling SPI I/O
    • 17.3.4 Typical Connection
      • FIGURE 17-2: SPI Master/Slave Connection
    • 17.3.5 Master Mode
      • FIGURE 17-3: SPI Mode Waveform (Master Mode)
    • 17.3.6 Slave Mode
    • 17.3.7 Slave Select Synchronization
      • FIGURE 17-4: Slave Synchronization Waveform
      • FIGURE 17-5: SPI Mode Waveform (Slave Mode with CKE = 0)
      • FIGURE 17-6: SPI Mode Waveform (Slave Mode with CKE = 1)
    • 17.3.8 Sleep Operation
    • 17.3.9 Effects of a Reset
    • 17.3.10 Bus Mode Compatibility
      • TABLE 17-1: SPI Bus Modes
      • TABLE 17-2: Registers Associated with SPI Operation
  • 17.4 I2C Mode
    • FIGURE 17-7: MSSP Block Diagram (I2C Mode)
    • 17.4.1 Registers
      • Register 17-3: SSPSTAT: MSSP Status Register (I2C Mode)
      • Register 17-4: SSPCON1: MSSP Control Register 1 (I2C Mode)
      • Register 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C Mode)
    • 17.4.2 Operation
    • 17.4.3 SLAVE Mode
      • FIGURE 17-8: I2C Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)
      • FIGURE 17-9: I2C Slave Mode Timing (Transmission, 7-bit Address)
      • FIGURE 17-10: I2C Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)
      • FIGURE 17-11: I2C Slave Mode Timing (Transmission, 10-bit Address)
    • 17.4.4 Clock Stretching
      • FIGURE 17-12: Clock synchronization Timing
      • FIGURE 17-13: I2C Slave Mode Timing With SEN = 1 (Reception, 7-bit Address)
      • FIGURE 17-14: I2C Slave Mode Timing SEN = 1 (Reception, 10-bit Address)
    • 17.4.5 General Call Address Support
      • FIGURE 17-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)
    • 17.4.6 Master Mode
      • FIGURE 17-16: MSSP Block Diagram (I2C Master Mode)
    • 17.4.7 Baud Rate Generator
      • FIGURE 17-17: Baud Rate Generator Block Diagram
      • TABLE 17-3: I2C Clock Rate w/BRG
      • FIGURE 17-18: Baud Rate Generator Timing With Clock Arbitration
    • 17.4.8 I2C Master Mode Start Condition Timing
      • FIGURE 17-19: First Start Bit Timing
    • 17.4.9 I2C Master Mode Repeated Start Condition Timing
      • FIGURE 17-20: Repeat Start Condition Waveform
    • 17.4.10 I2C Master Mode Transmission
    • 17.4.11 I2C Master Mode Reception
      • FIGURE 17-21: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address)
      • FIGURE 17-22: I2C Master Mode Waveform (Reception, 7-Bit Address)
    • 17.4.12 Acknowledge Sequence Timing
    • 17.4.13 Stop Condition Timing
      • FIGURE 17-23: Acknowledge Sequence Waveform
      • FIGURE 17-24: Stop Condition Receive or Transmit Mode
    • 17.4.14 Sleep Operation
    • 17.4.15 Effect of a Reset
    • 17.4.16 Multi-Master Mode
    • 17.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
      • FIGURE 17-25: Bus Collision Timing for Transmit and Acknowledge
      • FIGURE 17-26: Bus Collision During Start Condition (SDA only)
      • FIGURE 17-27: Bus Collision During Start Condition (SCL = 0)
      • FIGURE 17-28: BRG Reset Due to SDA Arbitration During Start Condition
      • FIGURE 17-29: Bus Collision During a Repeated Start Condition (Case 1)
      • FIGURE 17-30: Bus Collision During Repeated Start Condition (Case 2)
      • FIGURE 17-31: Bus Collision During a Stop Condition (Case 1)
      • FIGURE 17-32: Bus Collision During a Stop Condition (Case 2)
• 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART)
  • Register 18-1: TXSTA: Transmit Status and Control Register
  • Register 18-2: RCSTA: Receive Status and Control Register
  • Register 18-3: BAUDCON: Baud Rate Control Register
  • 18.1 USART Baud Rate Generator (BRG)
    • 18.1.1 SAMPLING
      • TABLE 18-1: Baud rate Formulas
      • EXAMPLE 18-1: Calculating Baud Rate Error
      • TABLE 18-2: Registers Associated with Baud Rate Generator
      • TABLE 18-3: BAUD Rates for Asynchronous Modes
    • 18.1.2 Auto-Baud Rate Detect
      • TABLE 18-4: BRG Counter Clock Rates
      • FIGURE 18-1: Automatic Baud Rate Calculation
  • 18.2 USART Asynchronous Mode
    • 18.2.1 USART Asynchronous Transmitter
      • FIGURE 18-2: USART Transmit Block Diagram
      • FIGURE 18-3: Asynchronous Transmission
      • FIGURE 18-4: Asynchronous Transmission (Back to Back)
      • TABLE 18-5: Registers Associated with Asynchronous Transmission
    • 18.2.2 USART Asynchronous Receiver
    • 18.2.3 Setting up 9-bit mode with address detect
      • FIGURE 18-5: USART Receive Block Diagram
      • FIGURE 18-6: Asynchronous Reception
      • TABLE 18-6: Registers Associated with Asynchronous Reception
    • 18.2.4 Auto-Wake-up on Sync Break Character
      • FIGURE 18-7: Auto-Wake-Up bit (WUE) timings during normal operation
      • FIGURE 18-8: Auto-Wake-Up bit (WUE) timings during Sleep
    • 18.2.5 BREAK Character Sequence
    • 18.2.6 Receiving a BREAK Character
      • FIGURE 18-9: Send BREAK Character Sequence
  • 18.3 USART Synchronous Master Mode
    • 18.3.1 USART Synchronous Master Transmission
      • FIGURE 18-10: Synchronous Transmission
      • FIGURE 18-11: Synchronous Transmission (Through TXEN)
      • TABLE 18-7: Registers Associated with Synchronous Master Transmission
    • 18.3.2 USART Synchronous Master Reception
      • FIGURE 18-12: Synchronous Reception (Master Mode, SREN)
      • TABLE 18-8: Registers Associated with Synchronous Master Reception
  • 18.4 USART Synchronous Slave Mode
    • 18.4.1 USART Synchronous Slave Transmit
      • TABLE 18-9: Registers Associated with Synchronous Slave Transmission
    • 18.4.2 USART Synchronous Slave Reception
      • TABLE 18-10: Registers Associated with Synchronous Slave Reception
• 19.0 10-bit Analog-to-Digital Converter (A/D) Module
  • Register 19-1: ADCON0 Register
  • Register 19-2: ADCON1 Register
  • Register 19-3: ADCON2 Register
  • FIGURE 19-1: A/D Block Diagram
  • FIGURE 19-2: Analog Input Model
  • 19.1 A/D Acquisition Requirements
  • 19.2 A/D Vref+ and Vref- References
    • EQUATION 19-1: Acquisition Time
    • EQUATION 19-2: A/D Minimum Charging Time
    • EXAMPLE 19-1: Calculating the Minimum Required Acquisition Time
  • 19.3 Selecting and Configuring Automatic Acquisition Time
  • 19.4 Selecting the A/D Conversion Clock
  • 19.5 Configuring Analog Port Pins
    • TABLE 19-1: Tad vs. Device Operating Frequencies
  • 19.6 A/D Conversions
  • 19.7 Use of the CCP2 Trigger
    • FIGURE 19-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, TACQ = 0)
    • FIGURE 19-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, TACQ = 4 TAD)
    • TABLE 19-2: Summary of A/D Registers
• 20.0 Comparator Module
  • Register 20-1: CMCON Register
  • 20.1 Comparator Configuration
    • FIGURE 20-1: Comparator I/O Operating Modes
  • 20.2 Comparator Operation
  • 20.3 Comparator Reference
    • FIGURE 20-2: Single Comparator
    • 20.3.1 EXTERNAL REFERENCE SIGNAL
    • 20.3.2 INTERNAL REFERENCE SIGNAL
  • 20.4 Comparator Response Time
  • 20.5 Comparator Outputs
    • FIGURE 20-3: Comparator Output Block Diagram
  • 20.6 Comparator Interrupts
  • 20.7 Comparator Operation During Sleep
  • 20.8 Effects of a Reset
  • 20.9 Analog Input Connection Considerations
    • FIGURE 20-4: Comparator Analog Input Model
    • TABLE 20-1: Registers Associated with Comparator Module
• 21.0 Comparator Voltage Reference Module
  • 21.1 Configuring the Comparator Voltage Reference
    • Register 21-1: CVRCON Register
    • FIGURE 21-1: Voltage Reference Block Diagram
  • 21.2 Voltage Reference Accuracy/Error
  • 21.3 Operation During Sleep
  • 21.4 Effects of a Reset
  • 21.5 Connection Considerations
    • FIGURE 21-2: Voltage Reference Output Buffer Example
    • TABLE 21-1: Registers Associated with Comparator Voltage Reference
• 22.0 Low-Voltage Detect
  • FIGURE 22-1: Typical Low-Voltage Detect Application
  • FIGURE 22-2: Low-Voltage Detect (LVD) Block Diagram
  • FIGURE 22-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
  • 22.1 Control Register
    • Register 22-1: LVDCON Register
  • 22.2 Operation
    • FIGURE 22-4: Low-Voltage Detect waveforms
    • 22.2.1 Reference Voltage Set Point
    • 22.2.2 Current Consumption
  • 22.3 Operation During Sleep
  • 22.4 Effects of a Reset
• 23.0 ECAN Module
  • 23.1 Module Overview
    • 23.1.1 Module Functionality
      • FIGURE 23-1: CAN Buffers and Protocol Engine Block Diagram
  • 23.2 CAN Module Registers
    • 23.2.1 CAN Control and Status Registers
      • Register 23-1: CANCON: CAN Control Register
      • Register 23-2: CANSTAT: CAN Status Register
      • Register 23-2: CANSTAT: CAN Status Register (CONTINUED)
      • EXAMPLE 23-1: changing to configuration mode
      • EXAMPLE 23-2: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers
      • EXAMPLE 23-2: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers (Cont...
      • Register 23-3: ECANCON: Enhanced CAN Control Register
      • Register 23-4: COMSTAT: Communication Status Register
    • 23.2.2 DEDICATED CAN Transmit Buffer Registers
      • Register 23-5: TXBnCON: Transmit Buffer n Control Registers [0 � n � 2]
      • Register 23-6: TXBnSIDH: Transmit Buffer n Standard Identifier REGISTERS, High Byte [0 � n � 2]
      • Register 23-7: TXBnSIDL: Transmit Buffer n Standard Identifier REGISTERS, Low Byte [0 � n � 2]
      • Register 23-8: TXBnEIDH: Transmit Buffer n Extended Identifier REGISTERS, High Byte [0 � n � 2]
      • Register 23-9: TXBnEIDL: Transmit Buffer n Extended Identifier REGISTERS, Low Byte [0 � n � 2]
      • Register 23-10: TXBnDm: Transmit Buffer n Data Field Byte m Registers [0 � n � 2, 0 � m � 7]
      • Register 23-11: TXBnDLC: Transmit Buffer n Data Length Code Registers [0 � n � 2]
      • Register 23-12: TXERRCNT: Transmit Error Count Register
      • EXAMPLE 23-3: transmitting a can message USING banked method
      • EXAMPLE 23-4: transmitting a can message USING WIN bits
    • 23.2.3 DEDICATED CAN Receive Buffer Registers
      • Register 23-13: RXB0CON: Receive Buffer 0 Control Register
      • Register 23-13: RXB0CON: Receive Buffer 0 Control Register (CONTINUED)
      • Register 23-14: RXB1CON: Receive Buffer 1 Control Register
      • Register 23-15: RXBnSIDH: Receive Buffer n Standard Identifier REGISTERS, High Byte [0 � n � 1]
      • Register 23-16: RXBnSIDL: Receive Buffer n Standard Identifier REGISTERS, Low Byte [0 � n � 1]
      • Register 23-17: RXBnEIDH: Receive Buffer n Extended Identifier REGISTERS, High Byte [0 � n � 1]
      • Register 23-18: RXBnEIDL: RECEIVE Buffer n Extended Identifier REGISTERS, Low BytE [0 � n � 1]
      • Register 23-19: RXBnDLC: Receive Buffer n Data Length Code Registers [0 � n � 1]
      • Register 23-20: RXBnDm: Receive Buffer n Data Field Byte m Registers [0 � n � 1, 0 � m � 7]
      • Register 23-21: RXERRCNT: Receive Error Count Register
      • EXAMPLE 23-5: reading a can message
      • Register 23-22: BnCON: tx/rx Buffer n Control RegisterS in receive mode [0 � n � 5, TXnEN (bsel0<...
      • Register 23-23: BnCON: tx/rx Buffer n Control RegisterS in transmit mode [0 � n � 5, TXnEN (bsel0...
      • Register 23-24: BnSIDH: TX/RX Buffer n Standard Identifier REGISTERS, High Byte in receive mode [...
      • Register 23-25: BnSIDH: TX/RX Buffer n Standard Identifier REGISTERS, High Byte in transmit mode ...
      • Register 23-26: BnSIDL: TX/RX Buffer n Standard Identifier REGISTERS, Low Byte IN RECEIVE MODE [0...
      • Register 23-27: BnSIDL: TX/RX Buffer n Standard Identifier REGISTERS, Low Byte IN TRANSMIT MODE [...
      • Register 23-28: BnEIDH: TX/RX Buffer n Extended Identifier REGISTERS, High Byte in receive mode [...
      • Register 23-29: BnEIDH: TX/RX Buffer n Extended Identifier REGISTERS, High Byte in transmit mode ...
      • Register 23-30: BnEIDL: TX/RX Buffer n Extended Identifier REGISTERS, Low Byte in receive mode [0...
      • Register 23-31: BnEIDL: TX/RX Buffer n Extended Identifier REGISTERS, Low Byte in transmit mode [...
      • Register 23-32: BnDm: TX/RX Buffer n Data Field Byte m Registers IN RECEIVE MODE [0 � n � 5, 0 � ...
      • Register 23-33: BnDm: TX/RX Buffer n Data Field Byte m Registers IN TRANSMIT MODE [0 � n � 5, 0 �...
      • Register 23-34: BnDLC: TX/RX Buffer n Data Length Code Registers in receive mode [0 � n � 5, TXnE...
      • Register 23-35: BnDLC: TX/RX Buffer n Data Length Code Registers in transmit mode [0 � n � 5, TXn...
      • Register 23-36: bsel0: buffer select register 0(1)
      • Register 23-37: RXFnSIDH: Receive Acceptance Filter n Standard Identifier Filter REGISTERS, High ...
      • Register 23-38: RXFnSIDL: Receive Acceptance Filter n Standard Identifier Filter REGISTERS, Low B...
      • Register 23-39: RXFnEIDH: Receive Acceptance Filter n Extended Identifier REGISTERS, High Byte [0...
      • Register 23-40: RXFnEIDL: Receive Acceptance Filter n Extended Identifier REGISTERS, Low Byte [0 ...
      • Register 23-41: RXMnSIDH: Receive Acceptance Mask n Standard Identifier Mask REGISTERS, High Byte...
      • Register 23-42: RXMnSIDL: Receive Acceptance Mask n Standard Identifier Mask REGISTERS, Low Byte ...
      • Register 23-43: RXMnEIDH: Receive Acceptance Mask n Extended Identifier Mask REGISTERS, High Byte...
      • Register 23-44: RXMnEIDL: Receive Acceptance Mask n Extended Identifier Mask REGISTERS, Low Byte ...
      • Register 23-45: SDFLC: Standard data bytes filter length count REGISTER(1)
      • Register 23-46: rxfconn: receive filter control register n [0 � n � 1](1)
      • Register 23-47: rxfbconn: receive filter buffer control register n(1)
      • Register 23-48: Msel0: mask select register 0(1)
      • Register 23-49: Msel1: mask select register 1(1)
      • Register 23-50: Msel2: mask select register 2(1)
      • Register 23-51: Msel3: mask select register 3(1)
    • 23.2.4 CAN Baud Rate Registers
      • Register 23-52: BRGCON1: Baud Rate Control Register 1
      • Register 23-53: BRGCON2: Baud Rate Control Register 2
      • Register 23-54: BRGCON3: Baud Rate Control Register 3
    • 23.2.5 CAN Module I/O Control Register
      • Register 23-55: CIOCON: CAN I/O Control Register
    • 23.2.6 CAN Interrupt Registers
      • Register 23-56: PIR3: Peripheral Interrupt Flag Register
      • Register 23-57: PIE3: Peripheral Interrupt Enable Register
      • Register 23-58: IPR3: Peripheral Interrupt Priority Register
      • Register 23-59: TXBIE: transmit buffers interrupt enable Register(1)
      • Register 23-60: BIE0: buffer interrupt enable Register 0(1)
      • TABLE 23-1: Can Controller Register Map 
      • TABLE 23-1: Can Controller Register Map (continued)
  • 23.3 CAN Modes of Operation
    • 23.3.1 Configuration Mode
    • 23.3.2 Disable Mode
    • 23.3.3 Normal Mode
    • 23.3.4 Listen Only Mode
    • 23.3.5 Loopback Mode
    • 23.3.6 Error Recognition Mode
  • 23.4 CAN Module Functional Modes
    • 23.4.1 Mode 0 � Legacy mode
    • 23.4.2 Mode 1 � enhanced Legacy mode
    • 23.4.3 Mode 2 � enhanced FIFO MODE
  • 23.5 CAN Message Buffers
    • 23.5.1 DEDICATED Transmit Buffers
    • 23.5.2 DEDICATED receive Buffers
    • 23.5.3 programmable transmit/ receive buffers
    • 23.5.4 programmable AUTO-RTR buffers
  • 23.6 CAN Message Transmission
    • 23.6.1 Initiating Transmission
    • 23.6.2 Aborting Transmission
    • 23.6.3 Transmit Priority
      • FIGURE 23-2: Transmit Buffers
  • 23.7 Message Reception
    • 23.7.1 Receiving a message
    • 23.7.2 Receive Priority
    • 23.7.3 ENHANCED FIFO mode
    • 23.7.4 Time-stamping
  • 23.8 Message Acceptance Filters and Masks
    • TABLE 23-2: Filter/Mask Truth Table
    • FIGURE 23-3: Message Acceptance Mask and Filter Operation
  • 23.9 Baud Rate Setting
    • EQUATION 23-1:
    • EQUATION 23-2:
    • EQUATION 23-3:
    • FIGURE 23-4: Bit Time Partitioning
    • 23.9.1 Time Quanta
      • EXAMPLE 23-6: Calculating Tq, Nominal Bit Rate and Nominal Bit Time
    • 23.9.2 Synchronization Segment
    • 23.9.3 Propagation Segment
    • 23.9.4 Phase Buffer Segments
    • 23.9.5 Sample Point
    • 23.9.6 Information Processing Time
  • 23.10 Synchronization
    • 23.10.1 Hard Synchronization
    • 23.10.2 Resynchronization
    • 23.10.3 SYNCHRONIZATION RULES
      • FIGURE 23-5: Lengthening a Bit Period (Adding SJW to Phase Segment 1)
      • FIGURE 23-6: Shortening a Bit Period (Subtracting SJW from Phase Segment 2)
  • 23.11 Programming Time Segments
  • 23.12 Oscillator Tolerance
  • 23.13 Bit Timing Configuration Registers
    • 23.13.1 BRGCON1
    • 23.13.2 BRGCON2
    • 23.13.3 BRGCON3
  • 23.14 Error Detection
    • 23.14.1 CRC Error
    • 23.14.2 Acknowledge Error
    • 23.14.3 Form Error
    • 23.14.4 Bit Error
    • 23.14.5 Stuff Bit Error
    • 23.14.6 Error States
    • 23.14.7 Error Modes and Error Counters
      • FIGURE 23-7: Error Modes State Diagram
  • 23.15 CAN Interrupts
    • 23.15.1 Interrupt Code Bits
    • 23.15.2 Transmit Interrupt
    • 23.15.3 Receive Interrupt
    • 23.15.4 Message Error Interrupt
    • 23.15.5 Bus Activity Wake-up Interrupt
    • 23.15.6 Error Interrupt
• 24.0 Special Features of the CPU
  • 24.1 Configuration Bits
    • TABLE 24-1: Configuration bits and Device IDs
    • Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
    • Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
    • Register 24-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
    • Register 24-4: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)(1)
    • Register 24-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
    • Register 24-6: CONFIG4l: Configuration Register 4 Low (Byte Address 300006h)
    • Register 24-7: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
    • Register 24-8: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
    • Register 24-9: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
    • Register 24-10: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
    • Register 24-11: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
    • Register 24-12: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
    • Register 24-13: DEVICE ID REGISTER 1 FOR PIC18FXX8x DEVICEs (Address 3FFFFEh)
    • Register 24-14: DEVICE ID REGISTER 2 FOR PIC18FXX8X DEVICEs (Address 3FFFFFh)
  • 24.2 Watchdog Timer (WDT)
    • 24.2.1 Control Register
      • Register 24-15: WDTCON Register
    • 24.2.2 WDT Postscaler
      • FIGURE 24-1: Watchdog Timer Block Diagram
      • TABLE 24-2: Summary of Watchdog Timer Registers
  • 24.3 Power-down Mode (Sleep)
    • 24.3.1 Wake-up from Sleep
    • 24.3.2 Wake-Up Using Interrupts
      • FIGURE 24-2: Wake-up from Sleep Through Interrupt(1,2)
  • 24.4 Program Verification and Code Protection
    • FIGURE 24-3: Code-Protected program memory FOR PIC18FXX8X Devices
    • TABLE 24-3: Summary of Code Protection Registers
    • 24.4.1 Program Memory code ProtectiON
      • FIGURE 24-4: Table Write (WRTn) Disallowed
      • FIGURE 24-5: External Block Table Read (EBTRn) Disallowed
      • FIGURE 24-6: External Block Table Read (EBTRn) Allowed
    • 24.4.2 Data EEPROM Code Protection
    • 24.4.3 Configuration Register Protection
  • 24.5 ID Locations
  • 24.6 In-Circuit Serial Programming
  • 24.7 In-Circuit Debugger
    • TABLE 24-4: Debugger Resources
  • 24.8 Low-Voltage ICSP Programming
• 25.0 Instruction Set Summary
  • TABLE 25-1: Opcode Field Descriptions
  • FIGURE 25-1: General Format for Instructions
  • TABLE 25-2: PIC18FXXX Instruction Set 
  • 25.1 Instruction Set
• 26.0 Development Support
  • 26.1 MPLAB Integrated Development Environment Software
  • 26.2 MPASM Assembler
  • 26.3 MPLAB C17 and MPLAB C18 C Compilers
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 26.5 MPLAB C30 C Compiler
  • 26.6 MPLAB ASM30 Assembler, Linker and Librarian
  • 26.7 MPLAB SIM Software Simulator
  • 26.8 MPLAB SIM30 Software Simulator
  • 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
  • 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
  • 26.11 MPLAB ICD 2 In-Circuit Debugger
  • 26.12 PRO MATE II Universal Device Programmer
  • 26.13 MPLAB PM3 Device Programmer
  • 26.14 PICSTART Plus Development Programmer
  • 26.15 PICDEM 1 PICmicro Demonstration Board
  • 26.16 PICDEM.net Internet/Ethernet Demonstration Board
  • 26.17 PICDEM 2 Plus Demonstration Board
  • 26.18 PICDEM 3 PIC16C92X Demonstration Board
  • 26.19 PICDEM 4 8/14/18-Pin Demonstration Board
  • 26.20 PICDEM 17 Demonstration Board
  • 26.21 PICDEM 18R PIC18C601/801 Demonstration Board
  • 26.22 PICDEM LIN PIC16C43X Demonstration Board
  • 26.23 PICkitTM 1 Flash Starter Kit
  • 26.24 PICDEM USB PIC16C7X5 Demonstration Board
  • 26.25 Evaluation and Programming Tools
• 27.0 Electrical Characteristics
  • Absolute Maximum Ratings (�)
    • FIGURE 27-1: PIC18F6585/8585/6680/8680 Voltage-Frequency Graph (Industrial)
    • FIGURE 27-2: PIC18LF6585/8585/6680/8680 Voltage-Frequency Graph (Industrial)
    • FIGURE 27-3: PIC18F6585/8585/6680/8680 Voltage-Frequency Graph (EXTENDED)
  • 27.1 DC Characteristics: Supply Voltage PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial)
  • 27.2 DC Characteristics: Power-down and Supply Current PIC18FXX8X (Industrial, Extended) PIC18LFX...
  • 27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial)
    • TABLE 27-1: Comparator Specifications
    • TABLE 27-2: Voltage Reference Specifications
    • FIGURE 27-4: Low-Voltage Detect Characteristics
    • TABLE 27-3: Low-Voltage Detect Characteristics
    • TABLE 27-4: Memory Programming Requirements
  • 27.4 AC (Timing) Characteristics
    • 27.4.1 Timing Parameter Symbology
    • 27.4.2 Timing Conditions
      • TABLE 27-5: Temperature and Voltage Specifications - AC
      • FIGURE 27-5: Load Conditions for Device Timing Specifications
    • 27.4.3 Timing Diagrams and Specifications
      • FIGURE 27-6: External Clock Timing (All Modes Except PLL)
      • TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
      • TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2 to 5.5V)
      • FIGURE 27-7: CLKO and I/O Timing
      • TABLE 27-8: CLKO and I/O Timing Requirements
      • FIGURE 27-8: Program Memory Read Timing Diagram
      • TABLE 27-9: Program Memory Read timing Requirements (Vdd = 4.2 to 5.5V)
      • FIGURE 27-9: Program Memory Write Timing Diagram
      • TABLE 27-10: Program Memory Write Timing Requirements (Vdd = 4.2 to 5.5V)
      • FIGURE 27-10: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
      • FIGURE 27-11: Brown-out Reset Timing
      • TABLE 27-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...
      • FIGURE 27-12: Timer0 and Timer1 External Clock Timings
      • TABLE 27-12: Timer0 and Timer1 External Clock Requirements
      • FIGURE 27-13: Capture/Compare/PWM Timings (aLL ccp mODULES)
      • TABLE 27-13: Capture/Compare/PWM Requirements (aLL ccp mODULES)
      • FIGURE 27-14: Parallel Slave Port Timing (PIC18FXX8X)
      • TABLE 27-14: Parallel Slave Port Requirements (PIC18FXX8X)
      • FIGURE 27-15: Example SPI Master Mode Timing (CKE=0)
      • TABLE 27-15: Example SPI Mode Requirements (Master Mode, CKE=0)
      • FIGURE 27-16: Example SPI Master Mode Timing (CKE=1)
      • TABLE 27-16: Example SPI Mode Requirements (Master Mode, CKE=1)
      • FIGURE 27-17: Example SPI Slave Mode Timing (CKE=0)
      • TABLE 27-17: Example SPI Mode Requirements (Slave Mode Timing, CKE=0)
      • FIGURE 27-18: Example SPI Slave Mode Timing (CKE=1)
      • TABLE 27-18: Example SPI Slave Mode Requirements (CKE=1)
      • FIGURE 27-19: I2C Bus Start/Stop Bits Timing
      • TABLE 27-19: I2C Bus Start/Stop Bits Requirements (Slave Mode)
      • FIGURE 27-20: I2C Bus Data Timing
      • TABLE 27-20: I2C Bus Data Requirements (Slave Mode)
      • FIGURE 27-21: Master SSP I2C Bus Start/Stop Bits Timing Waveforms
      • TABLE 27-21: Master SSP I2C Bus Start/Stop Bits Requirements
      • FIGURE 27-22: Master SSP I2C Bus Data Timing
      • TABLE 27-22: Master SSP I2C Bus Data Requirements
      • FIGURE 27-23: USART Synchronous Transmission (Master/Slave) Timing
      • TABLE 27-23: USART Synchronous Transmission Requirements
      • FIGURE 27-24: USART Synchronous Receive (Master/Slave) Timing
      • TABLE 27-24: USART Synchronous Receive Requirements
      • TABLE 27-25: A/D Converter Characteristics: PIC18F6585/8585/6680/8680 (Industrial, Extended) PIC1...
      • FIGURE 27-25: A/D Conversion Timing
      • TABLE 27-26: A/D Conversion Requirements
• 28.0 DC and AC Characteristics Graphs and Tables
  • FIGURE 28-1: Typical Idd vs. Fosc OVER Vdd (HS Mode)
  • FIGURE 28-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode)
  • FIGURE 28-3: Typical Idd vs. Fosc OVER Vdd (HS/PLL Mode)
  • FIGURE 28-4: Maximum Idd vs. Fosc over Vdd (HS/PLL Mode)
  • FIGURE 28-5: Typical Idd vs. Fosc OVER Vdd (XT Mode)
  • FIGURE 28-6: Maximum Idd vs. Fosc OVER Vdd (XT Mode)
  • FIGURE 28-7: Typical Idd vs. Fosc OVER Vdd (LP Mode)
  • FIGURE 28-8: Maximum Idd vs. Fosc OVER Vdd (LP Mode)
  • FIGURE 28-9: Typical Idd vs. Fosc OVER Vdd (EC Mode)
  • FIGURE 28-10: Maximum Idd vs. Fosc over Vdd (EC Mode)
  • FIGURE 28-11: Typical and Maximum It1osc vs. Vdd (Timer1 As System Clock)
  • FIGURE 28-12: Average Fosc vs. Vdd for various r�s (RC Mode, C = 20 pf, Temp = 25C)
  • FIGURE 28-13: Average Fosc vs. Vdd for various r�s (RC Mode, C = 100 pF, Temp = 25C)
  • FIGURE 28-14: Average Fosc vs. Vdd for various r�s (RC Mode, C = 300 pf, Temp = 25C)
  • FIGURE 28-15: Ipd vs. Vdd (Sleep Mode, all peripherals disabled)
  • FIGURE 28-16: Typical and Maximum DIbor vs. Vdd over Temperature, Vbor = 2.00V-2.16V
  • FIGURE 28-17: It1osc vs. Vdd (Sleep Mode, Timer1 and Oscillator Enabled)
  • FIGURE 28-18: Ipd vs. Vdd (Sleep Mode, WDT Enabled)
  • FIGURE 28-19: Typical, Minimum and Maximum WDT Period vs. Vdd
  • FIGURE 28-20: DIlvd vs. Vdd over Temperature, Vlvd = 4.5-4.78V
  • FIGURE 28-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40�C to +125�C)
  • FIGURE 28-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40�C to +125�C)
  • FIGURE 28-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40�C to +125�C)
  • FIGURE 28-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40�C to +125�C)
  • FIGURE 28-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40�C to +125�C)
  • FIGURE 28-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40�C to +125�C)
  • FIGURE 28-27: Minimum and Maximum Vin vs. Vdd (I2C Input, -40�C to +125�C)
  • FIGURE 28-28: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40�C to +125�C)
  • FIGURE 28-29: A/D Non-linearity vs. Vrefh (Vdd = 5V, -40�C to +125�C)
• 29.0 Packaging Information
  • 29.1 Package Marking Information
  • 29.2 Package Details
  • 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
  • 68-Lead Plastic Leaded Chip Carrier (L) �Square (PLCC)
  • 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
• Appendix A: Revision History
  • Revision A (February 2003)
  • Revision B (June 2003)
  • Revision C (February 2004)
• Appendix B: Device Differences
  • TABLE B-1: Device Differences
• Appendix C: Conversion Considerations
• Appendix D: Migration from Mid-range to Enhanced Devices
• Appendix E: Migration from High-end to Enhanced Devices
• INDEX
• On-Line Support
  • Connecting to the Microchip Internet Web Site
• Systems Information and Upgrade Hot Line
• Reader Response
• PIC18F6585/8585/6680/8680 Product Identification System
• Worldwide Sales and Service