Электронный компонент: PIC18LF2515

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2004 Microchip Technology Inc.

Preliminary

DS39636A

PIC18F2X1X/4X1X

Data Sheet

28/40/44-Pin Flash Microcontrollers

with 10-Bit A/D and nanoWatt Technology

DS39636A-page ii

Preliminary

2004 Microchip Technology Inc.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip's products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EE

L

OQ

, micro

ID

, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

� 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

�

Microchip products meet the specification contained in their particular Microchip Data Sheet.

�

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

�

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

�

Microchip is willing to work with the customer who is concerned about the integrity of their code.

�

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company's quality system processes and
procedures are for its PICmicro

�

8-bit MCUs, K

EE

L

OQ

�

code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip's quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

2004 Microchip Technology Inc.

Preliminary

DS39636A-page 1

PIC18F2X1X/4X1X

Power Managed Modes:

� Run: CPU on, peripherals on

� Idle: CPU off, peripherals on

� Sleep: CPU off, peripherals off

� Idle mode currents down to 3.0

�

A typical

� Sleep mode currents down to 20 nA typical

� Timer1 Oscillator: 1.8

�

A, 32 kHz, 2V

� Watchdog Timer: 2.1

�

A

� Two-Speed Oscillator Start-up

Peripheral Highlights:

� High-current sink/source 25 mA/25 mA

� Up to 2 Capture/Compare/PWM (CCP) modules,

one with Auto-Shutdown (28-pin devices)

� Enhanced Capture/Compare/PWM (ECCP)

module (40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-Shutdown and Auto-Restart

� Master Synchronous Serial Port (MSSP) module

supporting 3-wire SPITM (all 4 modes) and I

2

CTM

Master and Slave Modes

� Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.2

- RS-232 operation using internal oscillator

block (no external crystal required)

- Auto-Wake-up on Start bit

- Auto-Baud Detect

� 10-bit, up to 13-channel Analog-to-Digital

Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

� Dual analog comparators with input multiplexing

� Programmable 16-level High/Low-Voltage

Detection (HLVD) module:

- Supports interrupt on High/Low-Voltage

Detection

Flexible Oscillator Structure:

� Four Crystal modes, up to 40 MHz

� 4x Phase Lock Loop (PLL) � available for crystal

and internal oscillators

� Two External RC modes, up to 4 MHz

� Two External Clock modes, up to 40 MHz

� Internal oscillator block:

- 8 user selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL

- User tunable to compensate for frequency drift

� Secondary oscillator using Timer1 @ 32 kHz

� Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features:

� C compiler optimized architecture:

- Optional extended instruction set designed to

optimize re-entrant code

� 100,000 erase/write cycle Flash program memory

typical

� Three programmable external interrupts

� Four input-change interrupts

� Priority levels for interrupts

� 8 x 8 Single-Cycle Hardware Multiplier

� Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

� Single-supply 5V In-Circuit Serial

ProgrammingTM (ICSPTM) via two pins

� In-Circuit Debug (ICD) via two pins

� Wide operating voltage range: 2.0V to 5.5V

� Programmable Brown-out Reset (BOR) with

software enable option

28/40/44-Pin Flash Microcontrollers with

10-bit A/D and nanoWatt Technology

PIC18F2X1X/4X1X

DS39636A-page 2

Preliminary

2004 Microchip Technology Inc.

Device

Program Memory

Data

Memory

I/O

10-bit

A/D (ch)

CCP/ECCP

(PWM)

MSSP

EU

SA

RT

Comp.

Timers

8/16-bit

Flash

(bytes)

# Single-Word

Instructions

SRAM
(bytes)

SPITM

Master

I

2

CTM

PIC18F2410

16K

8192

768

25

10

2/0

Y

Y

1

2

1/3

PIC18F2510

32K

16384

1536

25

10

2/0

Y

Y

1

2

1/3

PIC18F2515

48K

24576

3968

25

10

2/0

Y

Y

1

2

1/3

PIC18F2610

64K

32768

3968

25

10

2/0

Y

Y

1

2

1/3

PIC18F4410

16K

8192

768

36

13

1/1

Y

Y

1

2

1/3

PIC18F4510

32K

16384

1536

36

13

1/1

Y

Y

1

2

1/3

PIC18F4515

48K

24576

3968

36

13

1/1

Y

Y

1

2

1/3

PIC18F4610

64K

32768

3968

36

13

1/1

Y

Y

1

2

1/3

2004 Microchip Technology Inc.

Preliminary

DS39636A-page 3

PIC18F2X1X/4X1X

Pin Diagrams

10
11

2

3
4
5

6

1

8

7

9

12

13
14

15

16

17

18

19

20

23

24

25

26

27

28

22
21

MCLR/V

PP

/RE3

RA0/AN0

RA1/AN1

RA2/AN2/V

REF

-/CV

REF

RA3/AN3/V

REF

+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

V

SS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

(1)

RC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2

(1)

RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12

V

DD

V

SS

RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

28-pin SPDIP, SOIC

Note

1:

RB3 is the alternate pin for CCP2 multiplexing.

10 11

2
3

6

1

18

19

20

21

22

12 13 14

15

8

7

16

17

23

24

25

26

27

28

9

RC0

/T

1

O

S

O/T

13

CK

I

5

4

R

B

7

/
KBI

3

/
PG

D

R

B

6

/
KBI

2

/
PG

C

R

B

5

/
KBI

1

/
PG

M

R

B

4

K

B

I
0/A

N

11

RB3/AN9/CCP2

(1)

RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V

DD

V

SS

RC7/RX/DT

RC6

/
T

X/CK

RC5

/
S

D

O

R

C

4/S

D

I/S

DA

MC

L

R

/V

PP

/RE

3

RA0

/
AN0

RA1

/
AN1

RA2/AN2/V

REF

-/CV

REF

RA3/AN3/V

REF

+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

V

SS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC1

/T

1

O

SI/CCP2

(1

)

RC2

/CCP1

RC3

/
S

CK/

S

CL

28-pin QFN

PIC

1

8F2X

1X

PIC18F2410
PIC18F2510

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2

(1)

RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V

DD

V

SS

RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

MCLR/V

PP

/RE3

RA0/AN0
RA1/AN1

RA2/AN2/V

REF

-/CV

REF

RA3/AN3/V

REF

+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

V

DD

V

SS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

(1)

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40-pin PDIP

PIC

1

8F4

X

1X

Document Outline

• Power Managed Modes:
• Peripheral Highlights:
• Flexible Oscillator Structure:
• Special Microcontroller Features:
• Pin Diagrams
• Pin Diagrams (Cont.�d)
• Table of Contents
• 1.0 Device Overview
  • 1.1 New Core Features
    • 1.1.1 nanoWatt Technology
    • 1.1.2 Multiple Oscillator Options and Features
  • 1.2 Other Special Features
  • 1.3 Details on Individual Family Members
    • TABLE 1-1: Device Features (PIC18F2410/2510/2515/2610)
    • TABLE 1-2: Device Features (PIC18F4410/4510/4515/4610)
    • FIGURE 1-1: PIC18F2410/2510/2515/2610 (28-Pin) Block Diagram
    • FIGURE 1-2: PIC18F4410/4510/4515/4610 (40/44-Pin) Block Diagram
    • TABLE 1-3: PIC18F2410/2510/2515/2610 Pinout I/O Descriptions
    • TABLE 1-4: PIC18F4410/4510/4515/4610 Pinout I/O Descriptions
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (XT, LP, HS or HSPLL Configuration)
    • TABLE 2-1: Capacitor Selection for Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
    • FIGURE 2-2: External Clock Input Operation (HS Oscillator Configuration)
  • 2.3 External Clock Input
    • FIGURE 2-3: External Clock Input Operation (EC Configuration)
    • FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
  • 2.4 RC Oscillator
    • FIGURE 2-5: RC Oscillator Mode
    • FIGURE 2-6: RCIO Oscillator Mode
  • 2.5 PLL Frequency Multiplier
    • 2.5.1 HSPLL Oscillator Mode
      • FIGURE 2-7: PLL Block Diagram (HS Mode)
    • 2.5.2 PLL and INTOSC
  • 2.6 Internal Oscillator Block
    • 2.6.1 INTIO Modes
    • 2.6.2 INTOSC Output Frequency
    • 2.6.3 OSCTUNE Register
    • 2.6.4 PLL in INTOSC Modes
    • 2.6.5 INTOSC Frequency Drift
      • Register 2-1: OSCTUNE: Oscillator Tuning Register
  • 2.7 Clock Sources and Oscillator Switching
    • FIGURE 2-8: PIC18F2X1X/4X1X Clock Diagram
    • 2.7.1 Oscillator Control Register
    • 2.7.2 Oscillator Transitions
      • Register 2-2: OSCCON: Oscillator Control Register
  • 2.8 Effects of Power Managed Modes on the Various Clock Sources
  • 2.9 Power-up Delays
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
• 3.0 Power Managed Modes
  • 3.1 Selecting Power Managed Modes
    • 3.1.1 Clock Sources
    • 3.1.2 Entering Power Managed Modes
      • TABLE 3-1: Power Managed Modes
    • 3.1.3 Clock Transitions and Status Indicators
    • 3.1.4 Multiple Sleep Commands
  • 3.2 Run Modes
    • 3.2.1 PRI_RUN Mode
    • 3.2.2 SEC_RUN Mode
      • FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode
      • FIGURE 3-2: Transition Timing from SEC_RUN Mode to PRI_RUN Mode (HSPLL)
    • 3.2.3 RC_RUN Mode
      • FIGURE 3-3: Transition Timing to RC_RUN Mode
      • FIGURE 3-4: Transition Timing from RC_RUN Mode to PRI_RUN Mode
  • 3.3 Sleep Mode
  • 3.4 Idle Modes
    • FIGURE 3-5: Transition Timing for Entry to Sleep Mode
    • FIGURE 3-6: Transition Timing for Wake from Sleep (HSPLL)
    • 3.4.1 PRI_IDLE Mode
    • 3.4.2 SEC_IDLE Mode
      • FIGURE 3-7: Transition Timing for Entry to Idle Mode
      • FIGURE 3-8: Transition Timing for Wake from Idle to Run Mode
    • 3.4.3 RC_IDLE Mode
  • 3.5 Exiting Idle and Sleep Modes
    • 3.5.1 Exit By Interrupt
    • 3.5.2 Exit By WDT Time-out
    • 3.5.3 Exit By Reset
    • 3.5.4 Exit Without an Oscillator Start-up Delay
      • TABLE 3-2: Exit Delay on Wake-up By Reset from Sleep Mode or Any Idle Mode (By Clock Sources)
• 4.0 Reset
  • 4.1 RCON Register
    • FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
    • Register 4-1: RCON: Reset Control Register
  • 4.2 Master Clear (MCLR)
  • 4.3 Power-on Reset (POR)
    • FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  • 4.4 Brown-out Reset (BOR)
    • 4.4.1 Software Enabled BOR
    • 4.4.2 Detecting BOR
    • 4.4.3 Disabling BOR in Sleep Mode
      • TABLE 4-1: BOR Configurations
  • 4.5 Device Reset Timers
    • 4.5.1 Power-up Timer (PWRT)
    • 4.5.2 Oscillator Start-up Timer (OST)
    • 4.5.3 PLL Lock Time-out
    • 4.5.4 Time-out Sequence
      • TABLE 4-2: Time-out in Various Situations
      • FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)
      • FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
      • FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
      • FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)
      • FIGURE 4-7: Time-out Sequence on POR W/PLL Enabled (MCLR Tied to Vdd)
  • 4.6 Reset State of Registers
    • TABLE 4-3: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • TABLE 4-4: Initialization Conditions for All Registers
• 5.0 Memory Organization
  • 5.1 Program Memory Organization
    • FIGURE 5-1: Program Memory Map and Stack for PIC18F2X1X/4X1X Devices
    • 5.1.1 Program Counter
    • 5.1.2 Return Address Stack
      • FIGURE 5-2: Return Address Stack and Associated Registers
      • Register 5-1: STKPTR: Stack Pointer Register
    • 5.1.3 Fast Register Stack
      • EXAMPLE 5-1: Fast Register Stack Code Example
    • 5.1.4 Look-up Tables in Program Memory
      • EXAMPLE 5-2: Computed GOTO Using an Offset Value
  • 5.2 PIC18 Instruction Cycle
    • 5.2.1 Clocking Scheme
    • 5.2.2 Instruction Flow/Pipelining
      • FIGURE 5-3: Clock/Instruction Cycle
      • EXAMPLE 5-3: Instruction Pipeline Flow
    • 5.2.3 Instructions In Program Memory
      • FIGURE 5-4: Instructions in Program Memory
    • 5.2.4 Two-Word Instructions
      • EXAMPLE 5-4: Two-Word Instructions
  • 5.3 Data Memory Organization
    • 5.3.1 Bank Select Register (BSR)
      • FIGURE 5-5: Data Memory Map for PIC18F2410/4410 Devices
      • FIGURE 5-6: Data Memory Map for PIC18F2510/4510 Devices
      • FIGURE 5-7: Data Memory Map for PIC18F2515/2610/4515/4610 Devices
      • FIGURE 5-8: Use of the Bank Select Register (Direct Addressing)
    • 5.3.2 Access Bank
    • 5.3.3 General Purpose Register File
    • 5.3.4 Special Function Registers
      • TABLE 5-1: Special Function Register Map for PIC18F2X1X/4X1X Devices
      • TABLE 5-2: Register File Summary (PIC18F2X1X/4X1X)
    • 5.3.5 Status Register
      • Register 5-2: Status Register
  • 5.4 Data Addressing Modes
    • 5.4.1 Inherent and Literal Addressing
    • 5.4.2 Direct Addressing
    • 5.4.3 Indirect Addressing
      • EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing
      • FIGURE 5-9: Indirect Addressing
  • 5.5 Data Memory and the Extended Instruction Set
    • 5.5.1 Indexed Addressing with Literal Offset
    • 5.5.2 Instructions Affected By Indexed Literal Offset Mode
      • FIGURE 5-10: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extend...
    • 5.5.3 Mapping the Access Bank in Indexed Literal Offset Addressing Mode
  • 5.6 PIC18 Instruction Execution and the Extended Instruction Set
    • FIGURE 5-11: Remapping the Access Bank with Indexed Literal Offset Addressing
• 6.0 Flash Program Memory
  • 6.1 Table Reads
    • FIGURE 6-1: Table Read Operation
  • 6.2 Control Registers
    • 6.2.1 TABLAT � Table Latch Register
    • 6.2.2 TBLPTR � Table Pointer Register
      • TABLE 6-1: Table Pointer Operations with TBLRD Instructions
  • 6.3 Reading the Flash Program Memory
    • FIGURE 6-2: Reads from Flash Program Memory
    • EXAMPLE 6-1: Reading a Flash Program Memory Word
    • TABLE 6-2: Registers Associated with Reading Program Flash Memory
• 7.0 8 X 8 Hardware Multiplier
  • 7.1 Introduction
  • 7.2 Operation
    • EXAMPLE 7-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 7-2: 8 x 8 Signed Multiply Routine
    • TABLE 7-1: Performance Comparison for Various Multiply Operations
    • EQUATION 7-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 7-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 7-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 7-4: 16 x 16 Signed Multiply Routine
• 8.0 Interrupts
  • FIGURE 8-1: PIC18 Interrupt Logic
  • 8.1 INTCON Registers
    • Register 8-1: INTCON Register
    • Register 8-2: INTCON2 Register
    • Register 8-3: INTCON3 Register
  • 8.2 PIR Registers
    • Register 8-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
    • Register 8-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
  • 8.3 PIE Registers
    • Register 8-6: PIE1: Peripheral Interrupt Enable Register 1
    • Register 8-7: PIE2: Peripheral Interrupt Enable Register 2
  • 8.4 IPR Registers
    • Register 8-8: IPR1: Peripheral Interrupt Priority Register 1
    • Register 8-9: IPR2: Peripheral Interrupt Priority Register 2
  • 8.5 RCON Register
    • Register 8-10: RCON Register
  • 8.6 INTn Pin Interrupts
  • 8.7 TMR0 Interrupt
  • 8.8 PORTB Interrupt-on-Change
  • 8.9 Context Saving During Interrupts
    • EXAMPLE 8-1: Saving Status, WREG and BSR Registers in RAM
• 9.0 I/O Ports
  • FIGURE 9-1: Generic I/O Port Operation
  • 9.1 PORTA, TRISA and LATA Registers
    • EXAMPLE 9-1: Initializing PORTA
    • TABLE 9-1: PORTA I/O Summary
    • TABLE 9-2: Summary of Registers Associated with PORTA
  • 9.2 PORTB, TRISB and LATB Registers
    • EXAMPLE 9-2: Initializing PORTB
    • TABLE 9-3: PORTB I/O Summary
    • TABLE 9-4: Summary of Registers Associated with PORTB
  • 9.3 PORTC, TRISC and LATC Registers
    • EXAMPLE 9-3: Initializing PORTC
    • TABLE 9-5: PORTC I/O Summary
    • TABLE 9-6: Summary of Registers Associated with PORTC
  • 9.4 PORTD, TRISD and LATD Registers
    • EXAMPLE 9-4: Initializing PORTD
    • TABLE 9-7: PORTD I/O Summary
    • TABLE 9-8: Summary of Registers Associated with PORTD
  • 9.5 PORTE, TRISE and LATE Registers
    • EXAMPLE 9-5: Initializing PORTE
    • 9.5.1 PORTE in 28-Pin Devices
      • Register 9-1: TRISE Register (40/44-pin Devices Only)
      • TABLE 9-9: PORTE I/O Summary
      • TABLE 9-10: Summary of Registers Associated with PORTE
  • 9.6 Parallel Slave Port
    • FIGURE 9-2: PORTD and PORTE Block Diagram (Parallel Slave Port)
    • FIGURE 9-3: Parallel Slave Port Write Waveforms
    • FIGURE 9-4: Parallel Slave Port Read Waveforms
    • TABLE 9-11: Registers Associated with Parallel Slave Port
• 10.0 Timer0 Module
  • Register 10-1: T0CON: Timer0 Control Register
  • 10.1 Timer0 Operation
  • 10.2 Timer0 Reads and Writes in 16-Bit Mode
    • FIGURE 10-1: Timer0 Block Diagram (8-Bit Mode)
    • FIGURE 10-2: Timer0 Block Diagram (16-Bit Mode)
  • 10.3 Prescaler
    • 10.3.1 Switching Prescaler Assignment
  • 10.4 Timer0 Interrupt
    • TABLE 10-1: Registers Associated with Timer0
• 11.0 Timer1 Module
  • Register 11-1: T1CON: Timer1 Control Register
  • 11.1 Timer1 Operation
    • FIGURE 11-1: Timer1 Block Diagram
    • FIGURE 11-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
  • 11.2 Timer1 16-Bit Read/Write Mode
  • 11.3 Timer1 Oscillator
    • FIGURE 11-3: External Components for the Timer1 LP Oscillator
    • TABLE 11-1: Capacitor Selection for the Timer Oscillator
    • 11.3.1 Using Timer1 as a Clock Source
    • 11.3.2 Low-Power Timer1 Option
    • 11.3.3 Timer1 Oscillator Layout Considerations
      • FIGURE 11-4: Oscillator Circuit with Grounded Guard Ring
  • 11.4 Timer1 Interrupt
  • 11.5 Resetting Timer1 Using the CCP Special Event Trigger
  • 11.6 Using Timer1 as a Real-Time Clock
    • EXAMPLE 11-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
    • TABLE 11-2: Registers Associated with Timer1 as a Timer/Counter
• 12.0 Timer2 Module
  • 12.1 Timer2 Operation
    • Register 12-1: T2CON: Timer2 Control Register
  • 12.2 Timer2 Interrupt
  • 12.3 Timer2 Output
    • FIGURE 12-1: Timer2 Block Diagram
    • TABLE 12-1: Registers Associated with Timer2 as a Timer/Counter
• 13.0 Timer3 Module
  • Register 13-1: T3CON: Timer3 Control Register
  • 13.1 Timer3 Operation
    • FIGURE 13-1: Timer3 Block Diagram
    • FIGURE 13-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
  • 13.2 Timer3 16-Bit Read/Write Mode
  • 13.3 Using the Timer1 Oscillator as the Timer3 Clock Source
  • 13.4 Timer3 Interrupt
  • 13.5 Resetting Timer3 Using the CCP Special Event Trigger
    • TABLE 13-1: Registers Associated with Timer3 as a Timer/Counter
• 14.0 Capture/Compare/PWM (CCP) Modules
  • Register 14-1: CCPXCON Register (CCP2 Module, CCP1 Module in 28-pin Devices)
  • 14.1 CCP Module Configuration
    • 14.1.1 CCP Modules and Timer Resources
      • TABLE 14-1: CCP Mode � Timer Resource
    • 14.1.2 CCP2 Pin Assignment
      • TABLE 14-2: Interactions Between CCP1 and CCP2 for Timer Resources
  • 14.2 Capture Mode
    • 14.2.1 CCP Pin Configuration
    • 14.2.2 Timer1/Timer3 Mode Selection
    • 14.2.3 Software Interrupt
    • 14.2.4 CCP Prescaler
      • EXAMPLE 14-1: Changing Between Capture Prescalers (CCP2 Shown)
      • FIGURE 14-1: Capture Mode Operation Block Diagram
  • 14.3 Compare Mode
    • 14.3.1 CCP Pin Configuration
    • 14.3.2 Timer1/Timer3 Mode Selection
    • 14.3.3 Software Interrupt Mode
    • 14.3.4 Special Event Trigger
      • FIGURE 14-2: Compare Mode Operation Block Diagram
      • TABLE 14-3: Registers Associated with Capture, Compare, Timer1 and Timer3
  • 14.4 PWM Mode
    • FIGURE 14-3: Simplified PWM Block Diagram
    • FIGURE 14-4: PWM Output
    • 14.4.1 PWM Period
      • EQUATION 14-1:
    • 14.4.2 PWM Duty Cycle
      • EQUATION 14-2:
      • EQUATION 14-3:
      • TABLE 14-4: Example PWM Frequencies and Resolutions at 40 MHz
    • 14.4.3 PWM Auto-Shutdown (CCP1 Only)
    • 14.4.4 Setup for PWM Operation
      • TABLE 14-5: Registers Associated with PWM and Timer2
• 15.0 Enhanced Capture/ Compare/PWM (ECCP) Module
  • Register 15-1: CCP1CON Register (ECCP1 Module, 40/44-pin Devices)
  • 15.1 ECCP Outputs and Configuration
    • 15.1.1 ECCP Modules and Timer Resources
  • 15.2 Capture and Compare Modes
    • 15.2.1 Special Event Trigger
  • 15.3 Standard PWM Mode
    • TABLE 15-1: Pin Assignments for Various ECCP1 Modes
  • 15.4 Enhanced PWM Mode
    • 15.4.1 PWM Period
      • EQUATION 15-1:
      • FIGURE 15-1: Simplified Block Diagram of the Enhanced PWM Module
    • 15.4.2 PWM Duty Cycle
      • EQUATION 15-2:
      • EQUATION 15-3:
    • 15.4.3 PWM Output Configurations
      • TABLE 15-2: Example PWM Frequencies and Resolutions at 40 MHz
      • FIGURE 15-2: PWM Output Relationships (Active-High State)
      • FIGURE 15-3: PWM Output Relationships (Active-Low State)
    • 15.4.4 Half-Bridge Mode
      • FIGURE 15-4: Half-Bridge PWM Output
      • FIGURE 15-5: Examples of Half-Bridge Output Mode Applications
    • 15.4.5 Full-Bridge Mode
      • FIGURE 15-6: Full-Bridge PWM Output
      • FIGURE 15-7: Example of Full-Bridge Application
      • FIGURE 15-8: PWM Direction Change
      • FIGURE 15-9: PWM Direction Change at Near 100% Duty Cycle
    • 15.4.6 Programmable Dead-Band Delay
    • 15.4.7 Enhanced PWM Auto-Shutdown
      • Register 15-2: PWM1CON: PWM Configuration Register
      • Register 15-3: ECCP1AS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register
    • 15.4.8 Start-up Considerations
      • FIGURE 15-10: PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled)
      • FIGURE 15-11: PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled)
    • 15.4.9 Setup for PWM Operation
    • 15.4.10 Operation in Power Managed Modes
    • 15.4.11 Effects of a Reset
      • TABLE 15-3: Registers Associated with ECCP1 Module and Timer1 to Timer3
• 16.0 Master Synchronous Serial Port (MSSP) Module
  • 16.1 MSSP Module Overview
  • 16.2 Control Registers
  • 16.3 SPI Mode
    • FIGURE 16-1: MSSP Block Diagram (SPI�Mode)
    • 16.3.1 Registers
      • Register 16-1: SSPSTAT: MSSP Status Register (SPI Mode)
      • Register 16-2: SSPCON1: MSSP Control Register 1 (SPI Mode)
    • 16.3.2 Operation
      • EXAMPLE 16-1: Loading the SSPBUF (SSPSR) Register
    • 16.3.3 Enabling SPI I/O
    • 16.3.4 Typical Connection
      • FIGURE 16-2: SPI� Master/Slave Connection
    • 16.3.5 Master Mode
      • FIGURE 16-3: SPI� Mode Waveform (Master Mode)
    • 16.3.6 Slave Mode
    • 16.3.7 Slave Select Synchronization
      • FIGURE 16-4: Slave Synchronization Waveform
      • FIGURE 16-5: SPI� Mode Waveform (Slave Mode with CKE = 0)
      • FIGURE 16-6: SPI� Mode Waveform (Slave Mode with CKE = 1)
    • 16.3.8 Operation in Power Managed Modes
    • 16.3.9 Effects of a Reset
    • 16.3.10 Bus Mode Compatibility
      • TABLE 16-1: SPI Bus Modes
      • TABLE 16-2: Registers Associated with SPI Operation
  • 16.4 I2C Mode
    • FIGURE 16-7: MSSP Block Diagram (I2C� Mode)
    • 16.4.1 Registers
      • Register 16-3: SSPSTAT: MSSP Status Register (I2C Mode) 
      • Register 16-4: SSPCON1: MSSP Control Register 1 (I2C Mode) 
      • Register 16-5: SSPCON2: MSSP Control Register 2 (I2C Mode)
    • 16.4.2 Operation
    • 16.4.3 Slave Mode
      • FIGURE 16-8: I2C� Slave Mode Timing with SEN = 0 (Reception, 7-Bit Address)
      • FIGURE 16-9: I2C� Slave Mode Timing (Transmission, 7-Bit Address)
      • FIGURE 16-10: I2C� Slave Mode Timing with SEN = 0 (Reception, 10-Bit Address)
      • FIGURE 16-11: I2C� Slave Mode Timing (Transmission, 10-Bit Address)
    • 16.4.4 Clock Stretching
      • FIGURE 16-12: Clock Synchronization Timing
      • FIGURE 16-13: I2C� Slave Mode Timing with SEN = 1 (Reception, 7-Bit Address)
      • FIGURE 16-14: I2C� Slave Mode Timing SEN = 1 (Reception, 10-Bit Address)
    • 16.4.5 General Call Address Support
      • FIGURE 16-15: Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode)
    • 16.4.6 Master Mode
      • FIGURE 16-16: MSSP Block Diagram (I2C� Master Mode)
    • 16.4.7 Baud Rate
      • FIGURE 16-17: Baud Rate Generator Block Diagram
      • TABLE 16-3: I2C� Clock Rate w/BRG
      • FIGURE 16-18: Baud Rate Generator Timing with Clock Arbitration
    • 16.4.8 I2C Master Mode Start Condition Timing
      • FIGURE 16-19: First Start Bit Timing
    • 16.4.9 I2C Master Mode Repeated Start Condition Timing
      • FIGURE 16-20: Repeat Start Condition Waveform
    • 16.4.10 I2C Master Mode Transmission
    • 16.4.11 I2C Master Mode Reception
      • FIGURE 16-21: I2C� Master Mode Waveform (Transmission, 7 or 10-Bit Address)
      • FIGURE 16-22: I2C� Master Mode Waveform (Reception, 7-Bit Address)
    • 16.4.12 Acknowledge Sequence Timing
    • 16.4.13 Stop Condition Timing
      • FIGURE 16-23: Acknowledge Sequence Waveform
      • FIGURE 16-24: Stop Condition Receive or Transmit Mode
    • 16.4.14 Sleep Operation
    • 16.4.15 Effects of a Reset
    • 16.4.16 Multi-Master Mode
    • 16.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
      • FIGURE 16-25: Bus Collision Timing for Transmit and Acknowledge
      • FIGURE 16-26: Bus Collision During Start Condition (SDA Only)
      • FIGURE 16-27: Bus Collision During Start Condition (SCL = 0)
      • FIGURE 16-28: BRG Reset Due to SDA Arbitration During Start Condition
      • FIGURE 16-29: Bus Collision During a Repeated Start Condition (Case 1)
      • FIGURE 16-30: Bus Collision During Repeated Start Condition (Case 2)
      • FIGURE 16-31: Bus Collision During a Stop Condition (Case 1)
      • FIGURE 16-32: Bus Collision During a Stop Condition (Case 2)
• 17.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)
  • Register 17-1: TXSTA: Transmit Status and Control Register
  • Register 17-2: RCSTA: Receive Status and Control Register
  • Register 17-3: BAUDCON: Baud Rate Control Register
  • 17.1 Baud Rate Generator (BRG)
    • 17.1.1 Operation in Power Managed Modes
    • 17.1.2 Sampling
      • TABLE 17-1: Baud Rate Formulas
      • EXAMPLE 17-1: Calculating Baud Rate Error
      • TABLE 17-2: Registers Associated With Baud Rate Generator
      • TABLE 17-3: Baud Rates for Asynchronous Modes
    • 17.1.3 Auto-Baud Rate Detect
      • TABLE 17-4: BRG Counter Clock Rates
      • FIGURE 17-1: Automatic Baud Rate Calculation
      • FIGURE 17-2: BRG Overflow Sequence
  • 17.2 EUSART Asynchronous Mode
    • 17.2.1 EUSART Asynchronous Transmitter
      • FIGURE 17-3: EUSART Transmit Block Diagram
      • FIGURE 17-4: Asynchronous Transmission
      • FIGURE 17-5: Asynchronous Transmission (Back to Back)
      • TABLE 17-5: Registers Associated with Asynchronous Transmission
    • 17.2.2 EUSART Asynchronous Receiver
    • 17.2.3 Setting Up 9-Bit Mode with Address Detect
      • FIGURE 17-6: EUSART Receive Block Diagram
      • FIGURE 17-7: Asynchronous Reception
      • TABLE 17-6: Registers Associated with Asynchronous Reception
    • 17.2.4 Auto-Wake-up on Sync Break Character
      • FIGURE 17-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation
      • FIGURE 17-9: Auto-Wake-up Bit (WUE) Timings During Sleep
    • 17.2.5 Break Character Sequence
    • 17.2.6 Receiving A Break Character
      • FIGURE 17-10: Send Break Character Sequence
  • 17.3 EUSART Synchronous Master Mode
    • 17.3.1 EUSART Synchronous Master Transmission
      • FIGURE 17-11: Synchronous Transmission
      • FIGURE 17-12: Synchronous Transmission (Through TXEN)
      • TABLE 17-7: Registers Associated with Synchronous Master Transmission
    • 17.3.2 EUSART Synchronous Master Reception
      • FIGURE 17-13: Synchronous Reception (Master Mode, SREN)
      • TABLE 17-8: Registers Associated with Synchronous Master Reception
  • 17.4 EUSART Synchronous Slave Mode
    • 17.4.1 EUSART Synchronous Slave Transmit
      • TABLE 17-9: Registers Associated with Synchronous Slave Transmission
    • 17.4.2 EUSART Synchronous Slave Reception
      • TABLE 17-10: Registers Associated with Synchronous Slave Reception
• 18.0 10-Bit Analog-to-Digital Converter (A/D) Module
  • Register 18-1: ADCON0: A/D Control Register 0
  • Register 18-2: ADCON1: A/D Control Register 1
  • Register 18-3: ADCON2: A/D Control Register 2
  • FIGURE 18-1: A/D Block Diagram
  • FIGURE 18-2: A/D Transfer Function
  • FIGURE 18-3: Analog Input Model
  • 18.1 A/D Acquisition Requirements
    • EQUATION 18-1: Acquisition Time
    • EQUATION 18-2: A/D Minimum Charging Time
    • EQUATION 18-3: Calculating the Minimum Required Acquisition Time
  • 18.2 Selecting and Configuring Acquisition Time
  • 18.3 Selecting the A/D Conversion Clock
    • TABLE 18-1: Tad vs. Device Operating Frequencies
  • 18.4 Operation in Power Managed Modes
  • 18.5 Configuring Analog Port Pins
  • 18.6 A/D Conversions
  • 18.7 Discharge
    • FIGURE 18-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
    • FIGURE 18-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
  • 18.8 Use of the CCP2 Trigger
    • TABLE 18-2: Registers Associated with A/D Operation
• 19.0 Comparator Module
  • Register 19-1: CMCON: Comparator Control Register
  • 19.1 Comparator Configuration
    • FIGURE 19-1: Comparator I/O Operating Modes
  • 19.2 Comparator Operation
  • 19.3 Comparator Reference
    • FIGURE 19-2: Single Comparator
    • 19.3.1 External Reference Signal
    • 19.3.2 Internal Reference Signal
  • 19.4 Comparator Response Time
  • 19.5 Comparator Outputs
    • FIGURE 19-3: Comparator Output Block Diagram
  • 19.6 Comparator Interrupts
  • 19.7 Comparator Operation During Sleep
  • 19.8 Effects of a Reset
  • 19.9 Analog Input Connection Considerations
    • FIGURE 19-4: Comparator Analog Input Model
    • TABLE 19-1: Registers Associated with Comparator Module
• 20.0 Comparator Voltage Reference Module
  • 20.1 Configuring the Comparator Voltage Reference
    • Register 20-1: CVRCON: Comparator Voltage Reference Control Register
    • FIGURE 20-1: Comparator Voltage Reference Block Diagram
  • 20.2 Voltage Reference Accuracy/Error
  • 20.3 Operation During Sleep
  • 20.4 Effects of a Reset
  • 20.5 Connection Considerations
    • FIGURE 20-2: Comparator Voltage Reference Output Buffer Example
    • TABLE 20-1: Registers Associated with Comparator Voltage Reference
• 21.0 High/Low-Voltage Detect (HLVD)
  • Register 21-1: HLVDCON: High/Low-Voltage Detect Control Register
  • 21.1 Operation
    • FIGURE 21-1: HLVD Module Block Diagram (with External Input)
  • 21.2 HLVD Setup
  • 21.3 Current Consumption
  • 21.4 HLVD Start-up Time
    • FIGURE 21-2: Low-Voltage Detect Operation (VDIRMAG = 0)
    • FIGURE 21-3: High-Voltage Detect Operation (VDIRMAG = 1)
  • 21.5 Applications
    • FIGURE 21-4: Typical High/Low-Voltage Detect Application
  • 21.6 Operation During Sleep
  • 21.7 Effects of a Reset
    • TABLE 21-1: Registers Associated with High/Low-Voltage Detect Module
• 22.0 Special Features of the CPU
  • 22.1 Configuration Bits
    • TABLE 22-1: Configuration Bits and Device IDs
    • Register 22-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
    • Register 22-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
    • Register 22-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
    • Register 22-4: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
    • Register 22-5: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
    • Register 22-6: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
    • Register 22-7: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
    • Register 22-8: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
    • Register 22-9: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
    • Register 22-10: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
    • Register 22-11: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
    • Register 22-12: Device ID Register 1 for PIC18F2X1X/4X1X Devices
    • Register 22-13: Device ID Register 2 for PIC18F2X1X/4X1X Devices
  • 22.2 Watchdog Timer (WDT)
    • 22.2.1 Control Register
      • FIGURE 22-1: WDT Block Diagram
      • Register 22-14: WDTCON: Watchdog Timer Control Register
      • TABLE 22-2: Summary of Watchdog Timer Registers
  • 22.3 Two-Speed Start-up
    • 22.3.1 Special Considerations for Using Two-Speed Start-up
      • FIGURE 22-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
  • 22.4 Fail-Safe Clock Monitor
    • FIGURE 22-3: FSCM Block Diagram
    • 22.4.1 FSCM and the Watchdog Timer
    • 22.4.2 Exiting Fail-Safe Operation
      • FIGURE 22-4: FSCM Timing Diagram
    • 22.4.3 FSCM Interrupts in Power Managed Modes
    • 22.4.4 POR or Wake From Sleep
  • 22.5 Program Verification and Code Protection
    • FIGURE 22-5: Code-Protected Program Memory for PIC18F2410/2510/4410/4510
    • FIGURE 22-6: Code-Protected Program Memory for PIC18F2515/2610/4515/4610
    • TABLE 22-3: Summary of Code Protection Registers
    • 22.5.1 Program Memory Code Protection
      • FIGURE 22-7: External Block Table Read (EBTRn) Disallowed (16-Kbyte and 32-Kbyte Devices)
      • FIGURE 22-8: External Block Table Read (EBTRn) Allowed (16-Kbyte and 32-Kbyte Devices)
      • FIGURE 22-9: External Block Table Read (EBTRn) Disallowed (48-Kbyte and 64-Kbyte Devices)
      • FIGURE 22-10: External Block Table Read (EBTRn) Allowed (48-Kbyte and 64-Kbyte Devices)
    • 22.5.2 Configuration Register Protection
  • 22.6 ID Locations
  • 22.7 In-Circuit Serial Programming
  • 22.8 In-Circuit Debugger
    • TABLE 22-4: Debugger Resources
  • 22.9 Single-Supply ICSP Programming
• 23.0 Instruction Set Summary
  • 23.1 Standard Instruction Set
    • TABLE 23-1: Opcode Field Descriptions
    • FIGURE 23-1: General Format for Instructions
    • TABLE 23-2: PIC18FXXXX Instruction Set
    • 23.1.1 Standard Instruction Set
  • 23.2 Extended Instruction Set
    • 23.2.1 Extended Instruction Syntax
      • TABLE 23-3: Extensions to the PIC18 Instruction Set
    • 23.2.2 Extended Instruction Set
    • 23.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode
    • 23.2.4 Considerations When Enabling the Extended Instruction Set
    • 23.2.5 Special Considerations with Microchip MPLAB� IDE Tools
• 24.0 Development Support
  • 24.1 MPLAB Integrated Development Environment Software
  • 24.2 MPASM Assembler
  • 24.3 MPLAB C17 and MPLAB C18 C Compilers
  • 24.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 24.5 MPLAB C30 C Compiler
  • 24.6 MPLAB ASM30 Assembler, Linker and Librarian
  • 24.7 MPLAB SIM Software Simulator
  • 24.8 MPLAB SIM30 Software Simulator
  • 24.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
  • 24.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
  • 24.11 MPLAB ICD 2 In-Circuit Debugger
  • 24.12 PRO MATE II Universal Device Programmer
  • 24.13 MPLAB PM3 Device Programmer
  • 24.14 PICSTART Plus Development Programmer
  • 24.15 PICDEM 1 PICmicro Demonstration Board
  • 24.16 PICDEM.net Internet/Ethernet Demonstration Board
  • 24.17 PICDEM 2 Plus Demonstration Board
  • 24.18 PICDEM 3 PIC16C92X Demonstration Board
  • 24.19 PICDEM 4 8/14/18-Pin Demonstration Board
  • 24.20 PICDEM 17 Demonstration Board
  • 24.21 PICDEM 18R PIC18C601/801 Demonstration Board
  • 24.22 PICDEM LIN PIC16C43X Demonstration Board
  • 24.23 PICkitTM 1 Flash Starter Kit
  • 24.24 PICDEM USB PIC16C7X5 Demonstration Board
  • 24.25 Evaluation and Programming Tools
• 25.0 Electrical Characteristics
  • Absolute Maximum Ratings(�)
    • FIGURE 25-1: PIC18F2X1X/4X1X Voltage-Frequency Graph (Industrial)
    • FIGURE 25-2: PIC18F2X1X/4X1X Voltage-Frequency Graph (Extended)
    • FIGURE 25-3: PIC18LF2X1X/4X1X Voltage-Frequency Graph (Industrial)
  • 25.1 DC Characteristics: Supply Voltage PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial)
  • 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4...
  • 25.3 DC Characteristics: PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial)
    • TABLE 25-1: Memory Programming Requirements
    • TABLE 25-2: Comparator Specifications
    • TABLE 25-3: Voltage Reference Specifications
    • FIGURE 25-4: High/Low-Voltage Detect Characteristics
    • TABLE 25-4: High/Low-Voltage Detect Characteristics
  • 25.4 AC (Timing) Characteristics
    • 25.4.1 Timing Parameter Symbology
    • 25.4.2 Timing Conditions
      • TABLE 25-5: Temperature and Voltage Specifications � AC
      • FIGURE 25-5: Load Conditions for Device Timing Specifications
    • 25.4.3 Timing Diagrams and Specifications
      • FIGURE 25-6: External Clock Timing (All Modes Except PLL)
      • TABLE 25-6: External Clock Timing Requirements
      • TABLE 25-7: PLL Clock Timing Specifications (Vdd = 4.2V to 5.5V)
      • TABLE 25-8: AC Characteristics: Internal RC Accuracy PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1...
      • FIGURE 25-7: CLKO and I/O Timing
      • TABLE 25-9: CLKO and I/O Timing Requirements
      • FIGURE 25-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
      • FIGURE 25-9: Brown-out Reset Timing
      • TABLE 25-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...
      • FIGURE 25-10: Timer0 and Timer1 External Clock Timings
      • TABLE 25-11: Timer0 and Timer1 External Clock Requirements
      • FIGURE 25-11: Capture/Compare/PWM Timings (All CCP Modules)
      • TABLE 25-12: Capture/Compare/PWM Requirements (All CCP Modules)
      • FIGURE 25-12: Parallel Slave Port Timing (PIC18F4410/4510/4515/4610)
      • TABLE 25-13: Parallel Slave Port Requirements (PIC18F4410/4510/4515/4610)
      • FIGURE 25-13: Example SPI� Master Mode Timing (CKE=0)
      • TABLE 25-14: Example SPI� Mode Requirements (Master Mode, CKE=0)
      • FIGURE 25-14: Example SPI� Master Mode Timing (CKE=1)
      • TABLE 25-15: Example SPI� Mode Requirements (Master Mode, CKE=1)
      • FIGURE 25-15: Example Spi� Slave Mode Timing (CKE=0)
      • TABLE 25-16: Example SPI� Mode Requirements (Slave Mode Timing, CKE=0)
      • FIGURE 25-16: Example SPI� Slave Mode Timing (CKE=1)
      • TABLE 25-17: Example SPI� Slave Mode Requirements (CKE=1)
      • FIGURE 25-17: I2C� Bus Start/Stop Bits Timing
      • TABLE 25-18: I2C� Bus Start/Stop Bits Requirements (Slave Mode)
      • FIGURE 25-18: I2C� Bus Data Timing
      • TABLE 25-19: I2C� Bus Data Requirements (Slave Mode)
      • FIGURE 25-19: Master SSP I2C� Bus Start/Stop Bits Timing Waveforms
      • TABLE 25-20: Master SSP I2C� Bus Start/Stop Bits Requirements
      • FIGURE 25-20: Master SSP I2C� Bus Data Timing
      • TABLE 25-21: Master SSP I2C� Bus Data Requirements
      • FIGURE 25-21: USART Synchronous Transmission (Master/Slave) Timing
      • TABLE 25-22: USART Synchronous Transmission Requirements
      • FIGURE 25-22: USART Synchronous Receive (Master/Slave) Timing
      • TABLE 25-23: USART Synchronous Receive Requirements
      • TABLE 25-24: A/D Converter Characteristics: PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Indust...
      • FIGURE 25-23: A/D Conversion Timing
      • TABLE 25-25: A/D Conversion Requirements
• 26.0 DC and AC Characteristics Graphs And Tables
• 27.0 Packaging Information
  • 27.1 Package Marking Information
  • 27.1 Package Marking Information (Continued)
  • 27.2 Package Details
  • 28-Lead Skinny Plastic Dual In-line (SP) � 300 mil Body (PDIP)
  • 28-Lead Plastic Small Outline (SO) �Wide, 300 mil Body (SOIC)
  • 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) � With 0.55 mm Contact Length (S...
  • 40-Lead Plastic Dual In-line (P) � 600 mil Body (PDIP)
  • 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
• Appendix A: Revision History
  • Revision A (June 2004)
• Appendix B: Device Differences
  • TABLE B-1: Device Differences (PIC18F2410/2510/2515/2610)
  • TABLE B-2: Device Differences (PIC18F4410/4510/4515/4610)
• Appendix C: Conversion Considerations
• Appendix D: Migration From Baseline to Enhanced Devices
• Appendix E: Migration From Mid-Range to Enhanced Devices
• Appendix F: Migration From High-End to Enhanced Devices
• INDEX
• On-Line Support
  • Connecting to the Microchip Internet Web Site
• Systems Information and Upgrade Hot Line
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• PIC18F2X1X/4X1X Product Identification System
• Worldwide Sales and Service