Document Outline

• Power Managed Modes:
• Flexible Oscillator Structure:
• Special Microcontroller Features:
• Peripheral Highlights:
• ECAN Module Features:
• Pin Diagrams
• Pin Diagrams (Continued)
• Table of Contents
• 1.0 Device Overview
  • 1.1 New Core Features
    • 1.1.1 nanoWatt Technology
    • 1.1.2 Multiple Oscillator Options and Features
  • 1.2 Other Special Features
  • 1.3 Details on Individual Family Members
    • TABLE 1-1: Device Features
    • FIGURE 1-1: PIC18F2585/2680 (28-Pin) Block Diagram
    • FIGURE 1-2: PIC18F4585/4680 (40/44-Pin) Block Diagram
    • TABLE 1-2: PIC18f2585/2680 Pinout I/O Descriptions
    • TABLE 1-3: PIC18F4585/4680 Pinout I/O Descriptions
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (XT, LP, HS or HSPLL Configuration)
    • TABLE 2-1: Capacitor Selection for Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
    • FIGURE 2-2: External Clock Input Operation (HS Oscillator Configuration)
  • 2.3 External Clock Input
    • FIGURE 2-3: External Clock Input Operation (EC Configuration)
    • FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
  • 2.4 RC Oscillator
    • FIGURE 2-5: RC Oscillator Mode
    • FIGURE 2-6: RCIO Oscillator Mode
  • 2.5 PLL Frequency Multiplier
    • 2.5.1 HSPLL Oscillator Mode
      • FIGURE 2-7: PLL Block Diagram (HS Mode)
    • 2.5.2 PLL and INTOSC
  • 2.6 Internal Oscillator Block
    • 2.6.1 INTIO Modes
    • 2.6.2 INTOSC Output Frequency
    • 2.6.3 OSCTUNE Register
    • 2.6.4 PLL in INTOSC Modes
    • 2.6.5 INTOSC Frequency Drift
      • Register 2-1: OSCTUNE: Oscillator Tuning Register
  • 2.7 Clock Sources and Oscillator Switching
    • FIGURE 2-8: PIC18F2585/2680/4585/4680 Clock Diagram
    • 2.7.1 Oscillator Control Register
    • 2.7.2 Oscillator Transitions
      • Register 2-2: OSCCON: Oscillator Control Register
  • 2.8 Effects of Power Managed Modes on the Various Clock Sources
  • 2.9 Power-up Delays
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
• 3.0 Power Managed Modes
  • 3.1 Selecting Power Managed Modes
    • 3.1.1 Clock Sources
    • 3.1.2 Entering Power Managed Modes
      • TABLE 3-1: Power Managed Modes
    • 3.1.3 Clock Transitions And Status Indicators
    • 3.1.4 Multiple Sleep Commands
  • 3.2 Run Modes
    • 3.2.1 PRI_RUN Mode
    • 3.2.2 SEC_RUN Mode
      • FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode
      • FIGURE 3-2: Transition Timing from SEC_RUN Mode to PRI_RUN Mode (HSPLL)
    • 3.2.3 RC_RUN Mode
      • FIGURE 3-3: Transition Timing to RC_RUN Mode
      • FIGURE 3-4: Transition Timing from RC_RUN Mode to PRI_RUN Mode
  • 3.3 Sleep Mode
  • 3.4 Idle Modes
    • FIGURE 3-5: Transition Timing for Entry to Sleep Mode
    • FIGURE 3-6: Transition Timing for Wake from Sleep (HSPLL)
    • 3.4.1 PRI_IDLE Mode
    • 3.4.2 SEC_IDLE Mode
      • FIGURE 3-7: Transition Timing for Entry to Idle Mode
      • FIGURE 3-8: Transition Timing for Wake from Idle to Run Mode
    • 3.4.3 RC_IDLE Mode
  • 3.5 Exiting Idle and Sleep Modes
    • 3.5.1 Exit By Interrupt
    • 3.5.2 Exit By WDT Time-out
    • 3.5.3 Exit By Reset
    • 3.5.4 Exit Without an Oscillator Start-up Delay
      • TABLE 3-2: Exit Delay on Wake-up By Reset from Sleep Mode or Any Idle Mode (By Clock Sources)
• 4.0 Reset
  • 4.1 RCON Register
    • FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
    • Register 4-1: RCON: Reset Control Register
  • 4.2 Master Clear Reset (MCLR)
  • 4.3 Power-on Reset (POR)
    • FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  • 4.4 Brown-out Reset (BOR)
    • 4.4.1 Software Enabled BOR
    • 4.4.2 Detecting BOR
    • 4.4.3 Disabling BOR in Sleep Mode
      • TABLE 4-1: BOR Configurations
  • 4.5 Device Reset Timers
    • 4.5.1 Power-up Timer (PWRT)
    • 4.5.2 Oscillator Start-up Timer (OST)
    • 4.5.3 PLL Lock Time-out
    • 4.5.4 Time-out Sequence
      • TABLE 4-2: Time-out in Various Situations
      • FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)
      • FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
      • FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
      • FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)
      • FIGURE 4-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)
  • 4.6 Reset State of Registers
    • TABLE 4-3: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • TABLE 4-4: Initialization Conditions for All Registers
• 5.0 Memory Organization
  • 5.1 Program Memory Organization
    • FIGURE 5-1: Program Memory Map and Stack for PIC18F2585/2680/4585/4680 Devices
    • 5.1.1 Program Counter
    • 5.1.2 Return Address Stack
      • FIGURE 5-2: Return Address Stack and Associated Registers
      • Register 5-1: STKPTR: Stack Pointer Register
    • 5.1.3 Fast Register Stack
      • EXAMPLE 5-1: Fast Register Stack Code Example
    • 5.1.4 Look-up Tables in Program Memory
      • EXAMPLE 5-2: Computed GOTO Using An Offset Value
  • 5.2 PIC18 Instruction Cycle
    • 5.2.1 Clocking Scheme
    • 5.2.2 Instruction Flow/Pipelining
      • FIGURE 5-3: Clock/Instruction Cycle
      • EXAMPLE 5-3: Instruction Pipeline Flow
    • 5.2.3 Instructions in Program Memory
      • FIGURE 5-4: Instructions in Program Memory
    • 5.2.4 Two-Word Instructions
      • EXAMPLE 5-4: Two-Word Instructions
  • 5.3 Data Memory Organization
    • 5.3.1 Bank Select Register (BSR)
      • FIGURE 5-5: Data Memory Map for PIC18F2585/2680/4585/4680 Devices
      • FIGURE 5-6: Use of the Bank Select Register (Direct Addressing)
    • 5.3.2 Access Bank
    • 5.3.3 General Purpose Register File
    • 5.3.4 Special Function Registers
      • TABLE 5-1: Special Function Register Map for PIC18F2585/2680/4585/4680 Devices
      • TABLE 5-2: Register File Summary (PIC18F2585/2680/4585/4680)
    • 5.3.5 Status Register
      • Register 5-2: Status Register
  • 5.4 Data Addressing Modes
    • 5.4.1 Inherent and Literal Addressing
    • 5.4.2 Direct Addressing
    • 5.4.3 Indirect Addressing
      • EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing
      • FIGURE 5-7: Indirect Addressing
  • 5.5 Program Memory and the Extended Instruction Set
  • 5.6 Data Memory and the Extended Instruction Set
    • 5.6.1 Indexed Addressing with Literal Offset
    • 5.6.2 Instructions Affected By Indexed Literal Offset Mode
      • FIGURE 5-8: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extende...
    • 5.6.3 Mapping the Access Bank in Indexed Literal Offset Mode
    • 5.6.4 BSR in Indexed Literal Offset Mode
      • FIGURE 5-9: Remapping the Access Bank with Indexed Literal Offset Addressing
• 6.0 Flash Program Memory
  • 6.1 Table Reads and Table Writes
    • FIGURE 6-1: Table Read Operation
    • FIGURE 6-2: Table Write Operation
  • 6.2 Control Registers
    • 6.2.1 EECON1 and EECON2 Registers
      • Register 6-1: EECON1: Data EEPROM Control Register 1
    • 6.2.2 TABLAT � Table Latch Register
    • 6.2.3 TBLPTR � Table Pointer Register
    • 6.2.4 Table Pointer Boundaries
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions
      • FIGURE 6-3: Table Pointer Boundaries Based on Operation
  • 6.3 Reading the Flash Program Memory
    • FIGURE 6-4: Reads From Flash Program Memory
    • EXAMPLE 6-1: Reading a Flash Program Memory Word
  • 6.4 Erasing Flash Program Memory
    • 6.4.1 Flash Program Memory Erase Sequence
      • EXAMPLE 6-2: Erasing a Flash Program Memory Row
  • 6.5 Writing to Flash Program Memory
    • FIGURE 6-5: Table Writes to Flash Program Memory
    • 6.5.1 Flash Program Memory Write Sequence
      • EXAMPLE 6-3: Writing to Flash Program Memory
      • EXAMPLE 6-3: Writing to Flash Program Memory (Continued)
    • 6.5.2 Write Verify
    • 6.5.3 Unexpected Termination of Write Operation
    • 6.5.4 Protection Against Spurious Writes
  • 6.6 Flash Program Operation During Code Protection
    • TABLE 6-2: Registers Associated with Program Flash Memory
• 7.0 Data EEPROM Memory
  • 7.1 EEADR and EEADRH Registers
  • 7.2 EECON1 and EECON2 Registers
    • Register 7-1: EECON1: Data EEPROM Control Register 1
  • 7.3 Reading the Data EEPROM Memory
  • 7.4 Writing to the Data EEPROM Memory
  • 7.5 Write Verify
    • EXAMPLE 7-1: Data EEPROM Read
    • EXAMPLE 7-2: Data EEPROM Write
  • 7.6 Operation During Code-Protect
  • 7.7 Protection Against Spurious Write
  • 7.8 Using the Data EEPROM
    • EXAMPLE 7-3: Data EEPROM Refresh Routine
    • TABLE 7-1: Registers Associated with Data EEPROM Memory
• 8.0 8 x 8 Hardware Multiplier
  • 8.1 Introduction
  • 8.2 Operation
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
    • TABLE 8-1: Performance Comparison For Various Multiply Operations
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
• 9.0 Interrupts
  • FIGURE 9-1: Interrupt Logic
  • 9.1 INTCON Registers
    • Register 9-1: INTCON: Interrupt Control Register
    • Register 9-2: INTCON2: Interrupt Control Register 2
    • Register 9-3: INTCON3: Interrupt Control Register 3
  • 9.2 PIR Registers
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
    • Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3
  • 9.3 PIE Registers
    • Register 9-7: PIE1: Peripheral Interrupt Enable Register 1
    • Register 9-8: PIE2: Peripheral Interrupt Enable Register 2
    • Register 9-9: PIE3: Peripheral Interrupt Enable Register 3
  • 9.4 IPR Registers
    • Register 9-10: IPR1: Peripheral Interrupt Priority Register 1
    • Register 9-11: IPR2: Peripheral Interrupt Priority Register 2
    • Register 9-12: IPR3: Peripheral Interrupt Priority Register 3
  • 9.5 RCON Register
    • Register 9-13: RCON: Reset Control Register
  • 9.6 INTn Pin Interrupts
  • 9.7 TMR0 Interrupt
  • 9.8 PORTB Interrupt-on-Change
  • 9.9 Context Saving During Interrupts
    • EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM
• 10.0 I/O Ports
  • FIGURE 10-1: Generic I/O Port Operation
  • 10.1 PORTA, TRISA and LATA Registers
    • EXAMPLE 10-1: Initializing PORTA
    • TABLE 10-1: PORTA I/O Summary
    • TABLE 10-2: Summary of Registers Associated with PORTA
  • 10.2 PORTB, TRISB and LATB Registers
    • EXAMPLE 10-2: Initializing PORTB
    • TABLE 10-3: PORTB I/O Summary
    • TABLE 10-4: Summary of Registers Associated with PORTB
  • 10.3 PORTC, TRISC and LATC Registers
    • EXAMPLE 10-3: Initializing PORTC
    • TABLE 10-5: PORTC I/O Summary
    • TABLE 10-6: Summary of Registers Associated with PORTC
  • 10.4 PORTD, TRISD and LATD Registers
    • EXAMPLE 10-4: Initializing PORTD
    • TABLE 10-7: PORTD I/O Summary
    • TABLE 10-8: Summary of Registers Associated with PORTD
  • 10.5 PORTE, TRISE and LATE Registers
    • EXAMPLE 10-5: Initializing PORTE
    • 10.5.1 PORTE in 28-Pin Devices
      • Register 10-1: TRISE Register (PIC18F4X8X Devices Only)
      • TABLE 10-9: PORTE I/O Summary
      • TABLE 10-10: Summary of Registers Associated with PORTE
  • 10.6 Parallel Slave Port
    • FIGURE 10-2: PORTD and PORTE Block Diagram (Parallel Slave Port)
    • FIGURE 10-3: Parallel Slave Port Write Waveforms
    • FIGURE 10-4: Parallel Slave Port Read Waveforms
    • TABLE 10-11: Registers Associated with Parallel Slave Port
• 11.0 Timer0 Module
  • Register 11-1: T0CON: Timer0 Control Register
  • 11.1 Timer0 Operation
  • 11.2 Timer0 Reads and Writes in 16-Bit Mode
    • FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)
    • FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)
  • 11.3 Prescaler
    • 11.3.1 Switching Prescaler Assignment
  • 11.4 Timer0 Interrupt
    • TABLE 11-1: Registers Associated with Timer0
• 12.0 Timer1 Module
  • Register 12-1: T1CON: Timer1 Control Register
  • 12.1 Timer1 Operation
    • FIGURE 12-1: Timer1 Block Diagram
    • FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
  • 12.2 Timer1 16-Bit Read/Write Mode
  • 12.3 Timer1 Oscillator
    • FIGURE 12-3: External Components for the Timer1 LP Oscillator
    • TABLE 12-1: Capacitor Selection for the Timer Oscillator(1,2,3,4)
    • 12.3.1 Using Timer1 as a Clock Source
    • 12.3.2 Low-Power Timer1 Option
    • 12.3.3 Timer1 Oscillator Layout Considerations
      • FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring
  • 12.4 Timer1 Interrupt
  • 12.5 Resetting Timer1 Using the CCP1 Special Event Trigger
  • 12.6 Using Timer1 as a Real-Time Clock
    • EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
• 13.0 Timer2 Module
  • 13.1 Timer2 Operation
    • Register 13-1: T2CON: Timer2 Control Register
  • 13.2 Timer2 Interrupt
  • 13.3 TMR2 Output
    • FIGURE 13-1: Timer2 Block Diagram
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
• 14.0 Timer3 Module
  • Register 14-1: T3CON: Timer3 Control Register
  • 14.1 Timer3 Operation
    • FIGURE 14-1: Timer3 Block Diagram
    • FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
  • 14.2 Timer3 16-Bit Read/Write Mode
  • 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source
  • 14.4 Timer3 Interrupt
  • 14.5 Resetting Timer3 Using the ECCP1 Special Event Trigger
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
• 15.0 Capture/Compare/PWM (CCP1) Modules
  • Register 15-1: CCP1CON: Capture/Compare/PWM Control Register
  • 15.1 CCP1 Module Configuration
    • 15.1.1 CCP1 Modules and Timer Resources
      • TABLE 15-1: CCP1 Mode � Timer Resource
      • TABLE 15-2: Interactions Between CCP1 and ECCP1 for Timer Resources
  • 15.2 Capture Mode
    • 15.2.1 CCP1 Pin Configuration
    • 15.2.2 Timer1/Timer3 Mode Selection
    • 15.2.3 Software Interrupt
    • 15.2.4 CCP1 Prescaler
    • 15.2.5 CAN Message Time-Stamp
      • EXAMPLE 15-1: Changing Between Capture Prescalers
      • FIGURE 15-1: Capture Mode Operation Block Diagram
  • 15.3 Compare Mode
    • 15.3.1 CCP1 Pin Configuration
    • 15.3.2 Timer1/Timer3 Mode Selection
    • 15.3.3 Software Interrupt Mode
    • 15.3.4 Special Event Trigger
      • FIGURE 15-2: Compare Mode Operation Block Diagram
      • TABLE 15-3: Registers Associated with Capture, Compare, Timer1 and Timer3
  • 15.4 PWM Mode
    • FIGURE 15-3: Simplified PWM Block Diagram
    • FIGURE 15-4: PWM Output
    • 15.4.1 PWM Period
      • EQUATION 15-1:
    • 15.4.2 PWM Duty Cycle
      • EQUATION 15-2:
      • EQUATION 15-3:
      • TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz
    • 15.4.3 PWM Auto-Shutdown (ECCP1 Only)
    • 15.4.4 Setup for PWM Operation
      • TABLE 15-5: Registers Associated with PWM and Timer2
• 16.0 Enhanced Capture/Compare/PWM (ECCP1) Module
  • Register 16-1: ECCP1CON Register (ECCP1 Module, PIC18F4585/4680 Devices)
  • 16.1 ECCP1 Outputs and Configuration
    • 16.1.1 ECCP1 Modules and Timer Resources
  • 16.2 Capture and Compare Modes
    • 16.2.1 Special Event Trigger
  • 16.3 Standard PWM Mode
    • TABLE 16-1: Pin Assignments for Various ECCP1 Modes
  • 16.4 Enhanced PWM Mode
    • 16.4.1 PWM Period
      • EQUATION 16-1:
      • FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module
    • 16.4.2 PWM Duty Cycle
      • EQUATION 16-2:
      • EQUATION 16-3:
    • 16.4.3 PWM Output Configurations
      • TABLE 16-2: Example PWM Frequencies and Resolutions at 40 MHz
      • FIGURE 16-2: PWM Output Relationships (Active-High State)
      • FIGURE 16-3: PWM Output Relationships (Active-Low State)
    • 16.4.4 Half-Bridge Mode
      • FIGURE 16-4: Half-Bridge PWM Output
      • FIGURE 16-5: Examples of Half-Bridge Output Mode Applications
    • 16.4.5 Full-Bridge Mode
      • FIGURE 16-6: Full-Bridge PWM Output
      • FIGURE 16-7: Example of Full-Bridge Application
      • FIGURE 16-8: PWM Direction Change
      • FIGURE 16-9: PWM Direction Change at Near 100% Duty Cycle
    • 16.4.6 Programmable Dead-Band Delay
    • 16.4.7 Enhanced PWM Auto-Shutdown
      • Register 16-2: ECCP1DEL: PWM Configuration Register
      • Register 16-3: ECCP1AS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register
    • 16.4.8 Start-up Considerations
      • FIGURE 16-10: PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled)
      • FIGURE 16-11: PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled)
    • 16.4.9 Setup for PWM Operation
    • 16.4.10 Effects of a Reset
      • TABLE 16-3: Registers Associated with ECCP1 Module and Timer1 to Timer3
• 17.0 Master Synchronous Serial Port (MSSP) Module
  • 17.1 Master SSP (MSSP) Module Overview
  • 17.2 Control Registers
  • 17.3 SPI Mode
    • FIGURE 17-1: MSSP Block Diagram (SPI�Mode)
    • 17.3.1 Registers
      • Register 17-1: SSPSTAT: MSSP Status Register (SPI Mode)
      • Register 17-2: SSPCON1: MSSP Control Register 1 (SPI Mode)
    • 17.3.2 Operation
      • EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register
    • 17.3.3 Enabling SPI I/O
    • 17.3.4 Typical Connection
      • FIGURE 17-2: SPI� Master/Slave Connection
    • 17.3.5 Master Mode
      • FIGURE 17-3: SPI� Mode Waveform (Master Mode)
    • 17.3.6 Slave Mode
    • 17.3.7 Slave Select Synchronization
      • FIGURE 17-4: Slave Synchronization Waveform
      • FIGURE 17-5: SPI� Mode Waveform (Slave Mode with CKE = 0)
      • FIGURE 17-6: SPI� Mode Waveform (Slave Mode with CKE = 1)
    • 17.3.8 Operation in Power Managed Modes
    • 17.3.9 Effects of a Reset
    • 17.3.10 Bus Mode Compatibility
      • TABLE 17-1: SPI� Bus Modes
      • TABLE 17-2: Registers Associated with SPI� Operation
  • 17.4 I2C Mode
    • FIGURE 17-7: MSSP Block Diagram (I2C� Mode)
    • 17.4.1 Registers
      • Register 17-3: SSPSTAT: MSSP Status Register (I2C Mode) 
      • Register 17-4: SSPCON1: MSSP Control Register 1 (I2C Mode) 
      • Register 17-5: SSPCON2: MSSP Control Register 2 (I2C Mode)
    • 17.4.2 Operation
    • 17.4.3 Slave Mode
      • FIGURE 17-8: I2C� Slave Mode Timing with SEN = 0 (Reception, 7-Bit Address)
      • FIGURE 17-9: I2C� Slave Mode Timing (Transmission, 7-Bit Address)
      • FIGURE 17-10: I2C� Slave Mode Timing with SEN = 0 (Reception, 10-Bit Address)
      • FIGURE 17-11: I2C� Slave Mode Timing (Transmission, 10-Bit Address)
    • 17.4.4 Clock Stretching
      • FIGURE 17-12: Clock Synchronization Timing
      • FIGURE 17-13: I2C� Slave Mode Timing with SEN = 1 (Reception, 7-Bit Address)
      • FIGURE 17-14: I2C� Slave Mode Timing SEN = 1 (Reception, 10-Bit Address)
    • 17.4.5 General Call Address Support
      • FIGURE 17-15: Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode)
    • 17.4.6 Master Mode
      • FIGURE 17-16: MSSP Block Diagram (I2C� Master Mode)
    • 17.4.7 Baud Rate
      • FIGURE 17-17: Baud Rate Generator Block Diagram
      • TABLE 17-3: I2C� Clock Rate w/BRG
      • FIGURE 17-18: Baud Rate Generator Timing with Clock Arbitration
    • 17.4.8 I2C Master Mode Start Condition Timing
      • FIGURE 17-19: First Start Bit Timing
    • 17.4.9 I2C Master Mode Repeated Start Condition Timing
      • FIGURE 17-20: Repeat Start Condition Waveform
    • 17.4.10 I2C Master Mode Transmission
    • 17.4.11 I2C Master Mode Reception
      • FIGURE 17-21: I2C� Master Mode Waveform (Transmission, 7 or 10-Bit Address)
      • FIGURE 17-22: I2C� Master Mode Waveform (Reception, 7-Bit Address)
    • 17.4.12 Acknowledge Sequence Timing
    • 17.4.13 Stop Condition Timing
      • FIGURE 17-23: Acknowledge Sequence Waveform
      • FIGURE 17-24: Stop Condition Receive or Transmit Mode
    • 17.4.14 Sleep Operation
    • 17.4.15 Effect of a Reset
    • 17.4.16 Multi-Master Mode
    • 17.4.17 Multi-Master Communication, Bus Collision and Bus Arbitration
      • FIGURE 17-25: Bus Collision Timing for Transmit and Acknowledge
      • FIGURE 17-26: Bus Collision During Start Condition (SDA Only)
      • FIGURE 17-27: Bus Collision During Start Condition (SCL = 0)
      • FIGURE 17-28: BRG Reset Due to SDA Arbitration During Start Condition
      • FIGURE 17-29: Bus Collision During a Repeated Start Condition (Case 1)
      • FIGURE 17-30: Bus Collision During a Repeated Start Condition (Case 2)
      • FIGURE 17-31: Bus Collision During a Stop Condition (Case 1)
      • FIGURE 17-32: Bus Collision During a Stop Condition (Case 2)
• 18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)
  • Register 18-1: TXSTA: Transmit Status and Control Register
  • Register 18-2: RCSTA: Receive Status and Control Register
  • Register 18-3: BAUDCON: Baud Rate Control Register
  • 18.1 Baud Rate Generator (BRG)
    • 18.1.1 Operation in Power Managed Modes
    • 18.1.2 Sampling
      • TABLE 18-1: Baud Rate Formulas
      • EXAMPLE 18-1: Calculating Baud Rate Error
      • TABLE 18-2: Registers Associated with Baud Rate Generator
      • TABLE 18-3: Baud Rates for Asynchronous Modes
    • 18.1.3 Auto-Baud Rate Detect
      • TABLE 18-4: BRG Counter Clock Rates
      • FIGURE 18-1: Automatic Baud Rate Calculation
      • FIGURE 18-2: BRG Overflow Sequence
  • 18.2 EUSART Asynchronous Mode
    • 18.2.1 EUSART Asynchronous Transmitter
      • FIGURE 18-3: EUSART Transmit Block Diagram
      • FIGURE 18-4: Asynchronous Transmission
      • FIGURE 18-5: Asynchronous Transmission (Back to Back)
      • TABLE 18-5: Registers Associated with Asynchronous Transmission
    • 18.2.2 EUSART Asynchronous Receiver
    • 18.2.3 Setting Up 9-Bit Mode with Address Detect
      • FIGURE 18-6: EUSART Receive Block Diagram
      • FIGURE 18-7: Asynchronous Reception
      • TABLE 18-6: Registers Associated with Asynchronous Reception
    • 18.2.4 Auto-Wake-up on Sync Break Character
      • FIGURE 18-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation
      • FIGURE 18-9: Auto-Wake-up Bit (WUE) Timings During Sleep
    • 18.2.5 Break Character Sequence
    • 18.2.6 Receiving a Break Character
      • FIGURE 18-10: Send Break Character Sequence
  • 18.3 EUSART Synchronous Master Mode
    • 18.3.1 EUSART Synchronous Master Transmission
      • FIGURE 18-11: Synchronous Transmission
      • FIGURE 18-12: Synchronous Transmission (Through TXEN)
      • TABLE 18-7: Registers Associated with Synchronous Master Transmission
    • 18.3.2 EUSART Synchronous Master Reception
      • FIGURE 18-13: Synchronous Reception (Master Mode, SREN)
      • TABLE 18-8: Registers Associated with Synchronous Master Reception
  • 18.4 EUSART Synchronous Slave Mode
    • 18.4.1 EUSART Synchronous Slave Transmit
      • TABLE 18-9: Registers Associated with Synchronous Slave Transmission
    • 18.4.2 EUSART Synchronous Slave Reception
      • TABLE 18-10: Registers Associated with Synchronous Slave Reception
• 19.0 10-Bit Analog-to-Digital Converter (A/D) Module
  • Register 19-1: ADCON0: A/D Control Register 0
  • Register 19-2: ADCON1: A/D Control Register 1
  • Register 19-3: ADCON2: A/D Control Register 2
  • FIGURE 19-1: A/D Block Diagram
  • FIGURE 19-2: Analog Input Model
  • 19.1 A/D Acquisition Requirements
    • EQUATION 19-1: Acquisition Time
    • EQUATION 19-2: A/D Minimum Charging Time
    • EQUATION 19-3: Calculating the Minimum Required Acquisition Time
  • 19.2 Selecting and Configuring Automatic Acquisition Time
  • 19.3 Selecting the A/D Conversion Clock
    • TABLE 19-1: Tad vs. Device Operating Frequencies
  • 19.4 Operation in Power Managed Modes
  • 19.5 Configuring Analog Port Pins
  • 19.6 A/D Conversions
    • FIGURE 19-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
    • FIGURE 19-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
  • 19.7 Use of the CCP1 Trigger
    • TABLE 19-2: Registers Associated with A/D Operation
• 20.0 Comparator Module
  • Register 20-1: CMCON: Comparator Control Register
  • 20.1 Comparator Configuration
    • FIGURE 20-1: Comparator I/O Operating Modes
  • 20.2 Comparator Operation
  • 20.3 Comparator Reference
    • FIGURE 20-2: Single Comparator
    • 20.3.1 External Reference Signal
    • 20.3.2 Internal Reference Signal
  • 20.4 Comparator Response Time
  • 20.5 Comparator Outputs
    • FIGURE 20-3: Comparator Output Block Diagram
  • 20.6 Comparator Interrupts
  • 20.7 Comparator Operation During Sleep
  • 20.8 Effects of a Reset
  • 20.9 Analog Input Connection Considerations
    • FIGURE 20-4: Comparator Analog Input Model
    • TABLE 20-1: Registers Associated with Comparator Module
• 21.0 Comparator Voltage Reference Module
  • 21.1 Configuring the Comparator Voltage Reference
    • Register 21-1: CVRCON: Comparator Voltage Reference Control Register
    • FIGURE 21-1: Comparator Voltage Reference Block Diagram
  • 21.2 Voltage Reference Accuracy/Error
  • 21.3 Operation During Sleep
  • 21.4 Effects of a Reset
  • 21.5 Connection Considerations
    • FIGURE 21-2: Voltage Reference Output Buffer Example
    • TABLE 21-1: Registers Associated with Comparator Voltage Reference
• 22.0 High/Low-Voltage Detect (HLVD)
  • Register 22-1: HLVDCON: High/Low-Voltage Detect Control Register
  • 22.1 Operation
    • FIGURE 22-1: HLVD Module Block Diagram (with External Input)
  • 22.2 HLVD Setup
  • 22.3 Current Consumption
  • 22.4 HLVD Start-up Time
    • FIGURE 22-2: Low-Voltage Detect Operation (VDIRMAG = 0)
    • FIGURE 22-3: High-Voltage Detect Operation (VDIRMAG = 1)
  • 22.5 Applications
    • FIGURE 22-4: Typical Low-Voltage Detect Application
  • 22.6 Operation During Sleep
  • 22.7 Effects of a Reset
    • TABLE 22-1: Registers Associated with High/Low-Voltage Detect Module
• 23.0 ECAN� Module
  • 23.1 Module Overview
    • 23.1.1 Module Functionality
      • FIGURE 23-1: CAN Buffers and Protocol Engine Block Diagram
  • 23.2 CAN Module Registers
    • 23.2.1 CAN Control and Status Registers
      • Register 23-1: CANCON: CAN Control Register
      • Register 23-2: Canstat: Can Status Register
      • EXAMPLE 23-1: Changing to Configuration Mode
      • EXAMPLE 23-2: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers
      • EXAMPLE 23-2: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers (Cont...
      • Register 23-3: ECANCON: Enhanced CAN Control Register
      • Register 23-4: COMSTAT: Communication Status Register
    • 23.2.2 Dedicated CAN Transmit Buffer Registers
      • Register 23-5: TXBnCON: Transmit Buffer n Control Registers [0 � n � 2]
      • Register 23-6: TXBnSIDH: Transmit Buffer n Standard Identifier Registers, High Byte [0 � n � 2]
      • Register 23-7: TXBnSIDL: Transmit Buffer n Standard Identifier Registers, Low Byte [0 � n � 2]
      • Register 23-8: TXBnEIDH: Transmit Buffer n Extended Identifier Registers, High Byte [0 � n � 2]
      • Register 23-9: TXBnEIDL: Transmit Buffer n Extended Identifier Registers, Low Byte [0 � n � 2]
      • Register 23-10: TXBnDm: Transmit Buffer n Data Field Byte m Registers [0 � n � 2, 0 � m � 7]
      • Register 23-11: TXBnDLC: Transmit Buffer n Data Length Code Registers [0 � n � 2]
      • Register 23-12: TXERRCNT: Transmit Error Count Register
      • EXAMPLE 23-3: Transmitting a CAN Message Using Banked Method
      • EXAMPLE 23-4: Transmitting a CAN Message Using WIN Bits
    • 23.2.3 Dedicated CAN Receive Buffer Registers
      • Register 23-13: RXB0CON: Receive Buffer 0 Control Register
      • Register 23-13: RXB0CON: Receive Buffer 0 Control Register (CONTINUED)
      • Register 23-14: RXB1CON: Receive Buffer 1 Control Register
      • Register 23-14: RXB1CON: Receive Buffer 1 Control Register (cONTINUED)
      • Register 23-15: RXBnSIDH: Receive Buffer n Standard Identifier Registers, High Byte [0 � n � 1]
      • Register 23-16: RXBnSIDL: Receive Buffer n Standard Identifier Registers, Low Byte [0 � n � 1]
      • Register 23-17: RXBnEIDH: Receive Buffer n Extended Identifier Registers, High Byte [0 � n � 1]
      • Register 23-18: RXBnEIDL: Receive Buffer n Extended Identifier Registers, Low Byte [0 � n � 1]
      • Register 23-19: RXBnDLC: Receive Buffer n Data Length Code Registers [0 � n � 1]
      • Register 23-20: RXBnDm: Receive Buffer n Data Field Byte m Registers [0 � n � 1, 0 � m � 7]
      • Register 23-21: RXERRCNT: Receive Error Count Register
      • EXAMPLE 23-5: Reading a CAN Message
      • Register 23-22: BnCON: tx/rx Buffer n Control Registers in Receive Mode [0 � n � 5, TXnEN (bsel0<...
      • Register 23-23: BnCON: tx/rx Buffer n Control Registers in Transmit Mode [0 � n � 5, TXnEN (bsel0...
      • Register 23-24: BnSIDH: TX/RX Buffer n Standard Identifier Registers, High Byte in Receive Mode [...
      • Register 23-25: BnSIDH: TX/RX Buffer n Standard Identifier Registers, High Byte in Transmit Mode ...
      • Register 23-26: BnSIDL: TX/RX Buffer n Standard Identifier Registers, Low Byte in Receive Mode [0...
      • Register 23-27: BnSIDL: TX/RX Buffer n Standard Identifier Registers, Low Byte in Transmit Mode [...
      • Register 23-28: BnEIDH: TX/RX Buffer n Extended Identifier Registers, High Byte in Receive Mode [...
      • Register 23-29: BnEIDH: TX/RX Buffer n Extended Identifier Registers, High Byte in Transmit Mode ...
      • Register 23-30: BnEIDL: TX/RX Buffer n Extended Identifier Registers, Low Byte in Receive Mode [0...
      • Register 23-31: BnEIDL: TX/RX Buffer n Extended Identifier Registers, Low Byte in Transmit Mode [...
      • Register 23-32: BnDm: TX/RX Buffer n Data Field Byte m Registers in Receive Mode [0 � n � 5, 0 � ...
      • Register 23-33: BnDm: TX/RX Buffer n Data Field Byte m Registers in Transmit Mode [0 � n � 5, 0 �...
      • Register 23-34: BnDLC: TX/RX Buffer n Data Length Code Registers in Receive Mode [0 � n � 5, TXnE...
      • Register 23-35: BnDLC: TX/RX Buffer n Data Length Code Registers in Transmit Mode [0 � n � 5, TXn...
      • Register 23-36: bsel0: Buffer Select Register 0(1)
      • Register 23-37: RXFnSIDH: Receive Acceptance Filter n Standard Identifier Filter Registers, High ...
      • Register 23-38: RXFnSIDL: Receive Acceptance Filter n Standard Identifier Filter Registers, Low B...
      • Register 23-39: RXFnEIDH: Receive Acceptance Filter n Extended Identifier Registers, High Byte [0...
      • Register 23-40: RXFnEIDL: Receive Acceptance Filter n Extended Identifier Registers, Low Byte [0 ...
      • Register 23-41: RXMnSIDH: Receive Acceptance Mask n Standard Identifier Mask Registers, High Byte...
      • Register 23-42: RXMnSIDL: Receive Acceptance Mask n Standard Identifier Mask Registers, Low Byte ...
      • Register 23-43: RXMnEIDH: Receive Acceptance Mask n Extended Identifier Mask Registers, High Byte...
      • Register 23-44: RXMnEIDL: Receive Acceptance Mask n Extended Identifier Mask Registers, Low Byte ...
      • Register 23-45: rxfconn: Receive Filter Control Register n [0 � n � 1](1)
      • Register 23-46: SDFLC: Standard Data Bytes Filter Length Count Register(1)
      • Register 23-47: rxfbconn: Receive Filter Buffer Control Register n(1)
      • Register 23-48: Msel0: Mask Select Register 0(1)
      • Register 23-49: Msel1: Mask Select Register 1(1)
      • Register 23-50: Msel2: Mask Select Register 2(1)
      • Register 23-51: Msel3: Mask Select Register 3(1)
    • 23.2.4 CAN Baud Rate Registers
      • Register 23-52: BRGCON1: Baud Rate Control Register 1
      • Register 23-53: BRGCON2: Baud Rate Control Register 2
      • Register 23-54: BRGCON3: Baud Rate Control Register 3
    • 23.2.5 CAN Module I/O Control Register
      • Register 23-55: CIOCON: CAN I/O Control Register
    • 23.2.6 CAN Interrupt Registers
      • Register 23-56: PIR3: Peripheral Interrupt Request (Flag) Register 3
      • Register 23-57: PIE3: Peripheral Interrupt Enable Register
      • Register 23-58: IPR3: Peripheral Interrupt Priority Register 5
      • Register 23-59: TXBIE: Transmit Buffers Interrupt Enable Register(1)
      • Register 23-60: BIE0: Buffer Interrupt Enable Register 0(1)
      • TABLE 23-1: Can Controller Register Map
      • TABLE 23-1: Can Controller Register Map (continued)
  • 23.3 CAN Modes of Operation
    • 23.3.1 Configuration Mode
    • 23.3.2 Disable Mode
    • 23.3.3 Normal Mode
    • 23.3.4 Listen Only Mode
    • 23.3.5 Loopback Mode
    • 23.3.6 Error Recognition Mode
  • 23.4 ECAN Module Functional Modes
    • 23.4.1 Mode 0 � Legacy Mode
    • 23.4.2 Mode 1 � Enhanced Legacy Mode
    • 23.4.3 Mode 2 � Enhanced FIFO Mode
  • 23.5 CAN Message Buffers
    • 23.5.1 Dedicated Transmit Buffers
    • 23.5.2 Dedicated Receive Buffers
    • 23.5.3 Programmable Transmit/ Receive Buffers
    • 23.5.4 Programmable Auto-RTR Buffers
  • 23.6 CAN Message Transmission
    • 23.6.1 Initiating Transmission
    • 23.6.2 Aborting Transmission
    • 23.6.3 Transmit Priority
      • FIGURE 23-2: Transmit Buffers
  • 23.7 Message Reception
    • 23.7.1 Receiving a Message
    • 23.7.2 Receive Priority
    • 23.7.3 Enhanced FIFO Mode
    • 23.7.4 Time-Stamping
  • 23.8 Message Acceptance Filters and Masks
    • TABLE 23-2: Filter/Mask Truth Table
    • FIGURE 23-3: Message Acceptance Mask and Filter Operation
  • 23.9 Baud Rate Setting
    • EQUATION 23-1:
    • EQUATION 23-2:
    • EQUATION 23-3:
    • FIGURE 23-4: Bit Time Partitioning
    • 23.9.1 External Clock, Internal Clock and Measurable Jitter in HS-PLL Based Oscillators
      • FIGURE 23-5: Effects of Phase Jitter on the Microcontroller Clock and CAN Bit Time
      • TABLE 23-3: Frequency Error from Jitter at Various PLL Generated Clock Speeds
      • TABLE 23-4: Total Frequency Error at Various PLL Generated Clock Speeds (100 PPM Oscillator Drift...
    • 23.9.2 Time Quanta
      • EXAMPLE 23-6: Calculating Tq, Nominal Bit Rate and Nominal Bit Time
    • 23.9.3 Synchronization Segment
    • 23.9.4 Propagation Segment
    • 23.9.5 Phase Buffer Segments
    • 23.9.6 Sample Point
    • 23.9.7 Information Processing Time
  • 23.10 Synchronization
    • 23.10.1 Hard Synchronization
    • 23.10.2 Resynchronization
    • 23.10.3 Synchronization Rules
      • FIGURE 23-6: Lengthening a Bit Period (Adding SJW to Phase Segment 1)
      • FIGURE 23-7: Shortening a Bit Period (Subtracting SJW from Phase Segment 2)
  • 23.11 Programming Time Segments
  • 23.12 Oscillator Tolerance
  • 23.13 Bit Timing Configuration Registers
    • 23.13.1 BRGCON1
    • 23.13.2 BRGCON2
    • 23.13.3 BRGCON3
  • 23.14 Error Detection
    • 23.14.1 CRC Error
    • 23.14.2 Acknowledge Error
    • 23.14.3 Form Error
    • 23.14.4 Bit Error
    • 23.14.5 Stuff Bit Error
    • 23.14.6 Error States
    • 23.14.7 Error Modes and Error Counters
      • FIGURE 23-8: Error Modes State Diagram
  • 23.15 CAN Interrupts
    • 23.15.1 Interrupt Code Bits
    • 23.15.2 Transmit Interrupt
    • 23.15.3 Receive Interrupt
      • TABLE 23-5: Values for ICODE<3:1>
    • 23.15.4 Message Error Interrupt
    • 23.15.5 Bus Activity Wake-up Interrupt
    • 23.15.6 Error Interrupt
• 24.0 Special Features of the CPU
  • 24.1 Configuration Bits
    • TABLE 24-1: Configuration Bits and Device IDs
    • Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
    • Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
    • Register 24-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
    • Register 24-4: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
    • Register 24-5: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
    • Register 24-6: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
    • Register 24-7: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
    • Register 24-8: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
    • Register 24-9: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
    • Register 24-10: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
    • Register 24-11: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
    • Register 24-12: Device ID Register 1 for PIC18F2585/2680/4585/4680 Devices
    • Register 24-13: Device ID Register 2 for PIC18F2585/2680/4585/4680 Devices
  • 24.2 Watchdog Timer (WDT)
    • 24.2.1 Control Register
      • FIGURE 24-1: WDT Block Diagram
      • Register 24-14: WDTCON: Watchdog Timer Control Register
      • TABLE 24-2: Summary of Watchdog Timer Registers
  • 24.3 Two-Speed Start-up
    • 24.3.1 Special Considerations for Using Two-Speed Start-up
      • FIGURE 24-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
  • 24.4 Fail-Safe Clock Monitor
    • FIGURE 24-3: FSCM Block Diagram
    • 24.4.1 FSCM and the Watchdog Timer
    • 24.4.2 Exiting Fail-Safe Operation
      • FIGURE 24-4: FSCM Timing Diagram
    • 24.4.3 FSCM Interrupts in Power Managed Modes
    • 24.4.4 POR or Wake-up From Sleep
  • 24.5 Program Verification and Code Protection
    • FIGURE 24-5: Code-Protected Program Memory for PIC18F2585/2680/4585/4680
    • TABLE 24-3: Summary of Code Protection Registers
    • 24.5.1 Program Memory Code Protection
      • FIGURE 24-6: Table Write (WRTn) Disallowed
      • FIGURE 24-7: External Block Table Read (EBTRn) Disallowed
      • FIGURE 24-8: External Block Table Read (EBTRn) Allowed
    • 24.5.2 Data EEPROM Code Protection
    • 24.5.3 Configuration Register Protection
  • 24.6 ID Locations
  • 24.7 In-Circuit Serial Programming
  • 24.8 In-Circuit Debugger
    • TABLE 24-4: Debugger Resources
  • 24.9 Single-Supply ICSP Programming
• 25.0 Instruction Set Summary
  • 25.1 Standard Instruction Set
    • TABLE 25-1: Opcode Field Descriptions
    • FIGURE 25-1: General Format For Instructions
    • TABLE 25-2: PIC18FXXXX Instruction Set
    • 25.1.1 Standard Instruction Set
  • 25.2 Extended Instruction Set
    • 25.2.1 Extended Instruction Syntax
      • TABLE 25-3: Extensions to the PIC18 Instruction Set
    • 25.2.2 Extended Instruction Set
    • 25.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode
    • 25.2.4 Considerations When Enabling the Extended Instruction Set
    • 25.2.5 Special Considerations with Microchip MPLAB� IDE Tools
• 26.0 Development Support
  • 26.1 MPLAB Integrated Development Environment Software
  • 26.2 MPASM Assembler
  • 26.3 MPLAB C17 and MPLAB C18 C Compilers
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 26.5 MPLAB C30 C Compiler
  • 26.6 MPLAB ASM30 Assembler, Linker and Librarian
  • 26.7 MPLAB SIM Software Simulator
  • 26.8 MPLAB SIM30 Software Simulator
  • 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
  • 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
  • 26.11 MPLAB ICD 2 In-Circuit Debugger
  • 26.12 PRO MATE II Universal Device Programmer
  • 26.13 MPLAB PM3 Device Programmer
  • 26.14 PICSTART Plus Development Programmer
  • 26.15 PICDEM 1 PICmicro Demonstration Board
  • 26.16 PICDEM.net Internet/Ethernet Demonstration Board
  • 26.17 PICDEM 2 Plus Demonstration Board
  • 26.18 PICDEM 3 PIC16C92X Demonstration Board
  • 26.19 PICDEM 4 8/14/18-Pin Demonstration Board
  • 26.20 PICDEM 17 Demonstration Board
  • 26.21 PICDEM 18R PIC18C601/801 Demonstration Board
  • 26.22 PICDEM LIN PIC16C43X Demonstration Board
  • 26.23 PICkitTM 1 Flash Starter Kit
  • 26.24 PICDEM USB PIC16C7X5 Demonstration Board
  • 26.25 Evaluation and Programming Tools
• 27.0 Electrical Characteristics
  • Absolute Maximum Ratings (�)
    • FIGURE 27-1: PIC18F2585/2680/4585/4680 Voltage-Frequency Graph (Industrial)
    • FIGURE 27-2: PIC18LF2585/2680/4585/4680 Voltage-Frequency Graph (Industrial)
  • 27.1 DC Characteristics: Supply Voltage PIC18F2585/2680/4585/4680 (Industrial) PIC18LF2585/2680/4...
  • 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2585/2680/4585/4680 (Industrial) PIC...
  • 27.3 DC Characteristics: PIC18F2585/2680/4585/4680 (Industrial) PIC18LF2585/2680/4585/4680 (Indus...
    • TABLE 27-1: Memory Programming Requirements
    • TABLE 27-2: Comparator Specifications
    • TABLE 27-3: Voltage Reference Specifications
    • FIGURE 27-3: High/Low-Voltage Detect Characteristics
    • TABLE 27-4: High/Low-Voltage Detect Characteristics
  • 27.4 AC (Timing) Characteristics
    • 27.4.1 Timing Parameter Symbology
    • 27.4.2 Timing Conditions
      • TABLE 27-5: Temperature and Voltage Specifications � AC
      • FIGURE 27-4: Load Conditions For Device Timing Specifications
    • 27.4.3 Timing Diagrams and Specifications
      • FIGURE 27-5: External Clock Timing (All Modes Except PLL)
      • TABLE 27-6: External Clock Timing Requirements
      • TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2V to 5.5V)
      • TABLE 27-8: AC Characteristics: Internal RC Accuracy PIC18F2585/2680/4585/4680 (Industrial) PIC18...
      • FIGURE 27-6: CLKO and I/O Timing
      • TABLE 27-9: CLKO and I/O Timing Requirements
      • FIGURE 27-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
      • FIGURE 27-8: Brown-out Reset Timing
      • TABLE 27-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...
      • FIGURE 27-9: Timer0 and Timer1 External Clock Timings
      • TABLE 27-11: Timer0 and Timer1 External Clock Requirements
      • FIGURE 27-10: Capture/Compare/PWM Timings (All CCP Modules)
      • TABLE 27-12: Capture/Compare/PWM Requirements (All CCP Modules)
      • FIGURE 27-11: Parallel Slave Port Timing (PIC18F4585/4680)
      • TABLE 27-13: Parallel Slave Port Requirements (PIC18F4585/4680)
      • FIGURE 27-12: Example SPI� Master Mode Timing (CKE=0)
      • TABLE 27-14: Example SPI� Mode Requirements (Master Mode, CKE=0)
      • FIGURE 27-13: Example SPI� Master Mode Timing (CKE=1)
      • TABLE 27-15: Example SPI� Mode Requirements (Master Mode, CKE=1)
      • FIGURE 27-14: Example SPI� Slave Mode Timing (CKE=0)
      • TABLE 27-16: Example SPI� Mode Requirements (Slave Mode Timing, CKE=0)
      • FIGURE 27-15: Example SPI� Slave Mode Timing (CKE=1)
      • TABLE 27-17: Example SPI� Slave Mode Requirements (CKE=1)
      • FIGURE 27-16: I2C� Bus Start/stop Bits Timing
      • TABLE 27-18: I2C� Bus Start/Stop Bits Requirements (Slave Mode)
      • FIGURE 27-17: I2C� Bus Data Timing
      • TABLE 27-19: I2C� Bus Data Requirements (Slave Mode)
      • FIGURE 27-18: Master SSP I2C� Bus Start/Stop Bits Timing Waveforms
      • TABLE 27-20: Master SSP I2C� Bus Start/Stop Bits Requirements
      • FIGURE 27-19: Master SSP I2C� Bus Data Timing
      • TABLE 27-21: Master SSP I2C� Bus Data Requirements
      • FIGURE 27-20: EUSART Synchronous Transmission (Master/Slave) Timing
      • TABLE 27-22: EUSART Synchronous Transmission Requirements
      • FIGURE 27-21: EUSART Synchronous Receive (Master/Slave) Timing
      • TABLE 27-23: EUSART Synchronous Receive Requirements
      • TABLE 27-24: A/D Converter Characteristics: PIC18F2585/2680/4585/4680 (Industrial) PIC18LF2585/26...
      • FIGURE 27-22: A/D Conversion Timing
      • TABLE 27-25: A/D Conversion Requirements
• 28.0 DC and AC Characteristics Graphs and Tables
• 29.0 Packaging Information
  • 29.1 Package Marking Information
  • 29.1 Package Marking Information (Continued)
  • 29.2 Package Details
  • 28-Lead Skinny Plastic Dual In-line (SP) � 300 mil Body (PDIP)
  • 28-Lead Plastic Small Outline (SO) �Wide, 300 mil Body (SOIC)
  • 40-Lead Plastic Dual In-line (P) � 600 mil Body (PDIP)
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
  • 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
• Appendix A: Revision History
  • Revision A (December 2003)
  • Revision B (July 2004)
• Appendix B: Device Differences
  • TABLE B-1: Device Differences
• Appendix C: Conversion Considerations
• Appendix D: Migration From Baseline to Enhanced Devices
• Appendix E: Migration from Mid-Range to Enhanced Devices
• Appendix F: Migration from High-End to Enhanced Devices
• INDEX
• On-Line Support
  • Connecting to the Microchip Internet Web Site
• Systems Information and Upgrade Hot Line
• Reader Response
• PIC18F2585/2680/4585/4680 Product Identification System
• Worldwide Sales and Service