1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND

ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET

MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

FLASH MEMORY

MT28F160C3

Low Voltage, Extended Temperature

GENERAL DESCRIPTION

The MT28F160C3 is a nonvolatile, electrically block-

erasable (flash), programmable, read-only memory con-
taining 16,777,216 bits organized as 1,048,576 words (16
bits).

The MT28F160C3 is manufactured on 0.22µm pro-

cess technology in a 48-ball FBGA package. The device

BALL ASSIGNMENT (Top View)

46-Ball FBGA

FEATURES

· Thirty-nine erase blocks:

Eight 4K-word parameter blocks
Thirty-one 32K-word main memory blocks

· V

, V

Q and V

voltages:

2.7V3.3V V

1.65V3.3V and 12V V

· Address access times:

90ns, 110ns at 2.7V3.3V

· Low power consumption:

Standby and deep power-down mode < 1µA

(typical I

)

Automatic power saving feature (APS mode)

· Enhanced WRITE/ERASE SUSPEND (1µs typical)
· 128-bit OTP area for security purposes
· Industry-standard command set compatibility
· Software/hardware block protection

OPTIONS

NUMBER

· Timing

90ns access

-9

110ns access

-11

· Boot Block Starting Address

Top (FFFFFH)

Bottom (00000H)

· Package

46-ball FBGA (6 x 8 ball grid)

· Temperature Range

Commercial (0°C to +70°C)

None

Extended (-40°C to +85°C)

*Lower V

Q ranges are available upon request.

Part Number Example:

MT28F160C3FD-11 TET

A13

A14

A15

A16

A19

A17

DQ8

DQ9

DQ10

WP#

A18

DQ2

DQ3

RP#

DQ11

DQ12

DQ4

WE#

DQ5

DQ6

DQ13

OE#

CE#

DQ0

DQ1

A11

A10

A12

DQ14

DQ15

DQ7

1 2 3 4 5 6 7 8

(Ball Down)

NOTE: See page 3 for Ball Description Table.

See last page for mechanical drawing.

has an I/O supply of 2.7V (MIN). Programming in pro-
duction is accomplished by using high voltage which can
be supplied on a separate line.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state
machine (WSM), which simplifies these operations and
relieves the system processor of secondary tasks. The
WSM status can be monitored by an on-chip status reg-
ister to determine the progress of program/erase tasks.

The device is equipped with 128 bits of one time

programmable (OTP) area. The soft protection feature
for blocks will mark them as read-only by configuring soft
protection registers with command sequences.

Please refer to Micron's Web site (

www.micron.com/

flash

) for the latest data sheet.

DEVICE MARKING

Due to the size of the package, Micron's standard part

number is not printed on the top of each device. Instead,
an abbreviated device mark comprised of a five-digit
alphanumeric code is used. The abbreviated device marks
are cross referenced to Micron part numbers in Table 1.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

Address

Input

Buffer

X DEC

Y/Z DEC

Data Input

Buffer

APS

Control

Data

Comparator

Output

Multiplexer

Address

CNT WSM

Output

Buffer

Status

Reg.

WSM

Program/

Erase Change

Pump Voltage

Switch

Address Latch

DQ0DQ15

CSM

RP#

CE#

X DEC

Y/Z DEC

WE#

OE#

I/O Logic

A0A19

Address

Multiplexer

Bank b Blocks

Y/Z Gating/Sensing

Data

Bank a Blocks

Y/Z Gating/Sensing

Table 1

Cross Reference for Abbreviated

Device Marks

PRODUCT

SAMPLE

PART NUMBER

MARKING

MT28F160C3FD-9 BET

FW610

FX610

MT28F160C3FD-9 TET

FW611

FX611

MT28F160C3FD-11 BET

FW612

FX612

MT28F160C3FD-11 TET

FW613

FX613

NOTE: 1. The mechanical sample marking is FY610.

ARCHITECTURE

The MT28F160C3 flash contains eight 4K-word

parameter blocks and thirty-one 32K-word blocks.
Memory is organized by using a blocked architecture to
allow independent erasure of selected memory blocks.
Any address within a block address range selects that
block for the required READ, WRITE, or ERASE operation
(see Figures 1 and 2).

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

BALL DESCRIPTIONS

46-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

WE#

Input

Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command state machine (CSM)
or to the memory array.

WP#

Input

Write Protect: Unlocks the soft-protected blocks when HIGH if V

1.65V3.3V or 12V and RP# = V

for WRITE or ERASE. Does not affect

WRITE or ERASE operation on other blocks.

CE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.

RP#

Input

Reset/Power-Down: When LOW, RP# clears the status register, sets the
write state machine (WSM) to the array read mode and places the
device in deep power-down mode. All inputs, including CE#, are "Don't
Care," and all outputs are High-Z. RP# must be held at V

during all

other modes of operation.

OE#

Input

Output Enable: Enables data output buffers when LOW. When OE# is
HIGH, the output buffers are disabled.

1A, 1B, 1C, 1D,

A0-A19

Input

Address Inputs: These address inputs select a unique, 16-bit word out

2A, 2B, 2C, 3A,

of the 1,048,576 available.

3C, 5B, 6A, 6B,
6C, 7A, 7B, 7C,

8A, 8B, 8C, 8D

2D, 2E, 2F, 3D, DQ0-DQ15

Input/

Data I/O: These data I/O are data output lines during any READ

3E, 3F, 4D, 4E,

Output

operation or data input lines during a WRITE. Data I/O are used to

4F, 5D, 5E, 6D,

input commands to the CSM.

6E, 6F, 7E, 7F

Supply

Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until
completion of the operation, V

must be 1.65V3.3V or 12V. V

"Don't Care" during all other operations.

Supply

Power Supply: 2.7V3.3V.

Supply

I/O Supply Voltage: 2.7V3.3V.

1F, 8E

Supply

Ground.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

NOTE: 1. L = V

(LOW), H = V

(HIGH), X = V

or V

("Don't Care").

2. V

PPH

= 1.65V3.3V and V

PPH

= 12V.

3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. See Table 3 for the IDENTIFY DEVICE command.

TRUTH TABLE

FUNCTION

RP#

CE#

OE#

WE#

WP#

DQ0-DQ7 DQ8-DQ15

Standby

High-Z

RESET

High-Z

READING

READ

Data-Out

Output Disable

High-Z

WRITE/ERASE (EXCEPT SOFT PROTECTED BLOCKS)

ERASE SETUP

20H

ERASE CONFIRM

PPH

D0H

WRITE SETUP

10H/40H

WRITE

PPH

Data-In

READ ARRAY

FFH

WRITE/ERASE (SOFT-PROTECTED BLOCKS)

ERASE SETUP

20H

ERASE CONFIRM

PPH

D0H

WRITE SETUP

10H/40H

WRITE

PPH

Data-In

READ ARRAY

FFH

DEVICE IDENTIFICATION

Manufacturer

2CH

00H

Device (top boot)

92H

44H

Device (bottom boot)

93H

44H

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

8 x 4K-Word Blocks

32K-Word Block

4K-Word Block

Parameter

Blocks

FFFFFh

F8000h

F7FFFh

F0000h

EFFFFh

E8000h

E7FFFh

E0000h

DFFFFh

D8000h

D7FFFh

D0000h

CFFFFh

C8000h

C7FFFh

C0000h

BFFFFh

B8000h

B7FFFh

B0000h

AFFFFh

A8000h

A7FFFh

A0000h

9FFFFh

98000h

97FFFh

90000h

8FFFFh

88000h

87FFFh

80000h

7FFFFh

78000h

77FFFh

70000h

6FFFFh

68000h

67FFFh

60000h

5FFFFh

58000h

57FFFh

50000h

4FFFFh

48000h

47FFFh

40000h

3FFFFh

38000h

37FFFh

30000h

2FFFFh

28000h

27FFFh

20000h

1FFFFh

18000h

17FFFh

10000h

0FFFFh

08000h

07FFFh

00000h

FFFFFh
FF000h
FEFFFh

FE000h
FDFFFh

FD000h
FCFFFh

FC000h
FBFFFh

FB000h
FAFFFh

FA000h
F9FFFh

F9000h
F8FFFh

F8000h

ADDRESS RANGE

Figure 1

Top Boot Block Memory Address Map

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

32K-Word Block

8 x 4K-Word Blocks

4K-Word Block

Parameter

Blocks

FFFFFh

F8000h

F7FFFh

F0000h

EFFFFh

E8000h

E7FFFh

E0000h

DFFFFh

D8000h

D7FFFh

D0000h

CFFFFh

C8000h

C7FFFh

C0000h

BFFFFh

B8000h

B7FFFh

B0000h

AFFFFh

A8000h

A7FFFh

A0000h

9FFFFh

98000h

97FFFh

90000h

8FFFFh

88000h

87FFFh

80000h

7FFFFh

78000h

77FFFh

70000h

6FFFFh

68000h

67FFFh

60000h

5FFFFh

58000h

57FFFh

50000h

4FFFFh

48000h

47FFFh

40000h

3FFFFh

38000h

37FFFh

30000h

2FFFFh

28000h

27FFFh

20000h

1FFFFh

18000h

17FFFh

10000h

0FFFFh

08000h

07FFFh

00000h

07FFFh
07000h
06FFFh

06000h
05FFFh

05000h
04FFFh

04000h
03FFFh

03000h
02FFFh

02000h
01FFFh

01000h
00FFFh

00000h

ADDRESS RANGE

Figure 2

Bottom Boot Block Memory Address Map

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

MEMORY ORGANIZATION

The MT28F160C3 memory array is segmented into 31

blocks of 32K words, along with eight 4K-word parameter
blocks. The device is available with block architecture
mapped in either of the two configurations: the param-
eter blocks located at the top or at the bottom of the
memory array, as required by different microprocessors.
The MT28F160C3 top boot configuration with the blocks
and address ranges is shown in Figure 1 and the bottom
boot configuration in Figure 2.

COMMAND STATE MACHINE

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between the external
microprocessor and the internal write state machine
(WSM). The available commands are listed in Table 2,
and the descriptions of these commands are shown in
Table 3. Program and erase algorithms are automated by
an on-chip WSM. Once a valid program/erase command
sequence is entered, the WSM executes the appropriate
algorithm, which generates the necessary timing signals
to control the device internally to accomplish the re-
quested operation. A command is valid only if the exact
sequence of WRITEs is completed. After the WSM com-
pletes its task, the WSM status bit (SR7) is set to a logic
HIGH level (1), allowing the CSM to respond to the full
command set again.

OPERATION

Device operations are selected by entering standard

JEDEC 8-bit command codes with conventional micro-
processor timings into an on-chip CSM through I/Os
DQ0-DQ7. When the device is powered up, internal reset

circuitry initializes the chip to a read array mode of op-
eration. Changing the mode of operation requires that a
command code be entered into the CSM. The on-chip
status register allows the progress of various operations
to be monitored. The status register is interrogated by
entering a READ STATUS REGISTER command onto the
CSM (cycle 1) and reading the register data on I/Os DQ0-
DQ7 (cycle 2). Status register bits SR0-SR7 correspond to
DQ0-DQ7 (see Table 3).

Table 2

Command State Machine Codes for

Device Mode Selection

COMMAND

CODE ON

DQ0DQ7

DEVICE MODE

10h/40h

Write setup/alternate write setup

20h

Block erase setup

50h

Clear status register

70h

Read status register

90h

Identify device

0Fh

Soft protection

B0h

Program/erase suspend

D0h

Program/erase resume
Erase confirm

FFh

Read array/OTP exit

AFh

OTP entry

60h

Reserved

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

Table 3

Command Definitions

FIRST CYCLE

SECOND CYCLE

COMMAND

OPERATION

ADDRESS

CSM/INPUT

OPERATION

ADDRESS

DATA

READ ARRAY

WRITE

FFh

READ

IDENTIFY DEVICE

WRITE

90h

READ

READ STATUS REGISTER

WRITE

70h

READ

SRD

WORD PROGRAM

WRITE

10h/40h

WRITE

BLOCK ERASE

WRITE

20h

WRITE

D0h

PROGRAM/ERASE SUSPEND

WRITE

B0h

PROGRAM/ERASE RESUME

WRITE

D0h

CLEAR STATUS REGISTER

WRITE

50h

SOFT PROTECTION

WRITE

0Fh

WRITE

SPC

OTP ENTRY

WRITE

AFh

WRITE

AFh

OTP EXIT

WRITE

FFh

WRITE

FFh

COMMAND DEFINITIONS

Once a specific command code has been entered, the

WSM executes an internal algorithm generating the nec-
essary timing signals to program, erase, and verify data.

See Table 3 for the CSM command definitions and data
for each of the bus cycles.

NOTE: 1. The command data is written through DQ0-DQ7

2. ID = Manufacturer ID: 002Ch; Device ID (Top Boot): 4492h; Device ID (Bottom Boot): 4493h
3. IA = Identify address: 00000h for manufacturer code and 00001h for device code
4. BA = Any address within the block to be selected
5. WA = Word address
6. AD = Array data
7. SRD = Data read from status register
8. PD = Data to be written at location WA
9. SPC = Soft protect command:

00h = Clear all soft protection
FFh = Set all soft protection
F0h = Clear addressed block soft protection
0Fh = Set addressed block soft protection

10. X = Don't Care

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored by
toggling OE# and CE# and by reading the resulting status
code on I/Os DQ0-DQ7. The high-order I/Os (DQ8-DQ15)
are set to 00h internally, so only the low-order I/Os (DQ0-
DQ7) need interpreting.

CE#. The latest falling edge of either of these two signals
updates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register monitoring. To ensure
that the status register output contains updated status
data, CE# or OE# must be toggled for each subsequent
STATUS READ.

The status register provides the internal state of the

WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 4 defines the status
register bits.

After monitoring the status register during a PRO-

GRAM/ERASE, the data appearing on DQ0-DQ7 remains
as status register data until a new command is issued to
the CSM. To return the device to other modes of opera-
tion, a new command must be issued to the CSM.

COMMAND STATE MACHINE
OPERATIONS

The CSM decodes instructions for read, read device

identification code, read status register, clear status reg-
ister, program, erase, erase suspend, erase resume, pro-
gram suspend, program resume, soft protection, and
OTP entry/exit. The 8-bit command code is input to the
device on DQ0-DQ7 (see Table 2 for CSM codes). During
a PROGRAM or ERASE cycle, the CSM informs the WSM
that a PROGRAM or ERASE cycle has been requested.

During a PROGRAM cycle, the WSM controls the pro-

gram sequences and the CSM responds to a PROGRAM
SUSPEND command only. During an ERASE cycle, the
CSM responds to an ERASE SUSPEND command only.
When the WSM has completed its task, the WSM status
bit (SR7) is set to a logic HIGH level and the CSM responds
to the full command set. The CSM stays in the current
command state until the microprocessor issues another
command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when V

is within its correct volt-

age range. For data protection, it is required that RP# be
held at a logic LOW level during a CPU reset.

CLEAR STATUS REGISTER

The WSM can set to "1" the block lock status bit (SR1),

the V

status bit (SR3), the program status bit (SR4), and

the erase status bit (SR5) of the status register. The CLEAR
STATUS REGISTER command (50h) allows the external
microprocessor to clear these status bits and synchro-
nize to internal operations. After issuing this command,
the status bits are cleared and the device returns to the
read array mode.

READ OPERATIONS

Three READ operations are available: read array, read

device identification code, and read status register.

READ ARRAY

The array is read by entering the command code FFh

on DQ0-DQ7. Control signals CE# and OE# must be at a
logic LOW level (V

) and WE# and RP# must be at a logic

HIGH level (V

) to read data from the array. Data is

available on DQ0-DQ15. Any valid address within any of
the blocks selects that address and allows data to be read
from that address. Upon initial power-up, the device
defaults to the read array mode.

READ DEVICE IDENTIFICATION CODE

Device identification codes are read by entering com-

mand code 90h on DQ0-DQ7. Two bus cycles are re-
quired for this operation, the first to enter the command
code and the second to read the selected code. Control
signals CE# and OE# must be at a logic LOW level (V

)

and WE# and RP# must be at a logic HIGH level (V

). The

manufacturer code is obtained on DQ0-DQ15 in the sec-
ond cycle, after the identify address 00000h is latched.
The device code is obtained on DQ0-DQ15 in the second
cycle, after the identify address 00001h is latched (see
Table 3).

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0-DQ7. Control signals CE# and OE#
must be at a logic LOW level (V

), and WE# and RP# must

be at a logic HIGH level (V

). Two bus cycles are required

for this operation: one to enter the command code, and
one to read the status register. The status register con-
tents are updated on the falling edge of CE# or OE#,
whichever occurs last within the cycle.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

Table 4

Status Register

STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

WRITE STATE MACHINE STATUS (WSM) If SR7 = 0 (busy), the WSM has not completed an ERASE or
1 = Ready

PROGRAM operation. If SR7 = 1 (ready), other operations can be

0 = Busy

performed.

SR6

ERASE SUSPEND STATUS

If SR6 = 1, WSM halts execution, indicating that the ERASE

1 = ERASE SUSPEND

operation has been suspended. SR6 remains "1" until an ERASE

0 = ERASE in progress or

RESUME command is issued.

ERASE complete

SR5

ERASE STATUS

SR5 = 0 indicates that a BLOCK ERASE has been successful. SR5 = 1

1 = BLOCK ERASE error

indicates that an erase has failed; therefore, the WSM has completed

0 = BLOCK ERASE successful

the maximum allowable erase pulses determined by the internal
algorithm but which were insufficient to completely erase the device.

SR4

PROGRAM STATUS

SR4 = 0 indicates successful programming has occurred at the

1 = PROGRAM error

address location. SR4 = 1 indicates the WSM was unable to

0 = PROGRAM successful

correctly program the addressed location.

SR3

STATUS

SR3 provides status of V

during programming.

1 = Program abort V

range error

0 = V

good

SR2

PROGRAM SUSPEND STATUS

If SR2 = 1, WSM halts execution, indicating the PROGRAM

1 = PROGRAM suspended

operation has been suspended. SR2 stays "1" until a PROGRAM

0 = PROGRAM in progress or

RESUME command is issued.

PROGRAM complete

SR1

BLOCK LOCK STATUS

SR1 = 1 indicates that the address block is locked when WP# = V

1 = Block locked

Any attempt to program/erase this block will abort the operation

0 = Block not locked

and the device will return to read status mode.

SR0

RESERVED

NOTE: 1. After a PROGRAM/ERASE command is issued and confirmed, status bit SR7 goes LOW to indicate that the operation is

in progress. If SR7 = 1 (ready), other polling operations can be performed. Until this occurs, the other status bits are
not valid. SR7 is not updated automatically at the completion of a WSM task; therefore, if the WSM status bit shows
busy (0), OE# and CE# must be toggled periodically to determine when the WSM has completed an operation (SR7 =
1).

2. When an ERASE SUSPEND command is issued, the WSM halts execution and sets SR6 = 1, indicating that the ERASE

operation has been suspended. The WSM status bit is also set to HIGH (SR7 = 1), indicating that the ERASE SUSPEND
operation has been completed successfully.

3. During an ERASE error, the SR5 bit is set (SR5 = 1), while SR5 = 0 indicates that a successful block erasure has occurred.
4. If the WSM is unable to program the addressed location correctly, the SR4 bit is set (SR4 = 1) and

SR4 = 0 indicates that a successful programming operation has occurred at the addressed block location. Information
concerning the status of V

during programming/erasure is provided by SR3. If V

is lower than V

PPLK

after a

PROGRAM/ERASE command has been issued, SR3 is set to a "1," indicating that the PROGRAM/ERASE operation has
aborted due to a low V

5. During a PROGRAM SUSPEND command, the WSM halts execution and the SR2 bit is set, indicating that the PRO-

GRAM operation has been suspended. This bit remains "1" until a PROGRAM RESUME command is issued. The WSM
status bit is also set to HIGH (SR7 = 1), indicating that the PROGRAM SUSPEND operation has been completed
successfully.

6. A proper block address must be provided in an ERASE operation. If that addressed block is protected, then the SR1 bit

is set (SR1 = 1) when WP# = V

. If that block is not protected, then SR1 = 0.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

PROGRAMMING OPERATIONS

There are two CSM commands for programming: pro-

gram setup and alternate program setup (see Table 2).
After the desired command code is entered, the WSM
takes over and correctly sequences the device to com-
plete the program operation. Monitoring of the WRITE
operation is possible through the status register (see the
Status Register section). During this time, the CSM re-
sponds only to a PROGRAM SUSPEND command until
the PROGRAM operation has been completed, after which
all commands to the CSM become valid again. (See Fig-
ure 4 for programming operation.)

During programming, V

must remain in the

appropriate V

voltage range as shown in the recom-

mended operating conditions table. Different combina-
tions of RP#, WP#, and V

voltage levels ensure that data

in certain blocks are secure and therefore cannot be
programmed (see Table 5 for a list of combinations).
Only "0s" are written and compared during a PROGRAM
operation. If "1s" are programmed, the memory cell con-
tents do not change and no error occurs.

PROGRAM SUSPENSION

The PROGRAM operation can be suspended by

issuing a PROGRAM SUSPEND command (B0h). The
PROGRAM SUSPEND command typically takes 1µs to
execute, and the device is then in program suspend mode.
Once the WSM has reached the suspend state, it allows
the CSM to respond only to READ ARRAY, READ STATUS
REGISTER, and PROGRAM RESUME commands. During
the PROGRAM SUSPEND operation, array data should
be read from an address other than the one being pro-
grammed. To resume the PROGRAM operation, a PRO-
GRAM RESUME command (D0h) must be issued to cause
the CSM to clear the suspend state previously set. (See
Figure 7 for PROGRAM SUSPEND and PROGRAM
RESUME.)

ERASE OPERATIONS

An ERASE operation must be used to initialize all bits

in an array block to "1s." After BLOCK ERASE CONFIRM
is issued, the CSM responds only to an ERASE SUSPEND
command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the addressed block to logic 1s. Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The block
to be erased is selected by using any valid address within
that block. Note that different combinations of RP#, WP#
and V

voltage levels ensure that data in certain blocks

are secure and therefore cannot be erased (see Table 5 for
a list of combinations). Block erasure is initiated by a
command sequence to the CSM: block erase setup (20h)
followed by block erase confirm (D0h) (see Figure 5). A
two-command erase sequence protects against acciden-
tal erasure of memory contents.

When the BLOCK ERASE CONFIRM command is com-

plete, the WSM automatically executes a sequence of
events to complete the block erasure. During this se-
quence, the block is programmed with logic 0s, data is
verified, all bits in the block are erased, and finally verifi-
cation is performed to ensure that all bits are correctly
erased. Monitoring of the ERASE operation is possible
through the status register (see the Status Register sec-
tion).

ERASE SUSPENSION

During the execution of an ERASE operation, the

ERASE SUSPEND command (B0h) can be entered to di-
rect the WSM to suspend the ERASE operation. The ERASE
SUSPEND command typically takes 1µs to execute, and
the device is then in erase suspend mode. Once the WSM
has reached the suspend state, it allows the CSM to
respond only to the READ ARRAY, READ STATUS REGIS-
TER, ERASE RESUME and PROGRAM commands. Dur-

Table 5

Data Protection Combinations

DATA PROTECTION PROVIDED

RP#

WP#

All blocks locked

PPLK

All blocks locked

All blocks unlocked

PPLK

Soft-protected blocks locked

PPLK

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

ing the ERASE SUSPEND operation, array data must be
read from a block other than the one being erased. To
resume the ERASE operation, an ERASE RESUME com-
mand (D0h) must be issued to cause the CSM to clear the
suspend state previously set. It is also possible that an
ERASE in any block can be suspended and a WRITE to
another block can be initiated. After the completion of
WRITE, the ERASE can be resumed by writing an ERASE
RESUME command (see Figure 6). It is also possible to
suspend the WRITE operation and read from another
block.

AUTOMATIC POWER-SAVING MODE

Substantial power savings are realized during periods

when the device is not accessed while in the active mode.
During this time, the device switches to the automatic
power saving (APS) mode. When the device switches to
this mode, I

is reduced to 1µA typically. This mode is

entered automatically if no address or control lines toggle
within approximately a 300ns time-out period. At least
one transition on CE# must occur after power-up to acti-
vate this mode's availability. The device remains in this
mode and the I/O lines retain the data from the last
access until a new read address is issued or another
operation is initiated.

RESET/ DEEP POWER-DOWN MODE

Very low levels of power consumption can be attained

by using a special ball, RP#, to disable internal device
circuitry. When RP# is at a logic LOW level of 0.0V ±0.2V,
a much lower I

current consumption is achieved, typi-

cally 1µA. This is important in portable applications where
extended battery life is a major concern.

A recovery time is required when exiting from deep

power-down mode. A minimum of

RS is required before

a CSM command can be recognized. With RP# at ground,
the WSM is reset and the status register is cleared, effec-
tively eliminating accidental programming to the array
during system reset. After restoration of power, the de-
vice will be disabled until RP# is returned to V

If RP# goes LOW during a PROGRAM or ERASE opera-

tion, the device powers down and becomes nonfunc-
tional. Data being written or erased at that time becomes
invalid or indeterminate, requiring that the operation be
performed again after power restoration. When RP# is set
at logic LOW, all internal circuits will be reset. Setting RP#
LOW during a PROGRAM or ERASE operation is not rec-
ommended.

OTP MODE

The device has 128 bits of OTP (one time program-

mable) area. There are 64 bits that are programmed at the
factory with a unique 64-bit code that is not modifiable.

The other 64-bit OTP area is left blank to program for
customer design requirements if needed. Protection of
the user-programmable, 64-bit contents is provided, af-
ter the area is programmed, by programming the lock-
bit.

To program the OTP area, two "AFh" commands must

be written, followed by two WRITE cycles of the normal
program sequences. When in the OTP mode, the WSM
programs the OTP area and not the array. During pro-
gramming, a read can acquire only the WSM status (sta-
tus register output). When the programming is complete,
the device remains in the OTP mode and only the status
can be read in the OTP area. Writing two "FFh" com-
mands exits the OTP mode and causes the device to go
into the read array mode. To read the OTP area after
programming, the OTP mode must be re-entered.

To read the OTP area contents, two "AFh" commands

must be written, followed by a READ. Writing two "FFh"
commands exits the OTP mode and causes the device to
go into the read array mode.

After programming the 64-bit OTP area, the lock-bit

can be programmed. The lock-bit is at address 00040H
and is on DQ15. Once the lock-bit is programmed to a "0,"
the 64-bit, user-programmable area is permanently pro-
tected (see Figure 3). The lock- bit can be read in OTP
mode, as described above.

4 Words

Factory-Programmed

4 Words

User-Programmed

DQ15

00000h
00002h
00004h
00006h

00020h
00022h
00024h
00026h

00040h

Figure 3

OTP Area Map

NOTE: 1. Always locked.

2. Locked by programming DQ15 at address 00040H.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

STANDBY MODE

supply current is reduced by applying a logic HIGH

level on CE# and RP# to enter the standby mode. In the
standby mode, the outputs are placed in the high-imped-
ance state. Applying a logic HIGH level (V

Q) on CE#

and RP# reduces the current to 1µA typically. If the device
is deselected during an ERASE operation or during pro-
gramming, the device continues to draw active current
until the operation is complete.

SOFT BLOCK DATA PROTECTION

Soft protection is available with CSM command 0Fh

(see Table 3). The protection bit for each block can be set
and cleared individually, or all at once. After the soft
protection bit of a block is set, the block is protected when
V

PPLK

, RP# is HIGH, and WP# is LOW. When V

PPLK

the block is protected (locked) as well. A block is

unlocked when WP# is HIGH, even if its soft protection
bit is set (see Table 5).

When the device is powered down or RP# reset, the

soft protection blocks will be set to the protected state.
So, if WP# goes LOW after first power-up, RP# reset, or
power-down, all blocks will be protected. The CSM com-
mand 0Fh is needed to clear the soft protected blocks.
When WP# goes LOW the cleared blocks will be unpro-
tected.

The block lock status bit SR1 is used to monitor the

individual block lock status after the second WRITE cycle
of the soft protection CSM command. Additionally, to

monitor the block lock status of any block, the read status
register command 70h can be used. On the command's
second cycle, any address within a block is issued and
SR1 will indicate the block lock status for that block.
When monitoring the block lock status bit SR1, the cor-
rect status can only be obtained with WP# LOW.

POWER-UP

During a power-up, it is not necessary to sequence

Q, V

and V

. However, it is recommended that RP#

be held LOW during power-up for additional protection
while V

is ramping above V

LKO

to a stable operative

level. After a power-up or RESET, the status register is
reset, and the device will enter the array read mode.

POWER-UP PROTECTION

The likelihood of unwanted WRITE or ERASE opera-

tions is minimized since two consecutive cycles are re-
quired to execute either operation. When V

< V

LKO

, the

device does not accept any WRITE cycles, and noise
pulses < 5ns on CE# or WE# do not initiate a WRITE cycle.

POWER SUPPLY DECOUPLING

For decoupling purposes, each device should have a

0.1µF ceramic capacitor connected between V

and V

, and between V

Q and V

. The capacitor

should be as close as possible to the device balls.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue WRITE SETUP

Command

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

Figure 4

Automated Word Programming

Flowchart

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

BUS
OPERATION

COMMAND

COMMENTS

WRITE

Data = 40h or 10h

SETUP

Addr = Don't Care

WRITE

Data = Word to be

DATA

programmed

Addr = Address of word to be

programmed

READ

Status register data
Toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.

BUS
OPERATION

COMMAND

COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect V

low

Standby

Check SR4

1 = Word program error

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR7 = 1?

Start

BLOCK ERASE Passed

Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

ERASE

SUSPEND Loop

YES

SR1 = 0?

YES

SR4 = 1 and

SR5 = 1?

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted
on a Locked Block

Command Sequence

Error

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command

Issue Block Address

and ERASE

CONFIRM Command

Figure 5

Automated BLOCK ERASE Flowchart

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

BUS
OPERATION

COMMAND

COMMENTS

WRITE

Data = 20h

ERASE

Addr = Don't Care

SETUP

WRITE

ERASE

Data = D0h
Block Addr = Address
within block to be erased

READ

Status register data
Toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to reset the
device to read array mode.

BUS
OPERATION

COMMAND

COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect V

low

Standby

Check SR4 and SR5
1 = BLOCK ERASE command

error

Standby

Check SR5

1 = BLOCK ERASE error

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

READ

PROGRAM

Issue READ MEMORY

Command

PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM
Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 2)

YES

SR7 = 1?

Figure 6

ERASE SUSPEND/ERASE RESUME

Flowchart

NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.

2. See Word Programming Flowchart for complete programming procedure.

BUS
OPERATION

COMMAND

COMMENTS

WRITE

ERASE

Data = B0h

SUSPEND

READ

Status register data
Toggle OE# or CE# to update
status register

Standby

Check SR7
1 = Ready

Standby

Check SR6
1 = Suspended

WRITE

READ

Data = FFh

MEMORY

or
WRITE

WRITE

Data = 40h or 10h

SETUP

Addr = Don't Care

READ

Read data from block other
than that being erased

or
WRITE

WRITE

Data = Word to be

DATA

programmed
Addr = Address of word to be
programmed

WRITE

ERASE

Data = D0h

RESUME

Addr = Don't Care

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-40°C

£ T

£ +85°C)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage (during program/read/erase/suspend)

2.7

3.3

I/O Supply Voltage

2.7

3.3

5, 6

Supply Voltage (during program/erase operations)

1.65

3.3

11.4

12.6

5, 7

Input High (Logic 1) Voltage, all inputs

Q - 0.2 V

Q + 0.2

Input Low (Logic 0) Voltage, all inputs

-0.2

0.2

OUTPUT VOLTAGE LEVELS

Q - 0.1

= V

(MIN), V

Q = V

Q (MIN)

Output High Voltage (I

= -0.1mA)

0.1

Output Low Voltage (I

= 0.1mA)

INPUT LEAKAGE CURRENT
V

= V

(MAX), V

Q = V

Q (MAX)

-1

µA

Any input (0V

£ V

Q);

All other balls not under test = 0V

OUTPUT LEAKAGE CURRENT
V

= V

(MAX), V

Q = V

Q (MAX)

-10

µA

OUT

is disabled; 0V

£ V

OUT

£ V

BLOCK ERASE cycling

100K

Cyc

ABSOLUTE MAXIMUM RATINGS

1, 2

Supply Voltage Range, V

....................... -0.6V to +4.0V

Supply Voltage Range, V

..................... -0.6V to +13.0V

Input Voltage Range ................................... -0.6V to +4.0V
Output Voltage Range .............................. -0.6V to +4.0V

Storage Temperature Range, T

STG

........ -65°C to +150°C

Stresses greater than those listed under "Absolute Maxi-

mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only, and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

All voltage values are with respect to V

The voltage can undershoot to -1V for periods < 20ns.

The voltage on any output can overshoot to 4.6V for

periods < 20ns.

NOTE: 5. All voltages referenced to V

6. V

Q must be less than or equal to V

7. 12V V

is allowable for production only.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

CAPACITANCE

= +25°C; f = 1 MHz)

PARAMETER/CONDITION

SYMBOL

MAX

UNITS

NOTES

Input Capacitance

Output Capacitance

READ, STANDBY AND DEEP POWER-DOWN CURRENT DRAIN

(-40°C

£ T

£ +85°C; V

= 2.7V3.3V)

PARAMETER/CONDITION

SYMBOL

TYP

MAX

UNITS NOTES

READ CURRENT:
V

= V

(MAX), V

Q = V

Q (MAX)

1, 2

(CE# = V

; OE# = V

; RP# = V

; f = 5 MHz; Other inputs V

or V

)

STANDBY CURRENT: V

SUPPLY

µA

= V

(MAX); (CE# = RP# = V

DEEP POWER-DOWN CURRENT: V

SUPPLY

= V

(MAX); V

Q = V

Q (MAX)

µA

(RP# = V

; Other inputs V

Q or V

)

READ CURRENT: V

SUPPLY

£ V

±15

µA

> V

200

µA

DEEP POWER-DOWN CURRENT: V

SUPPLY

µA

(RP# = V

; V

£ V

)

STANDBY CURRENT: V

SUPPLY (V

£ V

)

µA

NOTE: 1. I

is dependent on cycle rates.

2. Automatic power savings (APS) mode reduces I

to standby current level I

for static operation.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

0.1mA

Output

under

test

= 30pf

-0.1mA

Figure 8

AC Test Output and Load Circuit

NOTE: 1. C

includes probe and fixture capacitance.

AC TEST CONDITIONS

Input pulse levels ................................................. 0V to V

Input rise and fall times ................................................ <10ns
Input timing reference level ....................................... V

Q/2

Output timing reference level .................................... V

Q/2

Output load ............................................................. C

= 30pF

0.0V

Output

Input

Test Points

Figure 9

AC Input/Output Reference Waveform

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

READ AC TIMING CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS

(-40°C

£ T

£ +85°C; V

= 2.7V3.3V)

AC CHARACTERISTICS

-9

-11

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

READ cycle time

110

Access time from CE#

ACE

110

Access time from OE#

AOE

Access time from address

110

RP# HIGH to output valid delay

RWH

600

RP# LOW pulse width

100

OE# or CE# HIGH to output in High-Z

Output hold time from OE#, CE# or address change

NOTE: 1. OE# may be delayed by

ACE minus

AOE after CE# falls before

ACE is affected.

READ CYCLE

VALID DATA

VALID ADDRESS

CE#

A0A19

OE#

DQ0DQ15

DON'T CARE

UNDEFINED

tRC

tACE

tAOE

tOD

tOH

tAA

WE#

RP#

tRWH

TIMING PARAMETERS

-9

-11

SYMBOL

MIN

MAX

MIN

MAX

UNITS

110

ACE

110

AOE

110

-9

-11

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RWH

600

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

RECOMMENDED DC WRITE/ERASE CONDITIONS

(-40°C

£ T

£ +85°C; V

= 2.7V3.3V)

PARAMETER/CONDITION

SYMBOL

MIN

TYP

MAX

UNITS NOTES

WRITE/ERASE lockout voltage

PPLK

voltage during WRITE/ERASE operation

PPH

1.65

3.3

PPH

11.4

12.6

WRITE/ERASE lockout operation

LKO

1.5

WRITE/ERASE CURRENT DRAIN

(-40°C

£ T

£ +85°C; V

= 2.7V3.3V)

PARAMETER/CONDITION

SYMBOL

TYP

MAX

UNITS NOTES

WRITE CURRENT: V

SUPPLY

ERASE CURRENT: V

SUPPLY

ERASE/PROGRAM SUSPEND CURRENT: V

SUPPLY

µA

(ERASE/PROGRAM suspended)

WRITE/ERASE CURRENT: V

SUPPLY

= V

0.1

= V

ERASE/PROGRAM SUSPEND CURRENT: V

SUPPLY

= V

µA

(ERASE/PROGRAM suspended)

= V

200

µA

WORD WRITE AND ERASE DURATION CHARACTERISTICS

2.7V3.3V Vcc

1.65V3.3V V

12V V

PARAMETER

TYP

MAX

TYP

MAX

UNITS NOTES

Boot/parameter BLOCK ERASE time

0.5

4, 5

Main BLOCK ERASE time

4, 5

Boot/parameter BLOCK WRITE time

0.1

4, 5, 6, 7

Main BLOCK WRITE time

0.3

4, 5, 6, 7

Program/erase suspend latency

µs

NOTE: 1. Absolute WRITE/ERASE protection when V

£ V

PPLK

2. 12V V

is allowable for production only. Write timings are identical to 1.65V3.3V V

operation.

3. Parameter is specified when device is not accessed. Actual current draw will be I

plus current of operation being

executed while the device is in suspend mode.

4. The 12V V

is for production only.

5. Typical values measured at T

= +25°C.

6. Assumes no system overhead.
7. Typical write times tested with checkerboard data pattern.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS:
WE# (CE#)-CONTROLLED WRITES

(-40°C

£ T

£ +85°C; V

= 2.7V3.3V)

AC CHARACTERISTICS

-9

-11

PARAMETER

SYMBOL

MIN

UNITS

NOTES

WE# (CE#) HIGH pulse width

WPH (

CPH)

WE# (CE#) pulse width

WP (

CP)

Address setup time to WE# (CE#) HIGH

Address hold time from WE# (CE#) HIGH

Data setup time to WE# (CE#) HIGH

Data hold time from WE# (CE#) HIGH

CE# (WE#) setup time to WE# (CE#) LOW

CS (

WS)

CE# (WE#) hold time from WE# (CE#) HIGH

CH (

WH)

setup time to WE# (CE#) HIGH

VPS

200

RP# HIGH to WE# (CE#) LOW delay

150

WRITE duration

WED1

µs

Boot BLOCK ERASE duration

WED2

0.5

Parameter BLOCK ERASE duration

WED3

0.5

Main BLOCK ERASE duration

WED4

hold time from status data valid

VPH

WE# (CE#) HIGH to busy status (SR7 = 0)

200

1, 2

WP# HIGH setup time to WE# (CE#) HIGH

WHS

WP# HIGH hold time from status data valid

WHH

OE# HIGH hold time from WE# HIGH

OHH

NOTE: 1. Polling status register before

WB is met may falsely indicate WRITE or ERASE completion.

WB = 800ns (MAX).

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

WRITE/ERASE CYCLE

WE#-CONTROLLED WRITE/ERASE

CE#

A0A19

OE#

DQ0DQ15

DON'T CARE

tWED1, 2, 3, 4

WE#

RP#

tRS

tCH

tCS

tOHH

PPH

tAS

tAH

tWP

tWPH

tDS

tDH

CMD

CMD/

Data-in

CMD

WRITE SETUP or

ERASE SETUP

input

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

tDH

tWB

tDS

WRITE or block

address asserted, and

WRITE data or ERASE

CONFIRM

Note 1

tAS

tAH

Status

(SR7=1)

Status

(SR7=0)

tVPS

tWHS

[Unlock soft-protected blocks]

WP#

tVPH

tWHH

WED1

µs

WED2

0.5

WED3

0.5

WED4

VPH

200

WHS

WHH

OHH

TIMING PARAMETERS

-9

-11

SYMBOL

MIN

UNITS

WPH

VPS

200

150

-9

-11

SYMBOL

MIN

UNITS

NOTE: 1. Address inputs are "Don't Care" but must be held stable.

WB = 800ns (MAX).

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

WE#

A0A19

OE#

DQ0DQ15

DON'T CARE

tWED1, 2, 3, 4

CE#

RP#

tRS

tWH

tWS

PPH

tAS

tAH

tCP

tCPH

tDS

tDH

CMD

CMD/

Data-in

CMD

WRITE SETUP or

ERASE SETUP

input

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

tDH

[Unlock soft-protected blocks]

tDS

WRITE or block

address asserted, and

WRITE data or ERASE

CONFIRM

Note 1

tAS

tAH

Status

(SR7=1)

Status

(SR7=0)

tVPS

tVPH

WP#

tWB

tWHS

tWHH

WRITE/ERASE CYCLE

CE#-CONTROLLED WRITE/ERASE

NOTE: 1. Address inputs are "Don't Care" but must be held stable.

WB = 800ns (MAX).

150

WED1

µs

WED2

0.5

WED3

0.5

WED4

VPH

200

WHS

WHH

TIMING PARAMETERS

-9

-11

SYMBOL

MIN

UNITS

CPH

VPS

200

-9

-11

SYMBOL

MIN

UNITS

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

Table 6

Command State Machine Current/Next States

COMMAND INPUTS (and next state)

Current

SR7

Data

Read

Write

Block

Erase

Prog./

Read

Clear

Identify

Soft

Otp

State

when

Array

setup

erase

confirm

erase

device

prot.

entry

Read

(FFh)

(10h/

setup

(D0h)

susp.

resume

(70h)

(50h)

(90h)

setup

(SPC)

(AFh)

40h)

(20h)

(B0h)

(D0h)

(0Fh)

Read Array

Array

Read

Write

Erase

Read array

Read

Identify Soft prot. Soft prot.

Otp

array

setup

status

array

device

setup

setup/

entry

read

array

Read

Status

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Status

array

setup

status

array

device

prot.

setup/

entry

setup

read

array

Identify

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Device

array

setup

status

array

device

prot.

setup/

entry

setup

read

array

Soft Prot.

Status

Soft

Read array

Soft prot.

Soft

Read

Setup

prot. all

block

prot.

array

Soft

Status

Read

Write

Erase

Read array

Read

Identify Soft prot. Soft prot.

Otp

Protection

array

setup

status

array

device

setup

setup/

entry

Complete

read

array

Write

Status

Program

Setup

Program Not

Status

Program

Prog.

Program

Complete

(not complete)

susp.

(not complete)

status

Program

Status

Program Program suspend Program Program Program Program

Program suspend read array

Suspend

susp.

read array

susp.

Status

read

status

array

Program

Array

Program Program suspend Program Program Program Program

Program suspend read array

Suspend

susp.

read array

susp.

Read Array

read

status

array

Program

Status

Read

Write

Erase

Read array

Read

Identify Soft prot. Soft prot.

Otp

Complete

Array

setup

status

array

device

setup

setup/

entry

read

array

Erase

Status

Erase command error

Erase

Erase command error

Setup

Erase

Status

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Comd. Error

array

setup

status

array

device

prot.

setup/

entry

setup

Read

array

Erase Not

Status

Erase (not complete)

Erase

Erase (not complete)

Complete

susp. to

status

Erase

Status

Erase

Write

Erase

Erase suspend read array

Suspend

susp.

setup

susp.

Status

read

status

array

Erase

Array

Erase

Write

Erase

Erase suspend read array

Suspend

susp.

setup

susp.

Array

read

status

array

Erase

Status

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Complete

array

setup

status

array

device

prot.

setup/

entry

setup

read

array

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

46-BALL FBGA

3.50 ±.05

3.75

.75 (TYP)

.75

(TYP)

PIN #1 ID

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .27mm

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

PIN #1 ID

8.00 ±.10

1.20 MAX

4.00 ±.05

2.625 ±.05

5.25

.80 ±.075

.10

.35 +.05

-.10

(TYP)

1.875 ±.05

7.00 ±.10

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

1 Meg x 16 3V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F160C3_3.p65 Rev. 3, Pub. 8/01

1 MEG x 16

3V ENHANCED+ BOOT BLOCK FLASH MEMORY

ADVANCE

REVISION HISTORY

Rev. 3 .................................................................................................................................................................................... 8/01
· Added

WB maximum specification

· Corrected WRITE/ERASE Cycle timing diagram (CE-Controlled)

Rev. B ................................................................................................................................................................................... 5/01
· Changed I

MAX from 30mA to 20mA; added

WB maximum specification

Original document ............................................................................................................................................................. 4/00

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT28F160C3FD-9TET