PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory
MT28F320A18_12_1.fm Rev. A 4/03 EN

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

FLASH MEMORY

MT28F320A18A

Low Voltage, Extended Temperature
0.12µm Process Technology

Features

· 32Mb block architecture

Seventy-one erasable blocks:
Eight 4K-word parameter blocks
Sixty-three 32K-word main memory blocks

· V

, V

Q, V

voltages

1.65V (MIN), 1.95V (MAX) V

, V

0.9V (MIN), 1.95V (MAX) V

(in-system

PROGRAM/ERASE)
12V ±5% (HV) V

tolerant (factory programming

compatibility)

· Random access time: 70ns @ 1.65V V

· Low power consumption (V

= 1.8V)

Asynchronous Read < 18mA
Write/Erase < 40mA (MAX)
Standby < 50µA (MAX)
Automatic power saving feature (APS)

· Enhanced write and erase suspend options

ERASE-SUSPEND-to-READ
PROGRAM-SUSPEND-to-READ
ERASE-SUSPEND-to-PROGRAM

· Dual 64-bit chip protection registers for security

purposes

· Cross-compatible command support

Extended command set
Common flash interface

· PROGRAM/ERASE cycle

100,000 WRITE/ERASE cycles per block
(V

= V

PP1)

NOTE:

1. An extended voltage range of 1.65V2.20V for Vcc

and VccQ, and 0.9V2.20V for V

is available

upon request. A voltage range of 1.42V1.60V for
VccQ is also available upon request.

Part Number Example:

MT28F320A18AFF-70 TET

Options

Marking

· Timing

70ns access

-70

· Configurations

2 Meg x 16

MT28F320A18A

· Boot Block Configuration

Top

Bottom

· Package

47-ball FBGA (6 x 8 ball grid)

· Temperature Range

Extended (-40ºC to +85ºC)

1 2 3 4 5 6 7 8

Top View

(Ball Down)

A13

A14

A15

A16

A19

A17

DQ8

DQ9

DQ10

WP#

A18

A20

DQ2

DQ3

WE#

DQ5

DQ6

DQ13

OE#

CE#

DQ0

DQ1

A11

A10

A12

DQ14

DQ15

DQ7

RP#

DQ11

DQ12

DQ4

Figure 1: 47-Ball FBGA

NOTE:

1. See page 9 for Ball Description table.
2. See page 38 for mechanical drawing.

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12TOC.fm Rev. A 4/03 EN

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Architecture and Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Command State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command State Machine Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Clear Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Read Protection Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

PROGRAMMING Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Locking operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Locked Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Locking Operations during Erase Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Status Register Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Chip Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Reading the Chip Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Programming the Chip Protection
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Locking the Chip Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Program and Erase Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Automatic Power Save Mode (APS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Data Sheet Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12LOF.fm Rev. A 4/03 EN

List of Figures

Figure 1:

47-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1:

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 2:

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3:

32Mb Bottom Boot Block Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4:

32Mb Top Boot Block Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 5:

Automated Word Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 6:

PROGRAM SUSPEND/PROGRAM RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 7:

Block Erase Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 8:

ERASE SUSPEND/ERASE RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 9:

Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 10:

AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 11:

Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 12:

Two-Cycle Programming/ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 13:

Single Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 14:

Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 15:

47-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12LOT.fm Rev. A 4/03 EN

List of Tables

Table 1:

Cross Reference for Abbreviated Device Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 2:

Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 3:

Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 4:

Command State Machine Codes For Device Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 5:

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 6:

Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 7:

Command State Machine Current/Next States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 8:

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 9:

Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 10:

Block Locking State Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 11:

Chip Configuration Addressing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 12:

Range (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 13:

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 14:

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 15:

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 17:

WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 16:

READ Cycle Timing Requirements

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 18:

ERASE and PROGRAM Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 19:

CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

General Description

The MT28F320A18A is a nonvolatile, electrically

block-erasable (Flash) memory containing eight 4K-
word parameter blocks and sixty-three 32K-word main
blocks.

The MT28F320A18A allows soft protection for

blocks, as read only, by configuring soft protection reg-
isters with dedicated command sequences. For secu-
rity purposes, a 128-bit chip protection register is
provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state
machine (WSM). An on-chip status register can be
used to monitor the WSM status and to determine the
progress of the PROGRAM/ERASE task.

The ERASE/PROGRAM SUSPEND functionality

allows compatibility with existing EEPROM emulation
software packages.

The device is manufactured using 0.12µm process

technology.

Please refer to Micron's Web site

www.micron.com/flash

for the latest data sheet.

Architecture and Memory Organization

The MT28F320A18A contains eight 4K-word param-

eter blocks and sixty-three 32K-word main blocks.

3 and 4 show the bottom and top memory organiza-

tions for the 32Mb device.

Device Marking

Due to the size of the package, Micron's standard

part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.

Table 1:

Cross Reference for Abbreviated Device Marks

PART NUMBER

PRODUCT MARKING

SAMPLE MARKING

MECHANICAL

SAMPLE MARKING

MT28F320A18AFF-70 BET

FW705

FX705

FY705

MT28F320A18AFF-70 TET

FW706

FX706

FY706

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Figure 3: 32Mb Bottom Boot Block

Memory Address Map

Figure 4: 32Mb Top Boot Block Memory

Address Map

32K-Word Block

32K-Word Blocks

8 x 4K-Word Blocks

1FFFFFh

1F8000h

1F7FFFh

1F0000h

1EFFFFh

1E8000h

1E7FFFh

1E0000h
1DFFFFh

1D8000h

1D7FFFh

1D0000h

1CFFFFh

1C8000h

1C7FFFh

1C0000h

1BFFFFh

1B8000h

1B7FFFh

1B0000h

1AFFFFh

1A8000h

1A7FFFh

1A0000h

19FFFFh

198000h

197FFFh

190000h

18FFFFh

188000h

187FFFh

180000h

17FFFFh

178000h

177FFFh

170000h

16FFFFh

168000h

167FFFh

160000h

15FFFFh

158000h

157FFFh

150000h

14FFFFh

148000h

147FFFh

140000h

13FFFFh

138000h

137FFFh

130000h

12FFFFh

128000h

127FFFh

120000h

11FFFFh

118000h

117FFFh

110000h

10FFFFh

108000h

107FFFh

100000h

0FFFFFh

0F8000h

0F7FFFh

0F0000h

0EFFFFh

0E8000h

0E7FFFh

0E0000h
0DFFFFh

0D8000h

0D7FFFh

0D0000h

0CFFFFh

0C8000h

0C7FFFh

0C0000h

0BFFFFh

0B8000h

0B7FFFh

0B0000h

0AFFFFh

0A8000h

0A7FFFh

0A0000h

09FFFFh

098000h

097FFFh

090000h

08FFFFh

088000h

087FFFh

080000h

07FFFFh

078000h

077FFFh

070000h

06FFFFh

068000h

067FFFh

060000h

05FFFFh

058000h

057FFFh

050000h

04FFFFh

048000h

047FFFh

040000h

03FFFFh

038000h

037FFFh

030000h

02FFFFh

028000h

027FFFh

020000h

01FFFFh

018000h

017FFFh

010000h

00FFFFh

008000h

007FFFh

000000h

ADDRESS RANGE

4K-Word Block

Parameter

Blocks

007FFFh
007000h
006FFFh

006000h
005FFFh

005000h
004FFFh

004000h
003FFFh

003000h
002FFFh

002000h
001FFFh

001000h
000FFFh

000000h

8 x 4K-Word Blocks

32K-Word Block

4K-Word Block

Parameter

Blocks

1FFFFFh
1FF000h
1FEFFFh

1FE000h
1FDFFFh

1FD000h
1FCFFFh

1FC000h
1FBFFFh

1FB000h
1FAFFFh

1FA000h
1F9FFFh

1F9000h
1F8FFFh

1F8000h

ADDRESS RANGE

1F8000h

1F0000h

1E8000h

1E0000h

1D8000h

1D0000h

1C8000h

1C0000h

1B8000h

1B0000h

1A8000h

1A0000h

198000h

190000h

188000h

180000h

178000h

170000h

168000h

160000h

158000h

150000h

148000h

140000h

138000h

130000h

128000h

120000h

118000h

110000h

108000h

100000h

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

000000h

1FFFFFh

1F7FFFh

1EFFFFh

1E7FFFh

1DFFFFh

1D7FFFh

1CFFFFh

1C7FFFh

1BFFFFh

1B7FFFh

1AFFFFh

1A7FFFh

19FFFFh

197FFFh

18FFFFh

187FFFh

17FFFFh

177FFFh

16FFFFh

167FFFh

15FFFFh

157FFFh

14FFFFh

147FFFh

13FFFFh

137FFFh

12FFFFh

127FFFh

11FFFFh

117FFFh

10FFFFh

107FFFh

0FFFFFh

0F7FFFh

0EFFFFh

0E7FFFh

0DFFFFh

0D7FFFh

0CFFFFh

0C7FFFh

0BFFFFh

0B7FFFh

0AFFFFh

0A7FFFh

09FFFFh

097FFFh

08FFFFh

087FFFh

07FFFFh

077FFFh

06FFFFh

067FFFh

05FFFFh

057FFFh

04FFFFh

047FFFh

03FFFFh

037FFFh

02FFFFh

027FFFh

01FFFFh

017FFFh

00FFFFh

007FFFh

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Table 3:

Ball Descriptions

47-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

D8, C8, B8, A8,

C7, B7, A7, C6,
B6, A6, C5, B5,
C3, A3, C2, B2,

A2, D1, C1, B1,

A0A20

Input

Address Inputs: Inputs for the address during READ and WRITE operations.
Addresses are internally latched during WRITE and ERASE cycles.

CE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.

OE#

Input

Output Enable: Enables the outputs buffer when LOW. When OE# is HIGH, the
output buffers are disabled.

WE#

Input

Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is either a WRITE to the command state machine (CSM) or to the memory array.

RP#

Input

Reset: When RP# is a logic LOW, the device is in reset mode, which drives the
outputs to High-Z and resets the write state machine (WSM). When RP# is at logic
HIGH, the device is in standard operation. When RP# transitions from logic LOW
to logic HIGH, the device resets all blocks to locked and defaults to the read array
mode.

WP#

Input

Write Protect: Controls the lock down function of the flexible locking feature.

E7, F7, D5, E5,
F4, D3, E3, F2,

D6, E6, F6, D4,

E4, F3, D2, E2

DQ0DQ15

Input/

Output

Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle during
PROGRAM command. Inputs commands to the command user interface when CE#
and WE# are active.

Supply

Block Erase and Program Power Supply: [V

PP1

= 0.9V1.95V or V

PP2

= 11.4V

12.6V]. A valid voltage on this contact allows block erase or data programming.
Memory contents cannot be altered when V

£ V

PPLK

. Block erase and program

at invalid V

voltages should not be attempted. It provides factory programming

compatibility when driven to 11.4V12.6V

Supply

Device Power Supply: [1.65V1.95V] Supplies power for device operation.

Supply

I/O Power Supply: [1.65V1.95V] Supplies power for input/output buffers. This
input should be tied directly to V

E8, F1

Supply

Do not float any ground ball.

Internally not connected.

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Command State Machine

Commands are issued to the command state

machine (CSM) using standard microprocessor write
timings. The CSM acts as an interface between exter-
nal microprocessors and the internal write state
machine (WSM). The available commands are listed in
Table 4, their definitions are given in Table 5 and their
descriptions in Table 6. Program and erase algorithms
are automated by an on-chip WSM. Table 7 shows the
CSM transition states.

Once a valid PROGRAM/ERASE command is

entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally and accomplish the
requested operation. A command is valid only if the
exact sequence of WRITE cycles is completed. After the
WSM completes its task, the WSM status bit (SR7) (see
Table 9) is set to a logic HIGH level (1), allowing the
CSM to respond to the full command set again.

Operations

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals CE# and
WE# must be at a logic LOW level (V

), and OE# and

RP# must be at logic HIGH (V

). The second opera-

tion, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control signals CE# and OE# must be at a logic
LOW level (V

), and WE# and RP# must be at logic

HIGH (V

Table 8 illustrates the bus operations for all the

modes: write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of oper-
ation. Changing the mode of operation requires that a
command code be entered into the CSM. An on-chip
status register is available. The status register allows
the monitoring of the progress of various operations
that can take place on a memory. The status register is
interrogated by entering a READ STATUS REGISTER
command onto the CSM (cycle 1) and reading the reg-
ister data on I/Os DQ0DQ7 (cycle 2). Status register
bits SR0SR7 correspond to DQ0DQ7 (see Table 9).

Command Definition

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 5 for the CSM command defini-
tions and data for each of the bus cycles.

Table 4:

Command State Machine Codes For Device Mode Selection

COMMAND DQ0DQ7

CODE ON DEVICE MODE

40h/10h

Program setup/alternate program setup

20h

Block erase setup

50h

Clear status register

60h

Protection configuration setup

70h

Read status register

90h

Read protection configuration register

98h

Read query

B0h

Program/erase suspend

C0h

Protection register program/lock

D0h

Program/erase resume erase confirm

FFh

Read array

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Status Register

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE# by reading the resulting sta-
tus code on I/Os DQ0DQ7. The high-order I/Os
(DQ8DQ15) are set to 00h internally, so only the low-
order I/Os (DQ0DQ7) need to be interpreted.

edge of OE# or CE#, whichever occurs last. Latching
the data prevents errors from occurring if the register
input changes during a status register read.

The status register provides the internal state of the

WSM to the external microprocessor. During periods
when the WSM is active, the status register can be
polled to determine the WSM status. Table 9 defines
the status register bits.

After monitoring the status register during a PRO-

GRAM/ERASE operation, the data appearing on DQ0
DQ7 remains as status register data until a new com-
mand is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.

Command State Machine Operations

The CSM decodes instructions for read array, read

protection configuration register, read query, read sta-
tus register, clear status register, program, erase, erase
suspend, erase resume, erase confirm, program setup,
alternate program setup, program suspend, program
resume, lock block, unlock block and lock down block,
chip protection register program, and chip protection
register lock. The 8-bit command code is input to the
device on DQ0DQ7 (see Table 4 for CSM codes and
Table 5 for command definitions). During a PROGRAM
or ERASE cycle, the CSM informs the WSM that a PRO-
GRAM or ERASE cycle has been requested. During a
PROGRAM cycle, the WSM controls the program
sequences and the CSM responds to a PROGRAM SUS-
PEND command only. During an ERASE cycle, the

CSM responds to an ERASE SUSPEND command only.
When the WSM has completed its task, the WSM status
bit (SR7) is set to a logic HIGH level and the CSM
responds to the full command set. The CSM stays in
the current command state until the microprocessor
issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when V

is within its correct

voltage range.

Clear Status Register

The internal circuitry can set, but not clear, the

block lock status bit (SR1), the V

status bit (SR3), the

program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, a READ
ARRAY command (FFh) must be issued before data
can be read from the memory array, or a READ STATUS
REGISTER command (70h) must be issued to read sta-
tus.

READ Operations

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY, and READ STATUS REGISTER.

Read Array

The array is read by entering the command code

FFh on DQ0DQ7. Control signals CE# and OE# must
be at a logic LOW level (V

), and WE# and RP# must be

at logic HIGH level (V

) to read data from the array.

Data is available on DQ0DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial power-
up or device reset, the device defaults to the read array
mode.

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Read Protection Configuration Register

The chip identification mode outputs four types of

information: the manufacturer/device identifier, the
block locking status, the protection register content,
and protection register lock. Two bus cycles are
required for this operation: the chip identification data
is read by entering the command code 90h on DQ0
DQ7 and the identification code address on the
address lines.

Control signals CE# and OE# must be at a logic LOW

level (V

), and WE# and RP# must be at a logic HIGH

level (V

) to read data from the protection configura-

tion register. Data is available on DQ0DQ15. To return
to read array mode, write the read array command
code FFh on DQ0DQ7. See Table 11 for further
details.

NOTE:

1. WA:Word address of memory location to be writ-

ten, or read

IA:Identification code address
BA:Address within the block
ID:Identification code data
SRD:Data read from the status register
QA:Query code address

QD:Query code data
WD:Data to be written at the location WA
PA:Protection register address
LPA:Lock protection register address
AD:Array data
PD:Protection register data
X: "Don't Care"

Table 5:

Command Definitions

COMMAND

FIRST BUS CYCLE

SECOND BUS CYCLE

OPERATION

ADDRESS

DATA

OPERATION

ADDRESS

DATA

READ ARRAY

WRITE

FFh

READ

READ PROTECTION
CONFIGURATION REGISTER

WRITE

90h

READ

READ STATUS REGISTER

WRITE

70h

READ

SRD

CLEAR STATUS REGISTER

WRITE

50h

READ QUERY

WRITE

98h

READ

BLOCK ERASE SETUP

WRITE

20h

WRITE

D0h

PROGRAM SETUP/ALTERNATE
PROGRAM SETUP

WRITE

40h/10h

WRITE

PROGRAM/ERASE SUSPEND

WRITE

B0h

PROGRAM/ERASE RESUME
ERASE CONFIRM

WRITE

D0h

LOCK BLOCK

WRITE

60h

WRITE

01h

UNLOCK BLOCK

WRITE

60h

WRITE

D0h

LOCK DOWN BLOCK

WRITE

60h

WRITE

2Fh

PROTECTION REGISTER PROGRAM
SETUP

WRITE

C0h

WRITE

PROTECTION REGISTER LOCK

WRITE

C0h

WRITE

LPA

FFFDh

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Table 6:

Command Descriptions

CODE

DEVICE MODE

BUS

CYCLE

DESCRIPTION

10h

Alt. Program Setup

First

Operates the same as a PROGRAM SETUP command.

20h

Erase Setup

First

Prepares the CSM for an ERASE CONFIRM command. If the next command is
not an ERASE CONFIRM command, the command will be ignored, and the
device will go to read status mode and wait for another command.

40h

Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM operation, the
second cycle latches addresses and data and initiates the WSM to execute the
program algorithm. The Flash device outputs status register data on the
falling edge of OE# or CE#, whichever occurs first.

50h

Clear Status Register

First

The WSM can set the block lock status (SR1), V

Status (SR3), program status

(SR4),and erase status (SR5) bits in the status register to "1," but it cannot
clear them to "0." Issuing this command clears those bits to "0."

60h

Protection
Configuration Setup

First

Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK, or BLOCK LOCK DOWN, then
the CSM will set both the program and erase status register bits to indicate a
command sequence error.

70h

Read Status Register

First

Places the device into read status register mode. Reading the device will
output the contents of the status register for the addressed bank. The device
will automatically enter this mode for the addressed bank after a PROGRAM
or ERASE operation has been initiated.

90h

Read Protection
Configuration
Register

First

Puts the device into the read protection configuration register mode so that
reading the device will output the manufacturer/device codes, block lock
status, protection register, or protection register lock.

98h

Read Query

First

Puts the device into the read query mode so that reading the device will
output common flash interface information.

B0h

Program/Erase
Suspend

First

Suspends the currently executing PROGRAM/ERASE operation. The status
register will indicate when the operation has been successfully suspended by
setting either the program suspend (SR2) or erase suspend (SR6) and the
WSM status bit (SR7) to a "1" (ready). The WSM will continue to idle in the
suspend state, regardless of the state of all input control pins except RP#,
which will immediately shut down the WSM and the remainder of the chip if
RP# is driven to V

C0h

Program Device
Protection Register

First

Writes a specific code into the device protection register.

Lock Device
Protection Register

First

Locks the device protection register; data can no longer be changed.

D0h

Erase Confirm

Second

If the previous command was an ERASE SETUP command, then the CSM will
close the address and data latches, and it will begin erasing the block
indicated on the address pins. During programming/erase, the device will
respond only to the READ STATUS REGISTER, PROGRAM/ERASE SUSPEND
commands and will output status register data on the falling edge of OE# or
CE#, whichever occurs last.

Program/Erase
Resume

First

If a program or erase operation was previously suspended, this command will
resume the operation.

FFh

Read Array

First

During the read array mode, array data will be output on the data bus.

01h

Lock Block

Second

If the previous command was PROTECTION CONFIGURATION SETUP, the CSM
will latch the address and lock the block indicated on the address bus.

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Read Query

The read query mode outputs common flash inter-

face (CFI) data when the device is read (see Table 19).
Two bus cycles are required for this operation. It is pos-
sible to access the query by writing the read query
command code 98h on DQ0DQ7. Control signals CE#
and OE# must be at a logic LOW level (V

), and WE#

and RP# must be at logic HIGH level (V

) to read data

from the query. The CFI data structure contains infor-
mation such as block size, density, command set, and
electrical specifications. To return to read array mode,
write the read array command code FFh on DQ0DQ7.

Read Status Register

The status register is read by entering the command

code 70h on DQ0DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. In a READ cycle, the
register data is updated on the falling edge of OE# or
CE#, whichever occurs last.

PROGRAMMING Operations

There are two CSM commands for programming:

PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 4).

After the desired command code is entered (10h or

40h command code on DQ0DQ7), the WSM takes
over and correctly sequences the device to complete
the PROGRAM operation. The WRITE operation may
be monitored through the status register (see the Sta-
tus Register section). During this time, the CSM will
only respond to a PROGRAM SUSPEND command
until the PROGRAM operation has been completed,
after which time all commands to the CSM become
valid again. The PROGRAM operation can be sus-
pended by issuing a PROGRAM SUSPEND command
(B0h). Once the WSM reaches the suspend state, it
allows the CSM to respond only to READ ARRAY, READ
STATUS REGISTER, READ PROTECTION CONFIGU-
RATION, READ QUERY, and PROGRAM RESUME. Dur-
ing the PROGRAM SUSPEND operation, array data
should be read from an address other than the one
being programmed. To resume the PROGRAM opera-
tion, a PROGRAM RESUME command (D0h) must be
issued to cause the CSM to clear the suspend state pre-
viously set (see Figure 5 for programming operation
and Figure 6 for program suspend and program
resume).

During programming, V

must remain in the

appropriate V

voltage range as shown in the Recom-

mended Operating Conditions table.

ERASE Operations

An ERASE operation must be used to initialize all

bits in an array block to "1". After BLOCK ERASE CON-
FIRM is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic "1". Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid
address within that block. Block erasure is initiated by
a command sequence to the CSM: BLOCK ERASE
SETUP (20h) followed by BLOCK ERASE CONFIRM
(D0h) (see Figure 7). A two-command erase sequence
protects against accidental erasure of memory con-
tents.

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic "0",
data is verified, all bits in the block are erased, and
finally verification is performed to ensure that all bits
are correctly erased. Monitoring the ERASE operation
is possible through the status register (see the Status
Register section).

During the execution of an ERASE operation the

ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows the
CSM to respond only to the READ ARRAY, READ STA-
TUS REGISTER, READ QUERY, READ CHIP PROTEC-
TION CONFIGURATION, PROGRAM SETUP,
PROGRAM/ERASE RESUME and LOCK SETUP (see
the Block Locking section). During the ERASE SUS-
PEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 8). It is also possible that an
ERASE can be suspended and a write to another block
can be initiated. After the completion of a write, an
erase can be resumed by writing an ERASE RESUME
command.

2 ME

G x 16

8V E

NCE

+ B

OOT

BLOC

K
FLAS

M
E

M
O

PRELI

M
INA

2 Meg

16
,
1.
8V
En

c
ed
+ B

t
B

l
o

c
k

l
ash

Mem

i
c
r
o

ch
n

l
o

,
In
c.

, r

s
e

r
v

s

t
h

r
i
g

t
t

ch
a

r
o

c
t
s
o

r
s

c
if

t
io

s
w
i
t
h

t

n

t
i
ce
.

MT28

A18_

12_

f
m
-

ev
.
A 4/

03 R

.

A,
Pu

.
3/
03

EN

c
r
o

Tec

l
o

,
I

c
.

Table 7:

Command State Machine Current/Next States

CURRENT
STATE

SR7

COMMAND INPUT AND NEXT STATE

DATA

WHEN

READ

ARRAY

READ

CONFIG.

READ

STATUS

REG.

CLEAR

STATUS

REG.

READ

QUERY

ERASE

SETUP

PROGRAM/

ERASE

RESUME,

UNLOCK

PROGRAM

SETUP

PROGRAM/

ERASE

SUSPEND

OTP PROGRAM

SETUP

LOCK

SETUP

LOCK

DOWN

10/40

Read Array

Array

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Read Status

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Read Config.

Config.

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Read Query

CFI

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Clear Status

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Program Setup

Status

Program

Program (not
done)

Status

Program

Suspend Status

Program

Program (done)

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Program
Suspend Read
Array

Array

Program

Suspend

Read

Array

Program

Suspend

Read

Config.

Program

Suspend

Read

Status

Program

Suspend

Clear

Status

Program

Suspend

Read

Query

Program
Suspend

Read Array

Program

Program Suspend Read Array

Program
Suspend Read
Status

Status

Program

Suspend

Read

Array

Program

Suspend

Read

Config.

Program

Suspend

Read

Status

Program

Suspend

Clear

Status

Program

Suspend

Read

Query

Program
Suspend

Read Array

Program

Program Suspend Read Array

Program
Suspend Read
Config.

Config.

Program

Suspend

Read

Array

Program

Suspend

Read

Config.

Program

Suspend

Read

Status

Program

Suspend

Clear

Status

Program

Suspend

Read

Query

Program
Suspend

Read Array

Program

Program Suspend Read Array

Program
Suspend Read
Query

CFI

Program

Suspend

Read

Array

Program

Suspend

Read

Config.

Program

Suspend

Read

Status

Program

Suspend

Clear

Status

Program

Suspend

Read

Query

Program
Suspend

Read Array

Program

Program Suspend Read Array

Erase Setup

Status

Erase Command Error

Erase

Erase Command Error

Erase (Not Done)

Status

Erase

Erase Suspend

Read Status

Erase

Erase (Done)

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Erase Command
Error

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Program Setup
in Erase Suspend

Status

Program in Erase Suspend

Erase Suspend
Program (Not
Done)

Status

Program in Erase Suspend

Erase Suspend

Program

Suspend Read

Status

Program in Erase Suspend

Erase Suspend
(Done)

Status

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Read Array

Array

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

2 ME

G x 16

8V E

NCE

+ B

OOT

BLOC

K
FLAS

M
E

M
O

PRELI

M
INA

2 Meg

16
,
1.
8V
En

c
ed
+ B

t
B

l
o

c
k

l
ash

Mem

i
c
r
o

ch
n

l
o

,
In
c.

, r

s
e

r
v

s

t
h

r
i
g

t
t

ch
a

r
o

c
t
s
o

r
s

c
if

t
io

s
w
i
t
h

t

n

t
i
ce
.

MT28

A18_

12_

f
m
-

ev
.
A 4/

03 R

.

A,
Pu

.
3/
03

EN

c
r
o

Tec

l
o

,
I

c
.

Erase Suspend
Read Status

Status

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Read Config.

Config.

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Read Query

CFI

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Lock Setup

Status

Erase Suspend Lock Error

Erase Suspend

Unlock

Erase Suspend Lock Error

Erase

Suspend

Lock

Erase

Suspend

Lock Down

Erase Suspend
Lock

Status

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Lock Down

Status

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Unlock

Status

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Lock Error

Status

Erase

Suspend

Read

Array

Erase

Suspend

Read

Config.

Erase

Suspend

Read

Status

Erase

Suspend

Clear

Status

Erase

Suspend

Read

Query

Erase

Suspend

Read Array

Erase

Program Setup

in Erase

Suspend

Erase Suspend Read Array

Erase

Suspend

Lock

Setup

Erase Suspend Read

Array

Erase Suspend
Program
Suspend Read
Array

Array

Erase

Suspend

Program

Suspend

Read

Array

Erase

Suspend

Program

Suspend

Read

Config.

Erase

Suspend

Program

Suspend

Read

Status

Erase

Suspend

Program

Suspend

Clear

Status

Erase

Suspend

Program

Suspend

Read

Query

Erase

Suspend
Program
Suspend

Read Array

Erase Suspend

Program

Erase Suspend Program Suspend Read Array

Erase Suspend
Program
Suspend Read
Status

Status

Erase

Suspend

Program

Suspend

Read

Array

Erase

Suspend

Program

Suspend

Read

Config.

Erase

Suspend

Program

Suspend

Read

Status

Erase

Suspend

Program

Suspend

Clear

Status

Erase

Suspend

Program

Suspend

Read

Query

Erase

Suspend
Program
Suspend

Read Array

Erase Suspend

Program

Erase Suspend Program Suspend Read Array

Erase Suspend
Program
Suspend Read
Config.

Config.

Erase

Suspend

Program

Suspend

Read

Array

Erase

Suspend

Program

Suspend

Read

Config.

Erase

Suspend

Program

Suspend

Read

Status

Erase

Suspend

Program

Suspend

Clear

Status

Erase

Suspend

Program

Suspend

Read

Query

Erase

Suspend
Program
Suspend

Read Array

Erase Suspend

Program

Erase Suspend Program Suspend Read Array

Erase Suspend
Program
Suspend Read
Query

CFI

Erase

Suspend

Program

Suspend

Read

Array

Erase

Suspend

Program

Suspend

Read

Config.

Erase

Suspend

Program

Suspend

Read

Status

Erase

Suspend

Program

Suspend

Clear

Status

Erase

Suspend

Program

Suspend

Read

Query

Erase

Suspend
Program
Suspend

Read Array

Erase Suspend

Program

Erase Suspend Program Suspend Read Array

Table 7:

Command State Machine Current/Next States (continued)

CURRENT
STATE

SR7

COMMAND INPUT AND NEXT STATE

DATA

WHEN

READ

ARRAY

READ

CONFIG.

READ

STATUS

REG.

CLEAR

STATUS

REG.

READ

QUERY

ERASE

SETUP

PROGRAM/

ERASE

RESUME,

UNLOCK

PROGRAM

SETUP

PROGRAM/

ERASE

SUSPEND

OTP PROGRAM

SETUP

LOCK

SETUP

LOCK

DOWN

10/40

2 ME

G x 16

8V E

NCE

+ B

OOT

BLOC

K
FLAS

M
E

M
O

PRELI

M
INA

2 Meg

16
,
1.
8V
En

c
ed
+ B

t
B

l
o

c
k

l
ash

Mem

i
c
r
o

ch
n

l
o

,
In
c.

, r

s
e

r
v

s

t
h

r
i
g

t
t

ch
a

r
o

c
t
s
o

r
s

c
if

t
io

s
w
i
t
h

t

n

t
i
ce
.

MT28

A18_

12_

f
m
-

ev
.
A 4/

03 R

.

A,
Pu

.
3/
03

EN

c
r
o

Tec

l
o

,
I

c
.

OTP Program
Setup

Status

OTP Program

OTP Program
(Not Done)

Status

OTP Program

OTP Program
(Done)

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Lock Setup

Status

Lock Error

Unlock

Lock Error

Lock

Lock Down

Lock

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Lock Down

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Unlock

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Lock Error

Status

Read

Array

Read

Config.

Read

Status

Read Array

Read

Query

Erase

Setup

Read Array

Program Setup

Read Array

OTP Program

Setup

Lock

Setup

Read Array

Table 7:

Command State Machine Current/Next States (continued)

CURRENT
STATE

SR7

COMMAND INPUT AND NEXT STATE

DATA

WHEN

READ

ARRAY

READ

CONFIG.

READ

STATUS

REG.

CLEAR

STATUS

REG.

READ

QUERY

ERASE

SETUP

PROGRAM/

ERASE

RESUME,

UNLOCK

PROGRAM

SETUP

PROGRAM/

ERASE

SUSPEND

OTP PROGRAM

SETUP

LOCK

SETUP

LOCK

DOWN

10/40

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Block Locking

The MT28F320A18A Flash memory provides a flexi-

ble locking scheme that allows each block to be indi-
vidually locked or unlocked with no latency.

The device offers two-level protection for the

blocks. The first level allows software-only control of
block locking (for data that needs to be changed fre-
quently), while the second level requires hardware
interaction before locking can be changed (code that
does not require frequent updates). Control pins WP#,
DQ1, and DQ0 define the state of a block; for example,
state [001] means WP# = 0, DQ1 = 0 and DQ0 = 1.
Table 10 defines all of the possible locking states.

NOTE:

All blocks are software-locked upon power-up

sequence completion.

Locking operation

The following summarizes the locking operation.

1. All blocks are locked on power-up. They can then be

unlocked or locked down with the UNLOCK and
LOCK DOWN commands.

2. The LOCK DOWN command locks a block and pre-

vents it from being unlocked when WP# = 0.
· When WP# = 1, lock down is overridden. Com-

mands can then unlock/lock locked down blocks.

· When WP# returns to 0, locked down blocks

return to lock down.

· Lock down is cleared only when the device is

reset or powered down.

Locked State

After a power-up sequence completion, or after a

reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a
locked block will return an error on bit SR1 of the sta-
tus register. The status of a locked block can be
changed to unlocked or lock down using the appropri-
ate software commands. Writing the lock command
sequence, 60h followed by 01h, can lock an unlocked
block.

Unlocked State

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked
down using the appropriate software command
sequence (see Table 5).

Locked Down State

Blocks that are locked down (state [011]) are pro-

tected from PROGRAM and ERASE operations, but
their protection status cannot be changed using soft-
ware commands alone. A locked or unlocked block can
be locked down by writing the lock down command
sequence, 60h followed by 2Fh. Locked down blocks
revert to the locked state when the device is reset or
powered down.

The lock down function is dependent on the WP#

input pin. When WP# = 0, blocks in lock down [011] are
protected from program, erase and lock status
changes. When WP# = 1, the lock down function is dis-
abled ([111]) and locked down blocks can be individu-
ally unlocked by a software command to the [110]
state, where they can be erased and programmed.
These blocks can then be relocked [111] and unlocked
[110] as desired as long as WP# remains HIGH. When
WP# goes LOW, blocks that were previously locked
down return to the locked down state [011] regardless
of any changes made while WP# was HIGH. Device
reset or power-down resets all locked blocks, including
those in lock down, to locked state (see Table 10).

Reading a Block's Lock Status

The lock status of every block can be read in the

read device identification mode. To enter this mode,
write 90h to the device. Subsequent READs at block
address + 00002h will output the lock status of that
block. The lowest two outputs, DQ0 and DQ1, repre-
sent the lock status. DQ0 indicates the block lock/
unlock status and is set by the LOCK command and
cleared by the UNLOCK command. It is also automati-
cally set when entering lock down. DQ1 indicates lock
down status and is set by the LOCK DOWN command.
It can only be cleared by reset or power-down, not by
software. Table 10 shows the locking state transition
scheme.

Locking Operations during Erase Sus-
pend

Changes to block lock status can be performed dur-

ing an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down.
This is useful in the case when another block needs to
be updated while an ERASE operation is in progress.

To change block locking during an ERASE opera-

tion, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

lock status will be changed. After completing LOCK,
READ or PROGRAM operations, resume the ERASE
operation with the ERASE RESUME command (D0h).

If a block is locked or locked down during a suspend

erase of the same block, the locking status bits will
change immediately. But, when resumed, the erase
operation will complete.

A locking operation cannot be performed during a

PROGRAM SUSPEND.

Status Register Error Checking

Using nested locking or program command

sequences during ERASE SUSPEND can introduce
ambiguity into status register results.

Following protection configuration setup (60h), an

invalid command will produce a lock command error
(SR4 and SR5 will be set to "1") in the status register. If
a lock command error occurs during an ERASE SUS-
PEND, SR4 and SR5 will be set to "1" and will remain at
"1" after the ERASE SUSPEND is resumed. When the
ERASE is complete, any possible error during the
ERASE cannot be detected via the status register
because of the previous locking command error.

A similar situation happens if an error occurs during

a program operation error nested within an ERASE
SUSPEND.

Table 8:

Bus Operations

MODE

RP#

CE#

OE#

WE#

ADDRESS

DQ0DQ15

Read (array, status registers, device
identification register, or query)

OUT

Standby

High-Z

Output Disable

High-Z

Reset

High-Z

Write

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Table 9:

Status Register Bit Definition

WSMS

ESS

PSS

BLS

STATUS BIT

STATUS REGISTER BIT

DESCRIPTION

SR7

WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy

Check write state machine bit first to determine word program
or block erase completion, before checking program or erase
status bits.

SR6

ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in Progress/Completed

When ERASE SUSPEND is issued, WSM halts execution and sets
both WSMS and ESS bits to "1." ESS bit remains set to "1" until
an ERASE RESUME command is issued.

SR5

ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful BLOCK ERASE

When this bit is set to "1," WSM has applied the maximum
number of erase pulses to the block and is still unable to verify
successful block erasure.

SR4

PROGRAM STATUS (PS)
1 = Error in PROGRAM
0 = Successful PROGRAM

When this bit is set to "1," WSM has attempted but failed to
program a word.

SR3

STATUS (V

1 = V

Low Detect, Operation Abort

0 = V

= OK

The V

status bit does not provide continuous indication of the

level. The WSM interrogates the V

level only after the

program or erase command sequences have been entered. The
WSM informs the system if V

< 0.9V. The V

level is also

checked before the PROGRAM/ERASE operation is verified by
the WSM.

SR2

PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed

When PROGRAM SUSPEND is issued, WSM halts execution and
sets both WSMS and PSS bits to "1." PSS bit remains set to "1"
until a PROGRAM RESUME command is issued.

SR1

BLOCK LOCK STATUS (BLS)
1 = PROGRAM/ERASE Attempted on a
Locked Block; Operation Aborted
0 = No operation to locked blocks

If a PROGRAM or ERASE operation is attempted to one of the
locked blocks, this is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.

SR0

RESERVED FOR FUTURE ENHANCEMENTS

This bit is reserved for future enhancements.

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Figure 5: Automated Word

Programming Flowchart

NOTE:

1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

BUS
OPERATION COMMAND

COMMENTS

WRITE

WRITE
PROGRAM
SETUP

Data = 40h or 10h
Addr = Address of word to

be programmed

WRITE

WRITE DATA

Data = Word to be

programmed

Addr = Address of word to

be programmed

READ

Status register data
Toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent words.
Write FFh after the last word programming operation to
return the device to read array mode.

BUS
OPERATION COMMAND

COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3
1 = Detect V

LOW

Standby

Check SR4

1 = Word program error

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Figure 7: BLOCK ERASE Flowchart

NOTE:

1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR 7 = 1?

Start

BLOCK ERASE Passed

Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

ERASE

SUSPEND Loop

YES

SR1 = 0?

YES

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted
on a Locked Block

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

BUS
OPERATION COMMAND

COMMENTS

WRITE

WRITE ERASE
SETUP

Data = 20h
Block Addr = Address
within block to be
erased

WRITE

ERASE

Data = D0h
Block Addr = Address
within block to be
erased

READ

Status register data
Toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to return
the device to read array mode.

BUS
OPERATION COMMAND

COMMENTS

Standby

Check SR1
1 = Detect locked
block

Standby

Check SR3

1 = Detect Vpp block

Standby

Check SR4 and SR5
1 = Block erase
command error

Standby

Check SR5

1 = Block erase error

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

NOTE:

1. Other locations within the configuration address space are reserved by Micron for future use.
2. "XX" specifies the block address of lock configuration.

Table 10: Block Locking State Transition

WP#

DQ1

DQ0

NAME

ERASE/

PROGRAM

ALLOWED

LOCK

UNLOCK

LOCK DOWN

Unlocked

Yes

To [001]

No Change

To [011]

Locked

(Default)

No Change

To [000]

To [011]

Lock down

No Change

Unlocked

Yes

To [101]

No Change

To [111]

Locked

No Change

To [100]

To [111]

Lock down

disabled

Yes

To [111]

No Change

To [111]

Lock down

disabled

No Change

To [110]

No Change

Invalid

No Change

Table 11: Chip Configuration Addressing

ITEM

ADDRESS

DATA

Manufacturer Code (x16)

000000h

002Ch

Device Code

000001h

32Mb

00C2h
00C3h

Top boot configuration

Bottom boot configuration

Block Lock Configuration
Block is unlocked
Block is locked
Block is locked down

BA + 000002h

Lock

DQ0 = 0
DQ0 = 1
DQ1 = 1

Chip Protection Register Lock

80h

PR-Lock

DQ1 = 0 locked

DQ1 = 1 unlocked

Chip Protection Register 1

81h84h

Factory Data

Chip Protection Register 2

85h88h

User Data

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Chip Protection Register

A 128-bit protection register can be used to fulfill

the security considerations in the system (preventing
the device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit unchangeable
number. The other segment is left blank for customers
to program as desired. (See Figure 9).

Figure 9: Protection Register Memory

Map

Reading the Chip Protection Register

The chip protection register is read in the device

identification mode, loading the 90h command to the
bank containing address 00h. Once in this mode,
READ cycles from addresses shown in Table 11 retrieve
the specified information. To return to the read array
mode, write the READ ARRAY command (FFh).

Programming the Chip Protection
Register

Executing the PROTECTION PROGRAM command

enables the customer to program the user portion of
the protection register. First, write the PROTECTION
PROGRAM SETUP command, C0h; then write address
and data to program.

Attempts should not be made to address PROTEC-

TION PROGRAM commands outside the defined pro-
tection register address space. Attempting to program
to a previously locked protection register segment will
result in a status register error (program error bit SR4
and lock error bit SR1 = 1)

Locking the Chip Protection Register

The customer-programmable segment of the pro-

tection register can be locked by programming bit 1 of
the PR lock location to "0". Bit 0 of this location is pro-
grammed to a "0" at the Micron factory to protect the
unique device number. Bit 1 is set using the PROTEC-
TION PROGRAM command to program FFFDh to the
PR lock location. After these bits have been pro-
grammed, no further changes can be made to the val-
ues stored in the protection register. PROTECTION
PROGRAM commands to a locked section will result in
a status register error program error bit SR4 and lock
error bit SR1 will be set to 1. Protection register lockout
is not reversible.

Program and Erase Voltages

The MT28F320A18A Flash memory provides in-sys-

tem programming and erase with V

in the 0.9V

1.95V (V

PP1

) range. The 12V V

PP2

) mode program-

ming is offered for compatibility with existing pro-
gramming equipment. The fast programming
algorithm is enabled at V

= V

PP2

The device can withstand 100,000 WRITE/ERASE

operations when V

= V

PP1

or 100 WRITE/ERASE

operations and 10 cumulative hours when V

= V

PP2

In addition to the flexible block locking, the V

pro-

gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V

is below V

PPLK

, any PROGRAM or ERASE

operation will result in an error, prompting the corre-
sponding status register bit (SR3) to be set.

During WRITE and ERASE operations, the WSM

monitors the V

voltage level. WRITE/ERASE opera-

tions are allowed only when V

is within the range

specified in T

ABLE

12.

When V

is below V

LKO

or below V

PPLK

, any

WRITE/ERASE operation will be disabled.

4 Words

Factory-Programmed

4 Words

User-Programmed

PR Lock

88h

85h

84h

81h

80h

Table 12: V

Range (V)

MIN

MAX

In-System (V

0.9

1.95

In-Factory (V

11.4

12.6

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

READ Cycle

Addresses can be accessed in a random order with

an access time given by

AA = 70ns.

When CE# and OE# are LOW, the data is placed on

the data bus and the processor can read the data.

Standby Mode

supply current is reduced by applying a logic

HIGH level on CE# and RP# to enter the standby mode.
In the standby mode, the outputs are placed in High-Z.
Applying a CMOS logic HIGH level on CE# and RP#
reduces the current to I

CC2

(MAX). If the device is dese-

lected during an ERASE operation or during program-
ming, the device continues to draw current until the
operation is complete.

Automatic Power Save Mode (APS)

Substantial power savings are realized during peri-

ods when the array is not being read and the device is
in the active mode. During this time, the device

switches to the automatic power saving mode. When
the device switches to this mode, I

is reduced to

CC2

. The low level of power is maintained until

another operation is initiated. In this mode, the I/O
pins retain the data from the last memory address read
until a new address is initiated. This mode is entered
automatically if no address or control signal toggles.

Power-Up Sequence

The following power-up sequence is recommended

to properly initialize internal chip operations:

· At power-up, RST# should be kept at V

for 2µ

after V

reaches V

(MIN).

· VccQ should not come up before Vcc.
· V

should be kept at V

to maximize data integ-

rity.

When the power-up sequence is completed, RST#

should be brought to V

. To ensure proper power-up,

the rise time of RST# (10%90%) should be < 10µ

NOTE:

Stresses greater than those listed under Table 13 may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Table 13: Absolute Ratings

PAREMETERS/CONDITIONS

MIN

MAX

UNITS

Voltage to any ball except V

and V

with respect to V

-0.5

+2.45

voltage (for BLOCK ERASE and PROGRAM with Respect to Vss)

-0.5

+13.5

and V

Q Supply Voltage with Respect to V

-0.3 +2.45

Output Short Circuit Current

100

Operating Temperature Range

-40 +85

ºC

Storage Temperature Range

-55 ºC

+125

ºC

Soldering Cycle

260ºC for 10s

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

NOTE:

1. Test conditions are V

= V

(MAX), CE# = V

, OE# = V

; all other inputs at V

or V

2. APS mode reduces I

to approximately I

2 levels.

3. RP# = V

or V

Table 15: DC Characteristics

PARAMETER

SYMBOL

= 1.65V1.95V

UNIT

Q = 1.65V1.95V

MIN

TYP

MAX

Input Low Voltage

-0.2

0.2

Input High Voltage

Q - 0.2

Q + 0.2

Output Low Voltage
I

= 100µA

0.1

Output High Voltage
I

= 100µA

Q - 0.1

Lock Out Voltage

PPLK

0.4

During Program/Erase Operations

0.9

1.95

11.4

12.6

Program/Erase Lock Voltage

LKO

Input Leakage Current

-1

Output Leakage Current

-1

Read Current, 70ns cycle

1,2

Standby Current

Program Current
V

= V

25
12

40
40

mA
mA

Erase Current
V

= V

25
25

40
40

mA
mA

Erase Suspend Current

= V

Program Suspend Current

= V

Read Current

£ V

0.5

Standby Current

= V

0.5

Erase Suspend Current

= V

0.5

Program Suspend Current

= V

0.5

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

NOTE:

1. See Figures 11 and 12 for timing requirements and output load configuration.

Table 16: READ Cycle Timing Requirements

PARAMETER

SYMBOL

-70

UNITS

= 1.65V1.95V

MIN

MAX

Address to output delay

CE# LOW to output delay

ACE

OE# LOW to output delay

AOE

RP# HIGH to output delay

RWH

150

CE# or OE# HIGH to output High-Z

Output hold from address, CE#, or OE# change

READ cycle time

Table 17: WRITE Cycle Timing Requirements

PARAMETER

SYMBOL

-70

UNITS

= 1.65V1.95V

MIN

MAX

RP# HIGH recovery to WE# going LOW

150 ns

CE# setup to WE# going LOW

Write pulse width

Data setup to WE# going HIGH

Address setup to WE# going HIGH

CE# hold from WE# HIGH

Data hold from WE# HIGH

Address hold from WE# HIGH

Write pulse width HIGH

WPH

RP# pulse width

100

WP# setup to WE# going HIGH

RHS

200

setup to WE# going HIGH

VPS

200

Write recovery before READ

WOS

WP# hold from valid SRD

RHH

hold from valid SRD

VPPH

WE# HIGH to data valid

AA+50

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

Table 19: CFI

OFFSET

DATA

DESCRIPTION

2Ch

Manufacturer Code

C2h/C3h

32Mb Top /Bottom Boot Block Device Code

03 - 0F

reserved

Reserved

10, 11

0051, 0052 "QR"

0059

"Y"

13, 14

0003, 0000 Primary OEM Command Set

15, 16

0035, 0000 Address for Primary Extended Table

17, 18

0000, 0000 Alternate OEM Command Set

19, 1A

0000, 0000 Address for OEM Extended Table

0017

MIN for Erase/Write; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

0019

MAX for Erase/Write; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

00B4

MIN for Erase/Write; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD, 0000 = V

input

00C6

MAX for Erase/Write; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD, 0000 = V

input

0003

Typical timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Typical timeout for maximum size multiple byte/word program, 2

µs, 0000 = not supported

0009

Typical timeout for individual block erase, 2

ms, 0000 = not supported

0000

Typical timeout for full chip erase, 2

ms, 0000 = not supported

000C

Maximum timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Maximum timeout for maximum size multiple byte/word program, 2

µs, 0000 = not supported

000C

Maximum timeout for individual block erase, 2

ms, 0000 = not supported

0000

Maximum timeout for full chip erase, 2

ms, 0000 = not supported

0016

Device size, 2

bytes; 0016 for 32Mb

0001

Bus Interface x8 = 0, x16 = 1, x8/x16 = 2

0000

Flash device interface description 0000 = async

2A, 2B

0000, 0000 Maximum number of bytes in multi-byte program or page, 2

0002

Number of erase block regions within device (4K words and 32K words)

0007

Bottom boot erase block region information 1, 8 blocks ...

003E

Top boot erase block region information 1, 8 blocks ...

0000

Bottom and top erase block region information 1, 8 blocks ...

0020

Bottom ...of 8KB

0000

Top ...of 8KB

0000

Bottom ...of 8KB

0001

Top ...of 8KB

003E

Bottom 63 = 3Eh for 32Mb

0007

Top 63 = 3Eh for 32Mb

0000

Bottom and top 63 = 3Eh for 32Mb

0000

Bottom ...64KB

0020

Top ...64KB

0001

Bottom ...64KB

0000

Top ...64KB

35, 36

0050, 0052 "PR"

0049

"I"

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F320A18_12_2.fm Rev. A 4/03 EN

0030

Major Version number ASCII

0031

Minor version number, ASCII

3B
3C

0066
0000
0000
0000

Optional Feature and Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = no = 0
Bit 8 Synchronous read supported = no = 0
Bit 9 Simultaneous operation supported = no = 0

0001

Program supported after erase suspend = yes

3F, 40

0003, 0000 Bit 0 block lock status active = yes

Bit 1 block lock down active = yes

0018

supply optimum, 00 = not supported, Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

00C0

supply optimum, 00 = not supported, Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD

0001

Number of protection register fields in JEDEC ID space

44, 45

0080, 0000 Lock bytes LOW address, lock bytes HIGH address

46, 47

0003, 0003 2

factory programmed bytes, 2

user programmable bytes

0000

Background Operation
0000 = Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
00004 = 50% block split

0000

Burst Mode Type
0000 = No burst mode
00x1 = 4 words max
00x2 = 8 words max
00x13 = 16 words max
001x = Linear burst, and/or
002x = Interleaved burst, and/or
004x = Continuous burst

0000

Page Mode Type
0000 = No page mode
0001 = 4-word page
0002 = 8-word page
0003 = 16-word page
0004 = 32-word page

0000

Not used

Table 19: CFI (continued)

OFFSET

DATA

DESCRIPTION

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

PRELIMINARY

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice..

MT28F320A18_12_2.fm Rev. A 4/03 EN

Figure 15: 47-Ball FBGA

NOTE:

1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.
3. Micron recommends a one-to-one ratio between the solder ball pad and the PCB. For more information, see Micron

Technical Note, TN-00-11, "SMT Recommendations for BGA Assembly."

Data Sheet Designations

Preliminary:

This data sheet contains initial characertization limits that are subject to change upon full characterization of produc-

tion.

3.25 ±0.05

3.75

0.75 TYP

0.75

TYP

PIN A1 ID

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø 0.27mm

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

PIN A1 ID

7.00 ±0.10

1.20 MAX

3.50 ±0.05

2.625 ±0.05

5.25

0.80 ±.075

0.10

SEATING PLANE

0.35

47X Ø

1.875 ±0.05

6.50 ±0.10

BALL A1

SOLDER BALL DIAMETER REFERS TO

POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø .33mm.

BALL A8

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT28F320A18A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT28F320A18A