Document Outline
- Features/Options
- General Description
- Architecture and Memory Organization
- Device Marking
- Table 1, Cross Reference for Abbreviated Device Marks
- Part Numbering Information
- Figure 1, Part Number Chart
- Table 2, Valid Part Number Combinations
- Functional Block Diagram
- Figure 2, Bottom Boot Block Device
- Figure 3, Top Boot Block Device
- Ball Descriptions
- Command State Machine (CSM)
- Table 3, Command State Machine Codes For Device Mode Selection
- Operations
- Command Definition
- Status Register
- CSM Operations
- Table 4, Command Definitions
- Table 5, Command Descriptions
- Table 5, Command Descriptions (continued)
- CLEAR STATUS REGISTER
- READ Operations
- Read Array
- Read Protection Configuration Data
- Read Query
- Read Status Register
- Programming Operations
- ERASE Operations
- Table 6, Bus Operations
- Table 7, Status Register Bit Definition
- Figure 4, Automated Word Programming Flowchart
- Figure 5, PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
- Figure 6, BLOCK ERASE Flowchart
- Figure 7, ERASE SUSPEND/ERASE RESUME Flowchart
- READ-While-WRITE/ERASE Concurrency
- Figure 8, READ-While-WRITE Concurrency
- Block Locking
- Locked State
- Unlocked State
- Unlocked State
- Reading a Block's Lock Status
- Table 8 Block Locking State Transition
- Locking Operations During ERASE SUSPEND
- Table 9, Chip Configuration Addressing
- Chip Protection Register
- Figure 9, Protection Register Memory Map
- Reading the Chip Protection Register
- Programming the Chip Protection Register
- Asynchronous READ Cycle
- Page Read Mode
- VPP/VCC Program and Erase Voltages
- Table 10, VPP Range (V)
- Standby Mode
- Automatic Power Save Mode (APS)
- Device Reset
- Power-Up Sequence
- Absolute Maximum Ratings
- Operating Conditions
- Figure 10, AC Input/Output Reference Waveform
- Figure 11, Output Load Circuit
- DC Characteristics
- Capacitance
- READ Cycle Timing Requirements (MT28321P20)
- READ Cycle Timing Requirements (MT28321P18)
- WRITE Cycle Timing Requirements
- ERASE and PROGRAM Timing Requirements
- Timing Diagrams
- Single Asynchronous READ Operation
- Asynchronous Page Mode READ Operation
- Two-Cycle PROGRAMMING/ERASE Operation
- Reset Operation
- Table 11, CFI
- Table 11, CFI (continued)
- Table 11, CFI (continued)
- 48-Ball FBGA
1
2 Meg x 16 Page Flash Memory
2002, Micron Technology, Inc.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S
PRODUCTION DATA SHEET SPECIFICATIONS.
FLASH MEMORY
MT28F321P20
MT28F321P18
Low Voltage, Extended Temperature
0.18m Process Technology
BALL ASSIGNMENT
48-Ball FBGA
FEATURES
Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice versa
Basic configuration:
Seventy-one erasable blocks
Bank a (4Mb for data storage)
Bank b (28Mb for program storage)
V
CC
, V
CC
Q, V
PP
voltages*
1.70V (MIN), 1.90V (MAX) V
CC
, V
CC
Q
(MT28F321P18)
1.80V (MIN), 2.20V (MAX) V
CC
, V
CC
Q
(MT28F321P20)
0.9V (MIN) V
PP
(in-system PROGRAM/ERASE)
12V 5% (HV) V
PP
tolerant (factory
programming compatibility)
Random access time: 70ns and 80ns @ 1.80V V
CC
*
Page Mode read access*
Eight-word page
Interpage read access: 70ns/80ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
Low power consumption (V
CC
= 2.20V)
Asynchronous READ < 15mA
Standby < 50A
Automatic power save (APS) feature
Enhanced write and erase suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
Dual 64-bit chip protection registers for security
purposes
Cross-compatible command support
Extended command set
Common flash interface
PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
* Data based on MT28F321P20 device.
NOTE: See page 7 for Ball Description Table.
See page 33 for mechanical drawing.
A
B
C
D
E
F
1 2 3 4 5 6 7 8
Top View
(Ball Down)
A13
A14
A15
A16
V
CC
Q
V
SS
A19
A17
A6
DQ8
DQ9
DQ10
WP#
A18
A20
DQ2
DQ3
V
CC
A8
WE#
A9
DQ5
DQ6
DQ13
A4
A2
A1
A0
V
SS
OE#
A7
A5
A3
CE#
DQ0
DQ1
A11
A10
A12
DQ14
DQ15
DQ7
V
PP
RST#
NC
DQ11
DQ12
DQ4
OPTIONS
MARKING
Timing
70ns access
-70
80ns access
-80
90ns access
-90
Boot Block Configuration
Top
T
Bottom
B
Package
48-ball FBGA (6 x 8 ball grid)
FG
Operating Temperature Range
Extended (-40C to +85C)
ET
Part Number Example:
MT28F321P20FG-70 TET
2
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
GENERAL DESCRIPTION
The MT28F321P20 and MT28F321P18 are high-
performance, high-density, nonvolatile memory
solutions that can significantly improve system perfor-
mance. This new architecture features a two-memory-
bank configuration that supports background
operation with no latency.
A high-performance bus interface allows a fast page
mode, data transfer; a conventional asynchronous bus
interface is provided as well.
The devices allow soft protection for blocks, as read
only, by configuring soft protection registers with dedi-
cated command sequences. For security purposes, two
64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to moni-
tor the WSM status and to determine the progress of
the program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The device is manufactured using 0.18m process
technology.
Please refer to Micron's Web site (
www.micron.com/
flash
) for the latest data sheet.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ
and WRITE operations.
The Flash memory devices are available in the fol-
lowing bank segmentation configuration:
Bank a comprises one-eighth of the memory
and contains 8 x 4K-word parameter blocks;
the remainder of bank a is split into 7 x 32K-
word blocks.
Bank b represents seven-eighths of the
memory, is equally sectored, and contains 48
x 32K-word blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron's standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PRODUCT
SAMPLE
MECHANICAL
PART NUMBER
MARKING
MARKING
SAMPLE MARKING
MT28F321P20FG-70 BET
FW818
FX818
FY818
MT28F321P20FG-70 TET
FW819
FX819
FY819
MT28F321P20FG-80 BET
FW810
FX810
FY810
MT28F321P20FG-80 TET
FW811
FX811
FY811
MT28F321P18FG-90 BET
FW820
FX820
FY820
MT28F321P18FG-90 TET
FW821
FX821
FY821
3
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
PART NUMBERING INFORMATION
Micron's low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Table 2
Valid Part Number Combinations
BOOT BLOCK
OPERATING
ACCESS
STARTING
TEMPERATURE
PART NUMBER
TIME (ns)
ADDRESS
RANGE
MT28F321P20FG-70 BET
70
Bottom
-40
o
C to +85
o
C
MT28F321P20FG-70 TET
70
Top
-40
o
C to +85
o
C
MT28F321P20FG-80 BET
80
Bottom
-40
o
C to +85
o
C
MT28F321P20FG-80 TET
80
Top
-40
o
C to +85
o
C
MT28F321P18FG-90 BET
90
Bottom
-40
o
C to +85
o
C
MT28F321P18FG-90 TET
90
Top
-40
o
C to +85
o
C
MT 28F 321 P20FG-70 T ET
Micron Technology
Flash Family
28F = Dual-Supply Flash
Density/Organization/Banks
321 = 32Mb (2,048K x 16)
bank a = 1/8; bank b = 7/8
Access Time
-70 = 70ns
-80 = 80ns
-90 = 90ns
Read Mode Operation
P = Asynchronous/Page Read
Package Code
FG = 48-ball FBGA (6 x 8 grid)
Operating Temperature Range
ET = Extended (-40C to +85C)
Boot Block Starting Address
B = Bottom boot
T = Top boot
Operating Voltage Range
18 = 1.70V1.90V
20 = 1.80V2.20V
Figure 1
Part Number Chart
Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.
4
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
X DEC
Y/Z DEC
Data Input
Buffer
Output
Multiplexer
Address
CNT WSM
Output
Buffer
Status
Reg.
WSM
Program/
Erase
Pump Voltage
Generators
Address Latch
DQ0DQ15
DQ0DQ15
CSM
RST#
CE#
X DEC
Y/Z DEC
WE#
OE#
I/O Logic
A0A20
Address
Multiplexer
Bank 2 Blocks
Y/Z Gating/Sensing
Data
Register
Bank 1 Blocks
Y/Z Gating/Sensing
ID Reg.
RCR
Block Lock
Device ID
Manufacturer's ID
OTP
Query
PR Lock
Query/OTP
PR Lock
5
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
Figure 2
Bottom Boot Block Device
Bank b = 28Mb
Block
Block Size
Address Range
(K-bytes/K-words)
(x16)
70
64/32
1F8000h-1FFFFFh
69
64/32
1F0000h-1F7FFFh
68
64/32
1E8000h-1EFFFFh
67
64/32
1E0000h-1E7FFFh
66
64/32
1D8000h-1DFFFFh
65
64/32
1D0000h-1D7FFFh
64
64/32
1C8000h-1CFFFFh
63
64/32
1C0000h-1C7FFFh
62
64/32
1B8000h-1BFFFFh
61
64/32
1B0000h-1B7FFFh
60
64/32
1A8000h-1AFFFFh
59
64/32
1A0000h-1A7FFFh
58
64/32
198000h-19FFFFh
57
64/32
190000h-197FFFh
56
64/32
188000h-18FFFFh
55
64/32
180000h-187FFFh
54
64/32
178000h-17FFFFh
53
64/32
170000h-177FFFh
52
64/32
168000h-16FFFFh
51
64/32
160000h-167FFFh
50
64/32
158000h-15FFFFh
49
64/32
150000h-157FFFh
48
64/32
148000h-14FFFFh
47
64/32
140000h-147FFFh
46
64/32
138000h-13FFFFh
45
64/32
130000h-137FFFh
44
64/32
128000h-12FFFFh
43
64/32
120000h-127FFFh
42
64/32
118000h-11FFFFh
41
64/32
110000h-117FFFh
40
64/32
108000h-10FFFFh
39
64/32
100000h-107FFFh
38
64/32
0F8000h-0FFFFFh
37
64/32
0F0000h-0F7FFFh
36
64/32
0E8000h-0EFFFFh
35
64/32
0E0000h-0E7FFFh
34
64/32
0D8000h-0DFFFFh
33
64/32
0D0000h-0D7FFFh
32
64/32
0C8000h-0CFFFFh
31
64/32
0C0000h-0C7FFFh
30
64/32
0B8000h-0BFFFFh
29
64/32
0B0000h-0B7FFFh
28
64/32
0A8000h-0AFFFFh
27
64/32
0A0000h-0A7FFFh
26
64/32
098000h-097FFFh
25
64/32
090000h-097FFFh
24
64/32
088000h-087FFFh
23
64/32
080000h-087FFFh
22
64/32
078000h-07FFFFh
21
64/32
070000h-077FFFh
20
64/32
068000h-067FFFh
19
64/32
060000h-067FFFh
18
64/32
058000h-05FFFFh
17
64/32
050000h-057FFFh
16
64/32
048000h-04FFFFh
15
64/32
040000h-047FFFh
Bank a = 4Mb
Block
Block Size
Address Range
(K-bytes/K-words)
(x16)
14
64/32
038000h-03FFFFh
13
64/32
030000h-037FFFh
12
64/32
028000h-02FFFFh
11
64/32
020000h-027FFFh
10
64/32
018000h-01FFFFh
9
64/32
010000h-017FFFh
8
64/32
008000h-00FFFFh
7
8/4
007000h-007FFFh
6
8/4
006000h-006FFFh
5
8/4
005000h-005FFFh
4
8/4
004000h-004FFFh
3
8/4
003000h-003FFFh
2
8/4
002000h-002FFFh
1
8/4
001000h-001FFFh
0
8/4
000000h-000FFFh
6
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
Figure 3
Top Boot Block Device
Bank b = 28Mb
Block
Block Size
Address Range
(K-bytes/K-words)
(x16)
55
64/32
1B8000h-1BFFFFh
54
64/32
1B0000h-1B7FFFh
53
64/32
1A8000h-1AFFFFh
52
64/32
1A0000h-1A7FFFh
51
64/32
198000h-19FFFFh
50
64/32
190000h-197FFFh
49
64/32
188000h-18FFFFh
48
64/32
180000h-187FFFh
47
64/32
178000h-17FFFFh
46
64/32
170000h-177FFFh
45
64/32
168000h-16FFFFh
44
64/32
160000h-167FFFh
43
64/32
158000h-15FFFFh
42
64/32
150000h-157FFFh
41
64/32
148000h-14FFFFh
40
64/32
140000h-147FFFh
39
64/32
138000h-13FFFFh
38
64/32
130000h-137FFFh
37
64/32
128000h-12FFFFh
36
64/32
120000h-127FFFh
35
64/32
118000h-11FFFFh
34
64/32
110000h-117FFFh
33
64/32
108000h-10FFFFh
32
64/32
100000h-107FFFh
31
64/32
0F8000h-0FFFFFh
30
64/32
0F0000h-0F7FFFh
29
64/32
0E8000h-0EFFFFh
28
64/32
0E0000h-0E7FFFh
27
64/32
0D8000h-0DFFFFh
26
64/32
0D0000h-0D7FFFh
25
64/32
0C8000h-0CFFFFh
24
64/32
0C0000h-0C7FFFh
23
64/32
0B8000h-0BFFFFh
22
64/32
0B0000h-0B7FFFh
21
64/32
0A8000h-0AFFFFh
20
64/32
0A0000h-0A7FFFh
19
64/32
098000h-09FFFFh
18
64/32
090000h-097FFFh
17
64/32
088000h-08FFFFh
16
64/32
080000h-087FFFh
15
64/32
078000h-07FFFFh
14
64/32
070000h-077FFFh
13
64/32
068000h-06FFFFh
12
64/32
060000h-067FFFh
11
64/32
058000h-05FFFFh
10
64/32
050000h-057FFFh
9
64/32
048000h-04FFFFh
8
64/32
040000h-047FFFh
7
64/32
038000h-03FFFFh
6
64/32
030000h-037FFFh
5
64/32
028000h-02FFFFh
4
64/32
020000h-027FFFh
3
64/32
018000h-01FFFFh
2
64/32
010000h-017FFFh
1
64/32
008000h-00FFFFh
0
64/32
000000h-007FFFh
Bank a = 4Mb
Block
Block Size
Address Range
(K-bytes/K-words)
(x16)
70
8/4
1FF000h-1FFFFFh
69
8/4
1FE000h-1FEFFFh
68
8/4
1FD000h-1FDFFFh
67
8/4
1FC000h-1FCFFFh
66
8/4
1FB000h-1FBFFFh
65
8/4
1FA000h-1FAFFFh
64
8/4
1F9000h-1F9FFFh
63
8/4
1F8000h-1F8FFFh
62
64/32
1F0000h-1F7FFFh
61
64/32
1E8000h-1EFFFFh
60
64/32
1E0000h-1E7FFFh
59
64/32
1D8000h-1DFFFFh
58
64/32
1D0000h-1D7FFFh
57
64/32
1C8000h-1CFFFFh
56
64/32
1C0000h-1C7FFFh
7
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
BALL DESCRIPTIONS
48-BALL FBGA
NUMBERS
SYMBOL
TYPE
DESCRIPTION
D8, C8, B8, C7,
A0A20
Input
Address Inputs: Inputs for the address during READ and WRITE
A8, B7, C6, A7,
operations. Addresses are internally latched during READ and WRITE
A3, C3, B2, A2,
cycles.
C2, A1, B1, C1,
D1, B6, B5, A6,
C5
D7
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
F8
OE#
Input
Output Enable: Enables the output buffer when LOW. When OE# is
HIGH, the output buffers are disabled.
B3
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command state machine
(CSM) or to the memory array.
B4
RST#
Input
Reset: When RST# is a logic LOW, the device is in reset mode, which
drives the outputs to High-Z and resets the write state machine
(WSM). When RST# is at logic HIGH, the device is in standard
operation. When RST# transitions from logic LOW to logic HIGH, the
device resets all blocks to locked and defaults to the read array
mode.
A5
WP#
Input
Write Protect: Controls the lock down function of the flexible locking
feature.
A4
V
PP
Input
Program/Erase Enable: [0.9V2.2V or 11.4V12.6V] Operates as input
at logic levels to control complete device protection. Provides factory
programming compatibility when driven to 11.4V12.6V.
E7, F7, D5, B5,
DQ0DQ15
Input/
Data Inputs/Outputs: Input array data on the second CE# and WE#
F4, D3, E3, F2,
Output
cycle during PROGRAM command. Input commands to the
D6, 36, F6, D4,
command user interface when CE# and WE# are active. DQ0DQ15
E4, F3, D2, E2
output data when CE# and OE# are active.
E8, F1
V
SS
Supply
Do not float any ground ball.
F5
V
CC
Supply
Device Power Supply: [1.70V1.90V (MT28F321P18) or 1.80V2.20V
(MT28F321P20)] Supplies power for device operation.
E1
V
CC
Q
Supply
I/O Power Supply: [1.70V1.90V (MT28F321P18) or 1.80V2.20V
(MT28F321P20)] Supplies power for input/output buffers.
C4
NC
Internally not connected.
8
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
COMMAND STATE MACHINE (CSM)
Commands are issued to the command state ma-
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal WSM. The available
commands are listed in Table 3, their definitions are
given in Table 4, and their descriptions in Table 5.
Program and erase algorithms are automated by an
on-chip WSM. For more specific information about the
CSM transition states, see Micron technical note
TN-28-33, "Command State Machine Description and
Command Definition."
Once a valid PROGRAM/ERASE command is en-
tered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally and accomplish the requested
operation. A command is valid only if the exact se-
quence of WRITEs is completed. After the WSM com-
pletes its task, the WSM status bit (SR7) (see Table 7) is
set to a logic HIGH level (1), allowing the CSM to re-
spond to the full command set again.
OPERATIONS
Device operations are selected by entering a stan-
dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals CE# and
WE# must be at a logic LOW level (V
IL
), and OE# and
RST# must be at logic HIGH (V
IH
). The second opera-
tion, when needed, can be a WRITE or a READ depend-
ing upon the command. During a READ operation,
control signals CE# and OE# must be at a logic LOW
level (V
IL
), and WE# and RST# must be at logic HIGH
(V
IH
).
Table 6 shows the bus operations for all the modes:
write, read, reset, standby, and output disable.
When the device is powered up, internal reset cir-
cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two memory partitions, an on-chip status regis-
ter is available. These two registers allow the progress
of the various operations that can take place on a
memory bank to be monitored. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and reading the register data on I/Os DQ0DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0DQ7 (see Table 7).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE#, and reading the resulting
status code on I/Os DQ0DQ7. The high-order I/Os
(DQ8DQ15) are set to 00h internally, so only the low-
Table 3
Command State Machine Codes For Device Mode Selection
COMMAND DQ0DQ7
CODE ON DEVICE MODE
40h/10h
Program setup/alternate program setup
20h
Block erase setup
50h
Clear status register
60h
Protection configuration setup
70h
Read status register
90h
Read protection configuration register
98h
Read query
B0h
Program/erase suspend
C0h
Protection register program/lock
D0h
Program/erase resume erase confirm
FFh
Read array
9
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PRELIMINARY
order I/Os (DQ0DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.
Register data is updated and latched on the falling
edge of OE# or CE#, whichever occurs last. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 7 defines the sta-
tus register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
CSM OPERATIONS
The CSM decodes instructions for read array, read
protection configuration register, read query, read sta-
tus register, clear status register, program, erase, erase
suspend, erase resume, program suspend, program
resume, lock block, unlock block, and lock down block,
chip protection program, and set read configuration
register. The 8-bit command code is input to the device
on DQ0DQ7 (see Table 3 for CSM codes and Table 4
for command definitions). During a PROGRAM or
ERASE cycle, the CSM informs the WSM that a PRO-
GRAM or ERASE cycle has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSM status bit (SR7) is set to a
logic HIGH level and the CSM responds to the full com-
Table 4
Command Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
OPERATION ADDRESS
1
DATA
OPERATION ADDRESS
1
DATA
1
READ ARRAY
WRITE
WA
FFh
READ PROTECTION CONFIGURATION REGISTER
WRITE
IA
90h
READ
IA
ID
READ STATUS REGISTER
WRITE
BA
70h
READ
X
SRD
CLEAR STATUS REGISTER
WRITE
BA
50h
READ QUERY
WRITE
Q A
98h
READ
Q A
Q D
BLOCK ERASE SETUP
WRITE
BA
20h
WRITE
BA
D0h
PROGRAM SETUP/ALTERNATE PROGRAM SETUP
WRITE
WA
40h/10h
WRITE
WA
WD
PROGRAM/ERASE SUSPEND
WRITE
BA
B0h
PROGRAM/ERASE RESUME - ERASE CONFIRM
WRITE
BA
D0h
LOCK BLOCK
WRITE
BA
60h
WRITE
BA
01h
UNLOCK BLOCK
WRITE
BA
60h
WRITE
BA
D0h
LOCK DOWN BLOCK
WRITE
BA
60h
WRITE
BA
2Fh
PROTECTION REGISTER PROGRAM
WRITE
PA
C0h
WRITE
PA
PD
PROTECTION REGISTER LOCK
WRITE
LPA
C0h
WRITE
LPA
FFFDh
NOTE: 1. BA: Address within the block
IA:
Identification code address
ID:
Identification code data
LPA: Lock protection register address
PA: Protection register address
PD: Data to be written at the location PA
QA: Query code address
QD: Query code data
SRD: Data read from the status register
WA: Word address of memory location to be written, or read
WD: Data to be written at the location WA
X:
"Don't Care"
10
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PRELIMINARY
(continued on the next page)
Table 5
Command Descriptions
CODE DEVICE MODE
BUS CYCLE
DESCRIPTION
10h
Alt. Program Setup
First
Operates the same as a PROGRAM SETUP command.
20h
Erase Setup
First
Prepares the CSM for an ERASE CONFIRM command. If the next
command is not an ERASE CONFIRM command, the command will
be ignored, and the bank will go to read status mode and wait for
another command.
40h
Program Setup
First
A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. The Flash
device outputs status register data on the falling edge of OE# or CE#,
whichever occurs first.
50h
Clear Status
First
The WSM can set the block lock status (SR3), program status (SR4),
Register
and erase status (SR5) bits in the status register to "1," but it cannot
clear them to "0." Issuing this command clears those bits to "0."
60h
Protection
First
Prepares the CSM for changes to the block locking status. If the next
Configuration
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
Setup
DOWN, the command will be ignored, and the device will go to read
status mode.
70h
Read Status
First
Places the device into read status register mode. Reading the device
Register
will output the contents of the status register for the addressed bank.
The device will automatically enter this mode for the addressed bank
after a PROGRAM or ERASE operation has been initiated.
90h
Read Protection
First
Puts the device into the read protection configuration mode so that
Configuration
reading the device will output the manufacturer/device codes or
block lock status.
98h
Read Query
First
Puts the device into the read query mode so that reading the device
will output common flash interface information.
B0h
Program/Erase
First
Suspends the currently executing PROGRAM/ERASE operation. The
Suspend
status register will indicate when the operation has been successfully
suspended by setting either the program suspend (SR2) or erase
suspend (SR6), and the WSM status bit (SR7) to a "1" (ready). The
WSM will continue to idle in the suspend state, regardless of the state
of all input control signals except RST#, which will immediately shut
down the WSM and the remainder of the chip if RST# is driven to V
IL
.
C0h
Program Device
First
Writes a specific code into the device protection register.
Protection Register
Lock Device
First
Locks the device protection register; data can no longer be changed.
Protection Register
11
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Table 5
Command Descriptions (continued)
CODE DEVICE MODE
BUS CYCLE
DESCRIPTION
D0h
Erase Confirm
Second
If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address balls. During programming/erase,
the device will respond only to the READ STATUS REGISTER,
PROGRAM SUSPEND, or ERASE SUSPEND commands and will output
status register data on the falling edge of OE# or CE#, whichever
occurs last.
Program/Erase
First
If a PROGRAM or ERASE operation was previously suspended, this
Resume
command will resume the operation.
FFh
Read Array
First
During the array mode, array data will be output on the data bus.
01h
Lock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock the block indicated on the
address bus.
2Fh
Lock Down
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock down the block indicated on
the address bus.
D0h
Unlock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and unlock the block indicated on the
address bus. If the block had been previously set to lock down, this
operation will have no effect.
00h
Invalid /Reserved
Unassigned command that should not be used.
mand set. The CSM stays in the current command state
until the microprocessor issues another command.
The WSM successfully initiates an ERASE or PRO-
GRAM operation only when V
PP
is within its correct volt-
age range.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the V
PP
status bit (SR3), the pro-
gram status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER com-
mand (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal op-
erations. When the status bits are cleared, the device
returns to the read array mode.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0DQ7. Control signals CE# and OE# must
be at a logic LOW level (V
IL
), and WE# and RST# must be
at logic HIGH level (V
IH
) to read data from the array.
Data is available on DQ0DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial power-
up or device reset, the device defaults to the read array
mode.
READ PROTECTION CONFIGURATION DATA
The chip identification mode outputs three types
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip iden-
tification data is read by entering the command code
90h on DQ0DQ7 to the bank containing address 00h
and the identification code address on the address
lines. Control signals CE# and OE# must be at a logic
LOW level (V
IL
), and WE# and RST# must be at a logic
HIGH level (V
IH
) to read data from the protection con-
figuration register. Data is available on DQ0DQ15.
After data is read from the protection configuration
register, the READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands. See Table 9 for further details.
12
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Taking RST# to V
IL
during programming aborts the
PROGRAM operation. During programming, V
PP
must
remain in the appropriate V
PP
voltage range as shown
in the recommended operating conditions table.
ERASE OPERATIONS
An ERASE operation must be used to initialize all
bits in an array block to "1s." After BLOCK ERASE con-
firm is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.
Block erasure inside the memory array sets all bits
within the address block to logic 1s. Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid ad-
dress within that block. Block erasure is initiated by a
command sequence to the CSM: BLOCK ERASE setup
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Figure 6). A two-command erase sequence protects
against accidental erasure of memory contents.
When the BLOCK ERASE CONFIRM command is
complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. The ERASE operation may be monitored
through the status register (see the Status Register
section).
During the execution of an ERASE operation the
ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows
the CSM to respond only to the READ ARRAY, READ
STATUS REGISTER, READ QUERY, READ CHIP PRO-
TECTION CONFIGURATION, PROGRAM SETUP, PRO-
GRAM RESUME, ERASE RESUME and LOCK SETUP
(see the Block Locking section). During the ERASE SUS-
PEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 7). It is also possible to sus-
pend an ERASE in any bank and initiate a WRITE to
another block in the same bank. After the completion
of a WRITE, an ERASE can be resumed by writing an
ERASE RESUME command.
READ QUERY
The read query mode outputs common flash inter-
face (CFI) data when the device is read (see Table 11).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0DQ7 to the bank contain-
ing address 0h. Control signals CE# and OE# must be at
a logic LOW level (V
IL
), and WE# and RST# must be at a
logic HIGH level (V
IH
) to read data from the query. The
CFI data structure contains information such as block
size, density, command set, and electrical specifica-
tions. To return to read array mode, write the read array
command code FFh on DQ0DQ7.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0DQ7. Two bus cycles are required for
this operation: one to enter the command code and the
block address and a second to read the status register.
In a READ cycle, the address is latched and register
data is updated on the falling edge of OE# or CE#,
whichever occurs last. Register data is updated and
latched on the falling edge of OE# or CE#, whichever
occurs last.
PROGRAMMING OPERATIONS
There are two CSM commands for programming:
PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 3).
After the desired command code is entered (10h or
40h command code on DQ0DQ7), the WSM takes over
and correctly sequences the device to complete the
PROGRAM operation. The WRITE operation may be
monitored through the status register (see the Status
Register section). During this time, the CSM will only
respond to a PROGRAM SUSPEND command until the
PROGRAM operation has been completed, after which
time all commands to the CSM become valid again.
The PROGRAM operation can be suspended by issuing
a PROGRAM SUSPEND command (B0h). Once the WSM
reaches the suspend state, it allows the CSM to re-
spond only to READ ARRAY, READ STATUS REGISTER,
READ PROTECTION CONFIGURATION, READ QUERY,
PROGRAM SETUP, or PROGRAM RESUME. During the
PROGRAM SUSPEND operation, array data should be
read from an address other than the one being pro-
grammed. To resume the PROGRAM operation, a PRO-
GRAM RESUME command (D0h) must be issued to
cause the CSM to clear the suspend state previously
set (see Figure 4 for programming operation and Figure
5 for program suspend and program resume).
13
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Table 7
Status Register Bit Definition
WSMS
ESS
ES
PS
V
PP
S
PSS
BLS
R
7
6
5
4
3
2
1
0
STATUS
BIT #
STATUS REGISTER BIT
DESCRIPTION
SR7
WRITE STATE MACHINE STATUS (WSMS)
Check write state machine bit first to determine word
1 = Ready
program or block erase completion, before checking
0 = Busy
program or erase status bits.
SR6
ERASE SUSPEND STATUS (ESS)
When ERASE SUSPEND is issued, WSM halts execution and
1 = BLOCK ERASE Suspended
sets both WSMS and ESS bits to "1." ESS bit remains set to
0 = BLOCK ERASE in
"1" until an ERASE RESUME command is issued.
Progress/Completed
SR5
ERASE STATUS (ES)
When this bit is set to "1," WSM has applied the maximum
1 = Error in Block Erasure
number of erase pulses to the block and is still unable to
0 = Successful BLOCK ERASE
verify successful block erasure.
SR4
PROGRAM STATUS (PS)
When this bit is set to "1," WSM has attempted but failed
1 = Error in PROGRAM
to program a word.
0 = Successful PROGRAM
SR3
V
PP
STATUS (V
PP
S)
The V
PP
status bit does not provide continuous indication
1 = V
PP
Low Detect, Operation Abort
of the V
PP
level. The WSM interrogates the V
PP
level only
0 = V
PP
= OK
after the program or erase command sequences have been
entered and informs the system if V
PP
< 0.9V. The V
PP
level
is also checked before the PROGRAM/ERASE operation is
verified by the WSM.
SR2
PROGRAM SUSPEND STATUS (PSS)
When PROGRAM SUSPEND is issued, WSM halts execution
1 = PROGRAM Suspended
and sets both WSMS and PSS bits to "1." PSS bit remains
0 = PROGRAM in Progress/Completed
set to "1" until a PROGRAM RESUME command is issued.
SR1
BLOCK LOCK STATUS (BLS)
If a PROGRAM or ERASE operation is attempted to one of
1 = PROGRAM/ERASE Attempted on a
the locked blocks, this is set by the WSM. The operation
Locked Block; Operation Aborted
specified is aborted and the device is returned to read
0 = No Operation to Locked Blocks
status mode.
SR0
RESERVED FOR FUTURE
This bit is reserved for future use.
ENHANCEMENT
Table 6
Bus Operations
MODE
RST#
CE#
OE#
WE#
ADDRESS DQ0DQ15
Read (array, status registers,
V
IH
V
IL
V
IL
V
IH
X
D
OUT
device identification register, or
query)
Standby
V
IH
V
IH
X
X
X
High-Z
Output Disable
V
IH
V
IH
X
X
X
High-Z
Reset
V
IL
X
X
X
X
High-Z
Write
V
IH
V
IL
V
IH
V
IL
X
D
IN
14
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Figure 4
Automated Word Programming
Flowchart
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation
attempts.
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
Data =
40h or 10h
PROGRAM
Addr =
Address of word to be
SETUP
programmed
WRITE
WRITE
Data =
Word to be
DATA
programmed
Addr =
Address of word to be
programmed
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby
Check SR1
1 = Detect locked block
Standby
Check SR3
2
1 = Detect V
PP
LOW
Standby
Check SR4
3
1 = Word program error
YES
NO
Full Status Register
Check (optional)
NO
YES
PROGRAM
SUSPEND?
SR7 = 1?
Issue PROGRAM SETUP
Command and
Word Address
Start
Word Program Passed
V
PP
Range Error
Word Program Failed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
Issue Word Address
and Word Data
PROGRAM
SUSPEND Loop
1
YES
NO
SR1 = 0?
YES
NO
SR3 = 0?
YES
NO
SR4 = 0?
Word Program
Completed
Read Status Register
Bits
PROGRAM Attempted
on a Locked Block
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Issue READ ARRAY
Command
PROGRAM
Complete
Finished
Reading
?
Issue PROGRAM
RESUME Command
YES
YES
NO
NO
SR2 = 1?
Start
PROGRAM Resumed
Read Status Register
Bits
Issue PROGRAM
SUSPEND Command
YES
NO
SR7 = 1?
Figure 5
PROGRAM SUSPEND/
PROGRAM RESUME Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE
PROGRAM
Data = B0h
SUSPEND
READ
Status register data
Toggle OE# or CE# to update
status register.
Standby
Check SR7
1 = Ready
Standby
Check SR2
1 = Suspended
WRITE
READ
Data = FFh
ARRAY
READ
Read data from block other
than that being programmed.
WRITE
PROGRAM
Data = D0h
RESUME
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
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YES
NO
Full Status Register
Check (optional)
NO
YES
ERASE
SUSPEND?
SR 7 = 1?
Start
BLOCK ERASE Passed
V
PP
Range Error
BLOCK ERASE Failed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
ERASE
SUSPEND Loop
1
YES
NO
SR1 = 0?
YES
NO
YES
NO
BLOCK ERASE
Completed
Read Status Register
Bits
ERASE Attempted
on a Locked Block
SR3 = 0?
SR5 = 0?
Issue ERASE SETUP
Command and
Block Address
Issue BLOCK ERASE
CONFIRM Command
and Block Address
Figure 6
BLOCK ERASE Flowchart
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
Data = 20h
ERASE
Block Addr = Address
SETUP
within block to be erased
WRITE
ERASE
Data = D0h
Block Addr = Address
within block to be erased
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby
Check SR1
1 = Detect locked block
Standby
Check SR3
2
1 = Detect V
PP
block
Standby
Check SR5
3
1 = BLOCK ERASE error
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READ
PROGRAM
Issue READ ARRAY
Command
PROGRAM
Loop
ERASE
Complete
READ or
PROGRAM?
YES
NO
Issue ERASE
RESUME Command
READ or
PROGRAM
Complete?
YES
NO
SR6 = 1?
Start
ERASE Continued
Read Status Register
Bits
Issue ERASE
SUSPEND Command
2
(Note 1)
YES
NO
SR7 = 1?
Figure 7
ERASE SUSPEND/ERASE RESUME
Flowchart
NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.
2. See Word Programming Flowchart for complete programming procedure.
BUS
OPERATION COMMAND COMMENTS
WRITE
ERASE
Data = B0h
SUSPEND
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready
Standby
Check SR6
1 = Suspended
WRITE
READ
Data = FFh
ARRAY
READ
Read data from block
other than that being
erased.
WRITE
ERASE
Data = D0h
RESUME
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READ-WHILE-WRITE/ERASE
CONCURRENCY
It is possible for the device to read from one bank
while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PRO-
GRAM/ERASE command is issued in bank a, then bank
a changes to the read status mode and bank b defaults
to the read array mode. The device will read from bank
b if the latched address resides in bank b (see Figure 8).
Similarly, if a PROGRAM/ERASE command is issued in
bank b, then bank b changes to read status mode and
bank a defaults to read array mode. When returning to
bank a, the device will read PROGRAM/ERASE status if
the latched address resides in bank a. A correct bank
address must be specified to read status register after
returning from concurrent read in the other bank.
When reading the CFI or the chip protection regis-
ter, concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protec-
tion register is only allowed when a PROGRAM or ERASE
operation is performed on bank b on the bottom boot
device. For a bottom boot device, reading of the CFI
table or the chip protection register is only allowed if
bank b is in read array mode. For a top boot device,
reading of the CFI table or the chip protection register
is only allowed if bank a is in read array mode.
Figure 8
READ-While-WRITE Concurrency
Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be
suspended, and a WRITE to
another block in bank a
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
1 - Reading bank a
Bank b
1 - Reading from bank b
1 - Erasing/writing to bank b
2 - Erasing in bank b can be
suspended, and a WRITE to
another block in bank b
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
19
2 Meg x 16 Page Flash Memory
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MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
BLOCK LOCKING
The Flash memory devices provide a flexible lock-
ing scheme which allows each block to be individually
locked or unlocked with no latency.
The devices offer two-level protection for the blocks.
The first level allows software-only control of block lock-
ing (for data which needs to be changed frequently),
while the second level requires hardware interaction
before locking can be changed (code which does not
require frequent updates).
Control signals WP#, DQ0, and DQ1 define the state
of a block; for example, state [001] means WP# = 0,
DQ0 = 1 and DQ1 = 0.
Table 8 defines all of the possible locking states.
NOTE: All blocks are software-locked upon power-
up sequence completion.
LOCKED STATE
After a power-up sequence completion, or after a
reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a locked
block will return an error on bit SR1 of the status regis-
ter. The status of a locked block can be changed to
unlocked or lock down using the appropriate software
commands. Writing the lock command sequence, 60h
followed by 01h, can lock an unlocked block.
UNLOCKED STATE
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked down
using the appropriate software command sequence,
60h followed by D0h (see Table 4).
LOCKED DOWN STATE
Blocks that are locked down (state [011]) are pro-
tected from PROGRAM and ERASE operations, but
their protection status cannot be changed using soft-
ware commands alone. A locked or unlocked block can
be locked down by writing the lock down command
sequence, 60h followed by 2Fh. Locked down blocks
revert to the locked state when the device is reset or
powered down.
The LOCK DOWN function is dependent on the
WP# input. When WP# = 0, blocks in lock down [011] are
protected from program, erase, and lock status
changes. When WP# = 1, the lock down function is dis-
abled ([111]), and locked down blocks can be individu-
ally unlocked by a software command to the [110] state,
where they can be erased and programmed. These
blocks can then be relocked [111] and unlocked [110]
as desired while WP# remains HIGH. When WP# goes
LOW, blocks that were previously locked down return
to the locked down state [011] regardless of any changes
made while WP# was HIGH. Device reset or power-
down resets all locks, including those in lock down, to
locked state (see Table 9).
READING A BLOCK'S LOCK STATUS
The lock status of every block can be read in the
read device identification mode. To enter this mode,
write 90h to the the bank containing address 00h. Sub-
sequent READs at block address +00002 will output the
lock status of that block. The lowest two outputs, DQ0
and DQ1, represent the lock status. DQ0 indicates the
block lock/unlock status and is set by the LOCK com-
mand and cleared by the UNLOCK command. It is also
automatically set when entering lock down. DQ1 indi-
cates lock down status and is set by the LOCK DOWN
Table 8
Block Locking State Transition
ERASE/PROGRAM
LOCK
WP#
DQ1
DQ0
NAME
ALLOWED
LOCK
UNLOCK
DOWN
0
0
0
Unlocked
Yes
To [001]
No Change
To [011]
0
0
1
Locked (Default)
No
No Change
To [000]
To [011]
0
1
1
Lock Down
No
No Change
No Change
No Change
1
0
0
Unlocked
Yes
To [101]
No Change
To [111]
1
0
1
Locked
No
No Change
To [100]
To [111]
1
1
0
Lock Down
Yes
To [111]
No Change
To [111]
Disabled
1
1
1
Lock Down
No
No Change
To [110]
No Change
Disabled
20
2 Meg x 16 Page Flash Memory
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MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
command. It can only be cleared by reset or power-
down, not by software. Table 8 shows the locking state
transition scheme. The READ ARRAY command, FFh,
must be issued to the bank containing address 00h
prior to issuing other commands.
LOCKING OPERATIONS DURING ERASE
SUSPEND
Changes to block lock status can be performed dur-
ing an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down. This
is useful in the case when another block needs to be
updated while an ERASE operation is in progress.
To change block locking during an ERASE opera-
tion, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any de-
sired LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME com-
mand (D0h).
If a block is locked or locked down during an ERASE
SUSPEND on the same block, the locking status bits
will be changed immediately. When the ERASE is re-
sumed, the ERASE operation will complete.
A locking operation cannot be performed during a
PROGRAM SUSPEND.
CHIP PROTECTION REGISTER
A 128-bit chip protection register can be used to
fulfill the security considerations in the system (pre-
venting the device substitution).
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit unchange-
able number. The other segment is left blank for cus-
tomers to program as desired. (See Figure 9).
Figure 9
Protection Register Memory Map
4 Words
Factory-Programmed
4 Words
User-Programmed
PR Lock
0
88h
85h
84h
81h
80h
ITEM
ADDRESS
2
DATA
Manufacturer Code (x16)
00000h
002Ch
Device Code
00001h
Top boot configuration
44B2h
Bottom boot configuration
44B3h
Block Lock Configuration
XX002h
Lock
Block is unlocked
DQ0 = 0
Block is locked
DQ0 = 1
Block is locked down
DQ1 = 1
Chip Protection Register Lock
80h
PR Lock
Chip Protection Register 1
81h84h
Factory Data
Chip Protection Register 2
85h88h
User Data
NOTE: 1. Other locations within the configuration address space are reserved by
Micron for future use.
2. "XX" specifies the block address of lock configuration.
Table 9
Chip Configuration Addressing
1
21
2 Meg x 16 Page Flash Memory
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MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
READING THE CHIP PROTECTION REGISTER
The chip protection register is read in the device
identification mode. To enter this mode, load the 90h
command to the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
9 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh). The READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands.
PROGRAMMING THE CHIP PROTECTION
REGISTER
The first 64 bits (PR1) of the protection register (ad-
dresses 81h84h) are programmed with a unique iden-
tifier at the factory. DQ0 of the PR lock register (address
80h) is programmed to a "0" state, locking the first 64
bits and preventing any further programming. The
second 64 bits (PR2) is a user area (addresses 85h
88h), where the user can program any information into
this area as long as DQ1 of the PR lock register remains
unprogrammed. After DQ1 of the PR lock register is
programmed, no further programming is allowed on
PR2. The programming sequence is similar to array
programming except that the PROTECTION REGIS-
TER PROGRAMMING SETUP command (C0h) is issued
instead of an ARRAY PROGRAMMING SETUP com-
mand (40h), followed by the data to be programmed at
addresses 85h88h.
To program the PR lock bit for PR2 (to prevent fur-
ther programming), use the above sequence on ad-
dress 80h, with data of FFFDh (DQ1 = 0).
ASYNCHRONOUS READ CYCLE
When accessing addresses in a random order or
when switching between pages, the access time is given
by
t
AA.
When CE# and OE# are LOW, the data is placed on
the data bus and the processor can read the data.
PAGE READ MODE
The initial portion of the page mode cycle is the
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0A2 allows random ac-
cess of other words in the page. The page word size is
eight words.
V
PP
/ V
CC
PROGRAM AND ERASE
VOLTAGES
The MT28F321P20 Flash memory provides in-
system programming and erase with V
PP
in the
0.9V2.2V range. The 12V V
PP
mode programming is
offered for compatibility with existing programming
equipment and does not enhance program/erase
performance.
The device can withstand 100,000 WRITE/ERASE
operations when V
PP
= V
PP
1
or 100 WRITE/ERASE opera-
tions and 10 cumulative hours when V
PP
= V
PP
2
.
In addition to the flexible block locking, the V
PP
programming voltage can be held low for absolute hard-
ware write protection of all blocks in the Flash device.
When V
PP
is below V
PPLK
, any PROGRAM or ERASE
operation will result in an error, prompting the corre-
sponding status register bit (SR3) to be set.
During WRITE and ERASE operations, the WSM
monitors the V
PP
voltage level. WRITE/ERASE opera-
tions are allowed only when V
PP
is within the ranges
specified in Table 10.
When V
CC
is below V
LKO
, any WRITE/ERASE opera-
tion will be disabled.
Table 10
V
PP
Range (V)
MIN
MAX
In-System
0.9
2.2
In-Factory
11.4
12.6
22
2 Meg x 16 Page Flash Memory
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MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
STANDBY MODE
Icc supply current is reduced by applying a logic
HIGH level on CE# and RST# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on CE# and
RST# reduces the current to I
CC
3
(MAX). If the device is
deselected during an ERASE operation or during pro-
gramming, the device continues to draw current until
the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during peri-
ods when the array is not being read and the device is in
the active mode. During this time the device switches
to the automatic power save mode. When the device
switches to this mode, I
CC
is reduced to a level compa-
rable to I
CC
3
. Further power savings can be realized by
applying a logic HIGH level on CE# to place the device
in standby mode. The low level of power is maintained
until another operation is initiated. In this mode, the I/
Os retain the data from the last memory address read
until a new address is read. This mode is entered auto-
matically if no address or control signals toggle.
DEVICE RESET
To correctly reset the Flash memory devices, the
RST# signal must be asserted (RST# = V
IL
) for a mini-
mum of
t
RP. After reset, the devices can be accessed for
a READ operation with a delayed access time of
t
RWH
from the rising edge of RST#. The circuitry used for
generating the RST# signal needs to be common with
the rest of the system reset to ensure that correct sys-
tem initialization occurs. Please refer to the timing dia-
gram for further details.
POWER-UP SEQUENCE
The following power-up sequence is recommended
to properly initialize internal chip operations:
At power-up, RST# should be kept at V
IL
for 2s
after V
CC
reaches V
CC
(MIN).
V
CC
Q should not come up before V
CC
.
V
PP
should be kept at V
IL
to maximize data
integrity.
When the power-up sequence is completed, RST#
should be brought to V
IH
. To ensure a proper power-up,
the rise time of RST# (10%90%) should be <10s.
23
2 Meg x 16 Page Flash Memory
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MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Ball Except V
CC
and V
PP
with Respect to V
SS
....................... -0.5V to +2.45V
V
PP
Voltage (for BLOCK ERASE and PROGRAM
with Respect to V
SS
) ................. -0.5V to +13.5V**
V
CC
and V
CC
Q Supply Voltage
with Respect to V
SS
....................... -0.3V to +2.45V
Output Short Circuit Current ............................... 100mA
Operating Temperature Range ............ -40
o
C to +85
o
C
Storage Temperature Range ............... -55
o
C to +125
o
C
Soldering Cycle .......................................... 260
o
C for 10s
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum DC voltage on V
PP
may overshoot to +13.5V
for periods <20ns.
OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTE
Operating temperature
t
A
-40
+85
o
C
V
CC
supply voltage (MT28F321P18)
V
CC
1.70
1.90
V
V
CC
supply voltage (MT28F321P20)
V
CC
1.80
2.20
V
I/O supply voltage (MT28F321P18)
V
CC
Q
1.70
1.90
V
I/O supply voltage (MT28F321P20)
V
CC
Q
1.80
2.20
V
V
PP
voltage
V
PP
1
0.9
2.2
V
V
PP
in-factory programming voltage
V
PP
2
11.4
12.6
V
Block erase cycling
V
PP
=
V
PP
1
V
PP
1
100,000
Cycles
V
PP
=
V
PP
2
V
PP
2
100
Cycles
1
NOTE: 1. V
PP
= V
PP
2
is a maximum of 10 cumulative hours.
Figure 11
Output Load Circuit
I/O
14.5K
30pF
V
CC
V
SS
14.5K
Output
Test Points
Input
V
CC
V
SS
AC test inputs are driven at V
CC
for a logic 1 and V
SS
for a logic 0. Input timing begins at V
CC
/2,
and output timing ends
at V
CC
Q/2. Input rise and fall times (10% to 90%) < 5ns.
V
CC
Q/2
V
CC
/2
Figure 10
AC Input/Output Reference Waveform
24
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
DC CHARACTERISTICS
1
V
CC
/V
CC
Q = 1.70V1.90V
or 1.80V2.20V
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Input Low Voltage
V
IL
0
0.4
V
2
Input High Voltage
V
IH
V
CC
Q - 0.4V
V
CC
Q
V
2
Output Low Voltage
V
OL
0.10
V
I
OL
= 100A
Output High Voltage
V
OH
V
CC
Q - 0.1V
V
I
OH
= -100A
V
PP
Lockout Voltage
V
PPLK
0.4
V
V
PP
During PROGRAM/ERASE Operations
V
PP
1
0.9
2.2
V
V
PP
2
11.4
12.6
V
V
CC
Program/Erase Lock Voltage
V
LKO
1
V
Input Leakage Current
I
L
1
A
Output Leakage Current
I
OZ
1
A
V
CC
Random Read Current, 70ns cycle
I
CC
1
15
mA
3, 4
V
CC
Page Mode Read Current, 70ns/30ns cycle
I
CC
2
5
mA
3, 4
V
CC
Standby Current
I
CC
3
50
A
V
CC
Program Current
I
CC
4
55
mA
V
CC
Erase Current
I
CC
5
65
mA
V
CC
Erase Suspend Current
I
CC
6
50
A
5
V
CC
Program Suspend Current
I
CC
7
50
A
5
Read-While-Write Current
I
CC
8
80
mA
V
PP
Current
I
PP
1
(Read, Standby, Erase Suspend,
Program Suspend)
V
PP
= V
PP
1
1
A
V
PP
= V
PP
2
200
A
NOTE: 1. All currents are in RMS unless otherwise noted.
2. V
IL
may decrease to -0.4V and V
IH
may increase to V
CC
Q + 0.3V for durations not to exceed 20ns.
3. Test conditions: Vcc = V
CC
(MAX), CE# = V
IL
, OE# = V
IH
. All other inputs = V
IH
or V
IL
.
4. APS mode reduces I
CC
to approximately I
CC
3
levels.
5. I
CC
6
and I
CC
7
values are valid when the device is deselected. Any READ operation performed while in suspend mode will
have an additional current draw of suspend current (I
CC
6
or I
CC
7
).
25
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
READ CYCLE TIMING REQUIREMENTS
1
MT28F321P20 (V
CC
= 1.80V2.20V)
-70
-80
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
READ cycle time
t
RC
70
80
ns
Address to output delay
t
AA
70
80
ns
CE# LOW to output delay
t
ACE
70
80
ns
Page address access
t
APA
30
30
ns
OE# LOW to output delay
t
AOE
25
30
ns
RST# HIGH to output delay
t
RWH
200
200
ns
CE# or OE# HIGH to output High-Z
t
OD
15
25
ns
Output hold from address, CE# or OE# change
t
OH
0
0
ns
READ CYCLE TIMING REQUIREMENTS
1
MT28F321P18 (V
CC
= 1.70V1.90V)
-90
PARAMETER
SYMBOL
MIN
MAX
UNITS
READ cycle time
t
RC
90
ns
Address to output delay
t
AA
90
ns
CE# LOW to output delay
t
ACE
90
ns
Page address access
t
APA
35
ns
OE# LOW to output delay
t
AOE
30
ns
RST# HIGH to output delay
t
RWH
250
ns
CE# or OE# HIGH to output High-Z
t
OD
25
ns
Output hold from address, CE# or OE# change
t
OH
0
ns
NOTE: 1. See Figures 11 and 12 for timing requirements and load configuration.
CAPACITANCE
(T
A
= +25C; f = 1 MHz)
PARAMETER/CONDITION
SYMBOL
TYP
MAX
UNITS
Input Capacitance
C
7
12
p F
Output Capacitance
C
OUT
9
12
p F
26
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
WRITE CYCLE TIMING REQUIREMENTS
-70/-80/-90
PARAMETER
SYMBOL
MIN
MAX
UNITS
HIGH recovery to WE# going LOW
t
RS
150
ns
CE# setup to WE# going LOW
t
CS
0
ns
Write pulse width
t
WP
50
ns
Data setup to WE# going HIGH
t
DS
50
ns
Address setup to WE# going HIGH
t
AS
50
ns
CE# hold from WE# HIGH
t
CH
0
ns
Data hold from WE# HIGH
t
DH
0
ns
Address hold from WE# HIGH
t
AH
9
ns
Write pulse width HIGH
t
WPH
30
ns
RST# pulse width
t
RP
100
ns
WP# setup to WE# going HIGH
t
RHS
0
ns
V
PP
setup to WE# going HIGH
t
VPS
200
ns
Write recovery before READ
t
WOS
50
ns
WP# hold from valid SRD
t
RHH
0
ns
V
PP
hold from valid SRD
t
VPPH
0
ns
WE# HIGH to data valid
t
WB
t
AA + 50
ns
ERASE AND PROGRAM TIMING REQUIREMENTS
-70/-80/-90
PARAMETER
TYP
MAX
UNITS
4KW block program time
40
800
ms
32KW block program time
320
6400
ms
Word program time
8
10, 000
s
4KW block erase time
0.3
6
s
32KW block erase time
0.5
6
s
Program suspend latency
5
10
s
Erase suspend latency
5
20
s
27
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
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2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
SINGLE ASYNCHRONOUS READ OPERATION
VALID ADDRESS
UNDEFINED
t
OD
t
AA
t
ACE
t
OH
A0A20
OE#
CE#
WE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
RC
t
RWH
DQ0DQ15
RST#
V
OH
V
OL
VALID OUTPUT
High-Z
t
AOE
READ TIMING PARAMETERS
MT28F321P18 (V
CC
= 1.70V1.90V)
-90
SYMBOL
MIN
MAX
UNITS
t
AA
90
ns
t
ACE
90
ns
t
AOE
30
ns
t
RC
90
ns
t
RWH
250
ns
t
OD
25
ns
t
OH
0
ns
READ TIMING PARAMETERS
MT28F321P20 (V
CC
= 1.80V2.20V)
-70
-80
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
70
80
ns
t
ACE
70
80
ns
t
AOE
25
30
ns
t
RC
70
80
ns
t
RWH
200
200
ns
t
OD
15
25
ns
t
OH
0
0
ns
28
2 Meg x 16 Page Flash Memory
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MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
ASYNCHRONOUS PAGE MODE READ OPERATION
VALID ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
UNDEFINED
t
OD
t
AA
t
ACE
t
OH
t
APA
t
AOE
A0A2
OE#
CE#
WE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VALID ADDRESS
A3A20
V
IH
V
IL
t
RWH
DQ0DQ15
RST#
V
OH
V
OL
High-Z
t
RC
READ TIMING PARAMETERS
MT28F321P18 (V
CC
= 1.70V1.90V)
-90
SYMBOL
MIN
MAX
UNITS
t
AA
90
ns
t
ACE
90
ns
t
APA
35
ns
t
AOE
30
ns
t
RC
90
ns
t
RWH
250
ns
t
OD
25
ns
t
OH
0
ns
READ TIMING PARAMETERS
MT28F321P20 (V
CC
= 1.80V2.20V)
-70
-80
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
70
80
ns
t
ACE
70
80
ns
t
APA
30
30
ns
t
AOE
25
30
ns
t
RC
70
80
ns
t
RWH
200
200
ns
t
OD
15
25
ns
t
OH
0
0
ns
29
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
TWO-CYCLE PROGRAMMING/ERASE OPERATION
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
UNDEFINED
t
CH
t
DH
t
RHS
t
DS
A0A20
OE#
CE#
WE#
V
PP
RST#
WP#
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IPPLK
V
IL
V
IPPH
t
AS
t
AH
t
WPH
t
RS
t
WP
t
WOS
t
CS
t
WB
CMD
CMD/
DATA
DQ0DQ15
V
OH
V
OL
t
RHH
t
VPS
t
VPPH
STATUS
High-Z
-70/-80/-90
SYMBOL
MIN
MAX
UNITS
WRITE TIMING PARAMETERS
-70/-80/-90
SYMBOL
MIN
MAX
UNITS
t
RS
150
ns
t
CS
0
ns
t
WP
50
ns
t
DS
50
ns
t
AS
50
ns
t
CH
0
ns
t
DH
0
ns
t
AH
9
ns
t
RHS
0
ns
t
VPS
200
ns
t
WOS
50
ns
t
RHH
0
ns
t
VPPH
0
ns
t
WB
t
AA + 50
ns
30
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
RESET OPERATION
OE#
DQ0DQ15
V
IH
V
IL
RST#
V
IH
V
IL
CE#
V
IH
V
IL
V
OH
V
OL
t
RWH
t
RP
READ AND WRITE TIMING PARAMETERS
-70/-80
-90
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RWH
200
250
ns
t
RP
100
100
ns
31
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
Table 11
CFI
OFFSET
DATA
DESCRIPTION
00
2Ch
Manufacturer code
01
B2h
Top boot block device code
B3h
Bottom boot block device code
020F
reserved
Reserved
10, 11
0051, 0052
"QR"
12
0059
"Y"
13, 14
0003, 0000
Primary OEM command set
15, 16
0039, 0000
Address for primary extended table
17, 18
0000, 0000
Alternate OEM command set
19, 1A
0000, 0000
Address for OEM extended table
1B
0017
V
CC
MIN for Erase/Write; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD
1C
0022
V
CC
MAX for Erase/Write; Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in BCD
1D
00B4
V
PP
MIN for Erase/Write; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD
1E
00C6
V
PP
MAX for Erase/Write; Bit7Bit4 Volts in Hex; Bit3Bit0 100mV in BCD
1F
0003
Typical timeout for single byte/word program, 2
n
s, 0000 = not supported
20
0000
Typical timeout for maximum size multiple byte/word program, 2
n
s, 0000 = not
supported
21
0009
Typical timeout for individual block erase, 2
n
ms, 0000 = not supported
22
0000
Typical timeout for full chip erase, 2
n
ms, 0000 = not supported
23
000C
Maximum timeout for single byte/word program, 2
n
s, 0000 = not supported
24
0000
Maximum timeout for maximum size multiple byte/word program, 2
n
s, 0000 = not
supported
25
0003
Maximum timeout for individual block erase, 2
n
ms, 0000 = not supported
26
0000
Maximum timeout for full chip erase, 2
n
ms, 0000 = not supported
27
0016
Device size, 2
n
bytes
28
0001
Bus Interface x16 = 1
29
0000
Flash device interface description 0000 = async
2A, 2B
0000, 0000
Maximum number of bytes in multi-byte program or page, 2
n
2C
0003
Number of erase block regions within device (4K words and 32K words)
2D, 2E
0037, 0000
Top boot block device erase block region information 1, 8 blocks ...
0007, 0000
Bottom boot block device erase block region information 1, 8 blocks ...
2F, 30
0000, 0001
Top boot block device.....of 8KB
0020, 0000
Bottom boot block device.....of 8KB
31, 32
0006, 0000
15 blocks of ....
33, 34
0000, 0001
......64KB
(continued on the next page)
32
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
Table 11
CFI (continued)
OFFSET
DATA
DESCRIPTION
35, 36
0007, 0000
Top boot block device......48 block of
0037, 0000
Bottom boot block device......48 block of
37, 38
0020, 0000
Top boot block device......64KB
0000, 0001
Bottom boot block device......64KB
39, 3A
0050, 0052
"PR"
3B
0049
"I"
3C
0030
Major version number, ASCII
3D
0031
Minor version number, ASCII
3E
00E6
Optional Feature and Command Support
3F
0002
Bit 0 Chip erase supported no = 0
40
0000
Bit 1 Suspend erase supported = yes = 1
41
0000
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = no = 0
Bit 9 Simultaneous operation supported = yes = 1
42
0001
Program supported after erase suspend = yes
43, 44
0003, 0000
Bit 0 block lock status active = yes; Bit 1 block lock down active = yes
45
0018
V
CC
supply optimum, 00 = not supported, Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in
BCD
46
00C0
V
PP
supply optimum, 00 = not supported, Bit7Bit4 Volts in BCD; Bit3Bit0 100mV in
BCD
47
0001
Number of protection register fields in JEDEC ID space
48, 49
0080, 0000
Lock bytes LOW address, lock bytes HIGH address
4A, 4B
0003, 0003
2
n
factory programmed bytes, 2
n
user programmable bytes
4C
0002
Background Operation
0000 = Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
0004 = 50% block split
4D
0000
Burst Mode Type
0000 = No burst mode
00x1 = 4 words MAX
00x2 = 8 words MAX
00x3 = 16 words MAX
001x = Linear burst, and/or
002x = Interleaved burst, and/or
004x = Continuous burst
(continued on the next page)
33
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
Table 11
CFI (continued)
OFFSET
DATA
DESCRIPTION
4E
0002
Page Mode Type
0000 = No page mode
0001 = 4-word page
0002 = 8-word page
0003 = 16-word page
0004 = 32-word page
4F
0000
Not used
34
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.
48-BALL FBGA
0.80 0.075
0.10 C
C
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 37% Pb, 2%Ag
SOLDER BALL PAD: 0.27mm
BALL #1 ID
ENCAPSULATION MATERIAL: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
0.75
TYP
3.75
1.875 0.05
6.00 0.05
BALL #1 ID
0.75
TYP
3.50 0.05
2.625 0.05
5.25
7.00 .10
0.35
48X
TYP
12.00 0.10
1.20 MAX
BALL A8
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS 0.33
BALL A1
C
L
C
L
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
DATA SHEET DESIGNATION
Preliminary:
This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.
35
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
REVISION HISTORY
Rev. 3, PRELIMINARY ....................................................................................................................................................... 7/02
Added Programming the Chip Protection Register section
Updated Status Register section
Changed low power consumption voltage from 1.80V to 2.20
Updated command descriptions
Updated Read-While-Write/EraseConcurrency section
Updated timing diagrams
Rev. 2, PRELIMINARY ....................................................................................................................................................... 3/02
Added Notes 2 and 3 to DC Characteristics table
Original document, PRELIMINARY, Rev. 1 ................................................................................................................... 1/02
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