Document Outline

• Features/Options
• Ball Assignment 59-Ball FBGA
• General Description
• Architecture and Memory Organization
• Device Marking
  • Table 1 Cross Reference for Abbreviated Device Marks
• Part Numbering
  • Figure 1 Part Number Chart
  • Table 2 Valid Part Number Combinations
• Functional Block Diagram
• Figure 2 Bottom Boot Block Device
• Figure 3 Top Boot Block Device
• Ball Descriptions
  • Ball Descriptions (continued)
• Command State Machine (CSM)
  • Table 3 Command State Machine Codes For Device Mode Selection
• Operations
• Command Definition
• Table 4 Command Definitions
• Status Register
• Command State Machine Operations
• Table 5 Command Descriptions
  • Table 5 Command Descriptions (continued)
• CLEAR STATUS REGISTER
• READ Operations
  • Read Array
  • Read Protection Configuration Data
  • Read Query
  • Read Status Register
• Table 6 Command State Machine Transition Table
  • Table 6 Command State Machine Transition Table (continued)
  • Table 6 Command State Machine Transition Table (continued)
  • Table 6 Command State Machine Transition Table (continued)
• Table 7 Bus Operations
• Table 8 Status Register Bit Definitions
• Programming Operations
  • PROGRAM SETUP Command
  • Accelerated Programming Algorithm Command
• ERASE Operations
• Figure 4 Automated Word Programming Flowchart
• Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
• Figure 6 Accelerated Program Algorithm Flowchart
• Figure 7 BLOCK ERASE Flowchart
• Figure 8 ERASE SUSPEND/ERASE RESUME Flowchart
• Figure 9 CHECK BLOCK ERASE Flowchart
• READ-While-WRITE/ERASE Concurrency
  • Figure 10 READ-While-WRITE Concurrency
• Read Configuration Register (RCR) Mode
  • Read Configuration
    • Table 9 Read Configuration Register
  • Latency Counter
    • Figure 11 Latency Counter
  • Hold Data Output Configuration
    • Figure 12 Hold Data Output Configuration
  • WAIT# Configuration
  • Burst Sequence
  • Clock Configuration
  • Table 10 Clock Frequency vs. First Access Latency
  • Table 11 Sequence and Burst Length
  • Burst Wrap
  • Burst Length
  • Continuous Burst Length
  • WAIT# Signal in Burst Mode
• Table 12 Block Locking State Transition
• Block Locking
  • Locked State
  • Unlocked State
  • Locked Down State
  • Reading a Block's Lock Status
  • Locking Operations During ERASE SUSPEND
  • Status Register Error Checking
• Chip Protection Register
  • Reading the Chip Protection Register
  • Figure 13 Protection Register Memory Map
  • Table 13 Chip Configuration Addressing
  • Programming the Chip Protection Register
• Asynchronous Read Mode
• Synchronous Burst Read Mode
  • Figure 14 Bank Boundary Wrapping (Bottom Boot Example)
• Asynchronous Page Read Mode
• VPP/VCC PROGRAM and ERASE Voltages
  • Table 14 VPP Range (V)
• Standby Mode
• Automatic Power Save Mode
• Device Reset
• Deep Power-Down
• Power-Up Sequence
• Absolute Maximum Ratings
• Recommended Operating Conditions
• Figure 15 AC Input/Output Reference Waveform
• Figure 16 Output Load Circuit
• Capacitance
• DC Characteristics
• Asynchronous READ Cycle Timing Requirements
• Burst READ Cycle Timing Requirements
• WRITE Cycle Timing Requirements
• ERASE and PROGRAM Cycle Timing Requirements
• Timing Diagrams
  • Single Asynchronous READ Operation
  • Asynchronous Page Mode READ Operation
  • Single Synchronous READ Operation
  • 4-Word Synchronous Burst Operation
  • Continuous Burst READ Showing an Output Delay with RCR8 = 0(1)
  • Two-Cycle PROGRAMMING/ERASE Operation
  • RESET Operation
• Table 15 CFI
  • Table 15 (continued) CFI
• 59- Ball FBGA
• Revision History