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Document Outline

Features
Table of Contents
List of Figures
List of Tables

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef8098d2b5
MT28F644W30.fm - Rev. C, Pub. 7/03 EN

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

FLASH MEMORY

MT28F644W18
MT28F644W30

1.8V Low Voltage, Extended Temperature

Features

Flexible 4Mb multipartition architecture

Single word (16-bit) data bus

Support for true concurrent operation with zero latency

Basic configuration:
135 individually programmable/erasable blocks
16 Partitions (4Mb each for code and data storage)

, V

Q, V

voltages

1.65V (MIN)1.95V (MAX) V

1.65V (MIN)2.24V (MAX) V

Q (W18)

1.65V (MIN)3.3V (MAX) V

Q (W30)

1.8V (TYP) V

(in-system PROGRAM/ERASE)

12V ±5% (HV) V

tolerant (factory programming

compatibility)

Asynchronous Access Time
Random access time: 60ns @ 1.65V V

(W18)

Random access time: 70ns @ 1.65V V

(W30)

Burst mode read access

MAX clock rate: 66 MHz (

CLK = 15ns) (W18)

MAX clock rate: 54 MHz (

CLK = 18.5ns) (W30)

Burst latency 60ns @1.65V V

and 66 MHz

Burst latency 70ns @1.65V V

and 54 MHz

4 word, 8 word, and continuous burst modes

ACLK: 11ns @ 1.65V V

and 66 MHz (W18)

ACLK: 14ns @ 1.65V V

and 54 MHz (W30)

Page mode read access
Interpage read access: 60ns @ 1.65V V

(W18)

Intrapage read access: 15ns @ 1.65V V

(W18)

Interpage read access: 70ns @ 1.65V V

(W30)

Intrapage read access: 22ns @ 1.65V V

(W30)

Low power consumption (V

= 1.95V)

Burst read @ 66 MHz <8mA (TYP) (W18)
Burst read @ 54 MHz <6mA (TYP) (W30)
Standby <7µA (TYP)
Automatic power save (APS)

Enhanced write and erase suspend options
ERASE-SUSPEND-to-READ within same partition
PROGRAM-SUSPEND-to-READ within same partition
ERASE-SUSPEND-to-PROGRAM within same partition

Dual 64-bit chip protection registers for security purposes

Cross-compatible command support
Extended command set
Common flash interface

Programmable WAIT# configuration

Clock suspend

100,000 ERASE cycles per block

Fast programming algorithm (FPA)

Manufacturer's ID (ManID)
Micron

(0x2Ch)

Intel

(0x89h)

NOTE:

1. Contact factory for availability.

Part Number Example:

MT28F644W30FE-705 TET

ptions

arking

Timing
60ns access
70ns access
80ns access

-60
-70
-80

Burst Frequency
66 MHz

54 MHz
40 MHz

6
5
4

Boot Block Configuration
Top
Bottom

T
B

· I/O Voltage Range

VccQ 1.70V1.95V
VccQ 1.70V3.3V

18
30

Manufacturer's ID (ManID)
Micron (0x2Ch)
Intel (0x89h)

None

Package
56-ball VFBGA (7 x 8 ball grid)

Operating Temperature Range
Extended (-40ºC to +85ºC)

1 2 3 4 5 6

7 8

Top View

A11

A12

A13

A15

DQ7

A10

A14

DQ15

DQ14

A20

A21

WAIT#

DQ6

DQ13

DQ5

CLK

ADV#

A16

DQ4

DQ11

RST#

WE#

DQ12

DQ2

DQ10

DQ3

A18

A17

A19

WP#

DQ1

DQ9

CE#

DQ0

DQ8

OE#

Figure 1: 56-Ball VFBGA

NOTE:

1. See Table 3 for ball descriptions.
2. See Figure 35 for mechanical drawing.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Architecture and Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Command State Machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command State Machine Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Clear Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Read Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Device Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Asynchronous/Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read Configuration Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

WAIT# Signal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WAIT# Signal Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Hold Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WAIT# Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Burst Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Programming Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Conventional Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fast Programming Algorithm (FPA) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PROGRAM SUSPEND, PROGRAM RESUME, ERASE SUSPEND, ERASE RESUME Commands . . . . . . . . . . . . . . . .28
READ-While-PROGRAM/ERASE Concurrency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Locked Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Reading the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Programming the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Locking the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Program and Erase Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Automatic Power Save (APS) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Appendix A: CFI Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Appendix B: CSM Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

List of Figures

Figure 1:

56-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2:

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3:

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4:

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5:

Partition Boundary Wrapping (Bottom Boot Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 6:

Latency Counter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 7:

Hold Data Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 8:

Conventional WordProgramming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 9:

Fast Programming Algorithm (FPA) Flowchart (in-factory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 10:

Block Erase Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 11:

Program Suspend/Program Resume Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 12:

Erase Suspend/Erase Resume Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 13:

Block Locking State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 14:

Locking Operations Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 15:

Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 16:

Protection Register Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 17:

and V

at Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 18:

Reset Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 19:

AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 20:

Output Load Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 21:

Single Asynchronous READ Operation (Nonlatched Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 22:

Latched Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 23:

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 24:

Single Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 25:

READ Timing Parameters for Four-Word Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 26:

WAIT# Functionality for End-of-Word Line (EOWL) Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 27:

WAIT# Signal in Burst Non-Read Array Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 28:

WAIT# Signal in Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 29:

Two-Cycle WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 30:

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 31:

Asynchronous READ-to-WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 32:

WRITE-to-Asynchronous-READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 33:

Burst READ-to-WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 34:

Write-to-Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 35:

56-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

List of Tables

Table 1:

Cross Reference for Abbreviated Device Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 2:

Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 3:

Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4:

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5:

Command Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 6:

Command Codes and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 7

Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 8:

Status Register SR7 and SR0 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 9:

Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 10:

Clock Frequency vs. First Access Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 11:

Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 12:

Simultaneous Operations Allowed in the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 13:

Block Locking State Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 14:

Write Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 15:

Device Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 16:

Range (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 17:

Reset Parameter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 18:

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 19:

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 20:

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 21:

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 22:

Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 23:

Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 24:

WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 25:

ERASE and PROGRAM Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 26:

CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 27:

Command State Machine Transition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

General Description

The MT28F644W18/W30 is a high-performance,

high-density, nonvolatile memory solution that can
significantly improve system performance. This new
architecture features a multipartition configuration
that supports READ-while-PROGRAM/ERASE opera-
tions with no latency. A 4Mb partition size enables
optimal design flexibility.

A high-performance bus interface enables a fast

burst mode READ operation; a conventional asynchro-
nous/page bus interface is provided as well. The burst
interface increases the data throughput, minimizing
the impact of the first data latency.

The MT28F644W18/W30 enables soft protection for

blocks, as read only, by configuring soft protection reg-
isters with dedicated command sequences. For secu-
rity purposes, two 64-bit chip protection registers are
provided.

The embedded WORD PROGRAM and BLOCK

ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.

The MT28F644W18/W30 is offered with two manu-

facturing identifiers (ManID), Micron (0x2Ch) and
Intel (0x89h). this option provides flexibility for the
customer's design.

Please refer to Micron's Web site at

www.micron.com/flash

for the latest data sheet.

Architecture and Memory Organization

The MT28F644W18/W30 Flash device contains six-

teen separate partitions of memory for simultaneous
READ and PROGRAM

/ERASE operations. Burst READs

can cross partition boundaries, but the user must
ensure that the burst does not extend into a partition
that is actively programming or erasing. During a PRO-
GRAM/ERASE operation, any of the fifteen other

parti-

tions may be read. Note that only two partitions can
operate simultaneously. Partitions are configured as
follows:

· Partition 0 (bottom boot) or partition 15 (top

boot) contains eight 4K-word parameter blocks
and seven 32K-word main blocks.

· The other 15 partitions contain eight 32K-word

main blocks and comprise one-sixteenth of the
total memory.

Figure 3 depicts the memory organization.

Figure 2: Functional Block Diagram

Address

Input

Buffer

BSM

X DEC

Y/Z DEC

Data Input

Buffer

Address

CNT WSM

Output

Buffer

Status

Reg.

WSM

Program/

Erase

Pump Voltage

Generators

Address Latch

DQ0DQ15

CSM

RST#

ADV#

WAIT#

CLK

CE#

WE#

OE#

I/O Logic

A0A21

Address

Multiplexer

Data

RCR

Block Lock

Device ID

Manufacturer's ID

OTP

Query

PR Lock

X DEC

Y/Z DEC

Bank 0 Blocks

"
"

Output

Multiplexer

Bank 15 Blocks

Y/Z Gating/Sensing

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 3: Memory Organization

Bottom Boot Block Device

Top Boot Block Device

NOTE:

Total number of blocks: 8 parameter + 127 main = 135.

SIZE

(K-words)

BLOCK

64Mb

Partition

134

3F8000h3FFFFFh

.
.
.

127

3C0000h3C7FFFh

Partition

126

3B80003BFFFFh

.
.
.

119

380000h387FFFh

.
.
.

Partition

0F8000h0FFFFFh

.
.
.

0C0000h0C7FFFh

Partition

0B8000h0BFFFFh

.
.
.

080000h087FFFh

Partition

078000h07FFFFh

.
.
.

040000h047FFFh

Partition

038000h03FFFFh

.
.
.

008000h00FFFFh

Parameter

007000h007FFFh

.
.
.

000000h000FFFh

SIZE

(K-words)

BLOCK

64Mb

Partition

Parameter

134

3FF000h3FFFFFh

.
.
.

127

3F8000h3F8FFFh

126

3F00003F7FFFh

.
.
.

120

3C0000h3C7FFFh

Partition

119

3B8000h3BFFFFh

.
.
.

112

380000h387FFFh

Partition

111

378000h37FFFFh

.
.
.

104

340000h347FFFh

Partition

103

338000h33FFFFh

.
.
.

.
.

300000h307FFFh

.
.
.

.
.

.
.
.

Partition

078000h07FFFFh

.
.

040000h047FFFh

Partition

038000h03FFFFh

.
.
.

000000h007FFFh

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Device Marking

Due to the size of the package, Micron's standard

part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to the Micron part
numbers in Table 1.

Table 1:

Cross Reference for Abbreviated Device Marks

PRODUCT PART NUMBER

PRODUCT

MARKING

SAMPLE

MARKING

MECHANICAL

MARKING

MT28F644W18FE-606 BET

FW100

FX100

FY100

MT28F644W18FE-606 TET

FW112

FX112

FY112

MT28F644W18FE-606 KBET

FW115

FX115

FY115

MT28F644W18FE-606 KTET

FW116

FX116

FY116

MT28F644W18FE-70 TET

FW101

FX101

FY101

MT28F644W18FE-70 BET

FW102

FX102

FY102

MT28F644W18FE-705 BET

FW113

FX113

FY113

MT28F644W18FE-705 TET

FW114

FX114

FY114

MT28F644W18FE-705 KTET

FW117

FX117

FY117

MT28F644W18FE-705 KBET

FW118

FX118

FY118

MT28F644W30FE-70 BET

FW121

FX121

FY121

MT28F644W30FE-70 TET

FW103

FX103

FY103

MT28F644W30FE-705 TET

FW104

FX104

FY104

MT28F644W30FE-705 BET

FW108

FX108

FY108

MT28F644W30FE-705 KTET

FW119

FX119

FY119

MT28F644W30FE-705 KBET

FW120

FX120

FY120

MT28F644W30FE-804 TET

FW110

FX110

FY110

MT28F644W30FE-804 BET

FW109

FX109

FY109

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Part Numbering Information

Micron's low-power devices are available with sev-

eral different combinations of features (see Figure 4).

Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.

Figure 4: Part Number Chart

MT 28F 644W30 FE-80 4 B ET

Micron Technology

Flash Family

28F = Dual-Supply Flash

Density/Organization/Banks

64x = 64Mb (4,096K x 16)
4 = 16 banks (all banks have the same dimensions)

Access Time

-60 = 60ns
-70 = 70ns
-80 = 80ns

Read Mode Operation

W = Asynchronous/Page/Burst Read

Package Code

FE = 56-ball VFBGA (7 x 8 grid)

Operating Temperature Range

ET = Extended (-40ºC to +85ºC)

Burst Mode Frequency

4 = 40 MHz
5 = 54 MHz
6 = 66 MHz

Boot Block Starting Address

B = Bottom boot
T = Top boot

Operating Voltage Range

18 = 1.65V1.95V Vcc

1.65V2.24V VccQ

30 = 1.65V1.95V Vcc

1.65V3.30V VccQ

Manufacturer ID

None = Micron [2Ch]
K

= Intel [89h]

Table 2:

Valid Part Number Combinations

PART NUMBER

ManID

ACCESS

TIME (ns)

BOOT BLOCK

STARTING

ADDRESS

BURST

FREQUENCY

(MHz)

OPERATING

TEMPERATURE

RANGE

MT28F644W18FE-606 BET

Micron

Bottom

-40

C to +85

MT28F644W18FE-606 TET

Micron

Top

-40

C to +85

MT28F644W18FE-606 KBET

Intel

Bottom

-40

C to +85

MT28F644W18FE-606 KTET

Intel

Top

-40

C to +85

MT28F644W18FE-70 TET

Micron

Top

-40

C to +85

MT28F644W18FE-70 BET

Micron

Bottom

-40

C to +85

MT28F644W18FE-705 BET

Micron

Bottom

-40

C to +85

MT28F644W18FE-705 TET

Micron

Top

-40

C to +85

MT28F644W18FE-705 KTET

Intel

Top

-40

C to +85

MT28F644W18FE-705 KBET

Intel

Bottom

-40

C to +85

MT28F644W30FE-70 BET

Micron

Bottom

-40

C to +85

MT28F644W30FE-70 TET

Micron

Top

-40

C to +85

MT28F644W30FE-705 TET

Micron

Top

-40

C to +85

MT28F644W30FE-705 BET

Micron

Bottom

-40

C to +85

MT28F644W30FE-705 KTET

Intel

Top

-40

C to +85

MT28F644W30FE-705 KBET

Intel

Bottom

-40

C to +85

MT28F644W30FE-804 TET

Micron

Top

-40

C to +85

MT28F644W30FE-804 BET

Micron

Bottom

-40

C to +85

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Table 3:

Ball Descriptions

NOTE:

1. The CLK and ADV# inputs can be tied to V

if the device is always operating in asynchronous/page mode.

58-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

E8, D8, C8, B8, A8,
B7, A7, C7, A2, B2,
C2, A1, B1, C1, D2,

D1, D4, B6, A6, C6,

B3, C3

A0A21

Input

Address inputs: Inputs for the addresses during READ and WRITE
operations. All addresses are internally latched during WRITE cycles and
synchronous READ cycles. During asynchronous READ cycles, A0A2 are not
internally latched.

CLK

Input

Clock: Synchronizes the Flash device to the system operating frequency
during burst mode READ operations. When configured for burst mode
READs, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon
a rising ADV# edge, whichever occurs first. CLK is ignored during
asynchronous page access READ and WRITE operations.

ADV#

Input

Address Valid: Indicates that a valid address is present on the address inputs.

Addresses are latched on the rising edge of ADV# during READ operations.

CE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the device
goes into standby power mode if neither PROGRAM nor ERASE operations
are pending.

OE#

Input

Output Enable: Enables the output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.

WE#

Input

Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is either a WRITE to the command state machine (CSM) or to the
memory array.

RST#

Input

Reset: When RST# is a logic LOW, the device is in reset mode, which drives
the outputs to High-Z and resets the write state machine. When RST# is at
logic HIGH, the device is in standard operation. When RST# transitions from
logic LOW to logic HIGH, the device resets all blocks to locked and defaults
to the read array mode.

WP#

Input

Write Protect: Controls the lock down function of the flexible locking
feature.

F7, E6, E5, G5, E4, G3,

E3, G1, G7, F6, F5, F4,

D5, F3, F2, E2

DQ0
DQ15

Input/

Output

Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle
during PROGRAM operation. Inputs commands to the command user
interface when CE# and WE# are active. DQ0DQ15 output data when CE#
and OE# are active.

WAIT#

Output

Wait: Provides data valid feedback during continuous burst read access. The
signal is gated by CE#. The WAIT# signal polarity is set by RCR10 in the RCR.

A4, G4

Supply

Device Power Supply: [1.65V1.95V] Supplies power for device operation.

E1, G6

Supply

I/O Power Supply: [1.65V3.3V for W30] Supplies power for input/output
buffers.

I/O Power Supply: [1.65V2.24V for W18] Supplies power for input/output
buffers.

G2, G8

Supply

I/O Ground: Do not float any ground ball.

A3, F1

Supply

Supply Ground: Do not float any ground ball.

Internally not connected.

Supply/

Input

Program/Erase Enable: [0.9V1.95V or 11.4V12.6V] Operates as input at
logic levels to control complete device protection. Provides factory
programming compatibility, and acts as a current source, when driven to
11.4V12.6V.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Command State Machine (CSM)

Commands are issued to the command state

machine (CSM) using standard microprocessor write
timings. The CSM acts as an interface between exter-
nal microprocessors and the internal write state
machine (WSM). Table 5 defines the available com-
mands and provides data for each of the bus cycles,
and Table 6 provides the command descriptions. Pro-
gram and erase algorithms are automated by an on-
chip WSM. During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE
cycle has been requested. Table 27 on page 64 shows
the CSM transition states.

Once a valid PROGRAM/ERASE command is

entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally to accomplish the requested
operation. A command is valid only if the exact
sequence is completed. After the WSM completes its
task, the WSM status bit (SR7) (see Table 7) is set to a
logic HIGH level (V

), allowing the CSM to respond to

the full command set again.

Command State Machine Activation

Device operations are selected by entering an 8-bit

command code with conventional microprocessor
timings into an on-chip CSM through I/Os DQ0DQ7.
The number of bus cycles required to activate a com-
mand is typically one or two. The first operation is
always a WRITE. Control signals CE# and WE# must be
at a logic LOW level (V

), and OE# and RST# must be

at logic HIGH (V

). The second operation, when

needed, can be a WRITE or a READ, depending upon
the command. During a READ operation, control sig-
nals CE#, ADV#, and OE# must be at a logic LOW level
(V

), and WE# and RST# must be at logic HIGH (V

Table 4 illustrates the bus operations for all the modes:
write, read, reset, standby, and output disable.

When the device is reset, internal reset circuitry ini-

tializes the chip to a read array mode of operation.
Changing the mode of operation requires that a com-
mand code be entered into the CSM. Users can verify
the status of the operations initiated by the CSM by
reading the status register. This single status register
permits monitoring of the progress of the various
operations that can take place on a memory partition.
Status register bits SR0SR7 correspond to DQ0DQ7
(see Table 7).

NOTE:

1. The WAIT# signal is driven by CE#; polarity depends on RCR10. Valid only in synchronous mode only.

Table 4:

Bus Operations

MODE

RST#

CE#

ADV#

OE#

WE#

WAIT#

DQ0

DQ15

Read (array, status registers, device
identifier, or query)

Active

OUT

Standby

High-Z

Output disable

Active

High-Z

Reset

High-Z

Write

High-Z

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

NOTE:

1. BA:Address within the block.

IA: Identification code address.
IC:Identifier code data.
ID: Identification code data.
BBA: Block base address. The first address of a

particular block.

LPA: Lock protection register address

(BBA + 80h).

PA: Protection register address.
PBA:Partition base address. The very first
address of a particular partition.
PD: Data to be written at location PA.

PnA:Any address within a specific partition.
QA: Query code address.
QD: Query code data DQ[7:0].
RCRV: Data to be written into the read

configuration register presented on
A15A0.

SRD: Data read from the status register.
WA: Word address of memory location to be

written.

WD: Data to be written at the location WA.
XX: Any valid address within the device.

Table 5:

Command Sequencing

COMMAND

FIRST BUS CYCLE

SECOND BUS CYCLE

OPERATION

ADDRESS

DATA

OPERATION

ADDRESS

DATA

READ ARRAY

WRITE

PnA

FFh

READ DEVICE IDENTIFIER

WRITE

PnA

90h

READ

BBA + IA

READ QUERY

WRITE

PnA

98h

READ

PBA + QA

READ STATUS REGISTER

WRITE

PnA

70h

READ

SRD

CLEAR STATUS REGISTER

WRITE

50h

BLOCK ERASE SETUP

WRITE

20h

WRITE

D0h

PROGRAM SETUP

WRITE

40h/10h

WRITE

FAST PROGRAMMING ALGORITHM

WRITE

30h

WRITE

D0h

PROGRAM/ERASE SUSPEND

WRITE

B0h

PROGRAM/ERASE RESUME

WRITE

D0h

LOCK BLOCK

WRITE

60h

WRITE

01h

UNLOCK BLOCK

WRITE

60h

WRITE

D0h

LOCK-DOWN BLOCK

WRITE

60h

WRITE

2Fh

PROTECTION PROGRAM

WRITE

C0h

WRITE

LOCK PROTECTION PROGRAM

WRITE

LPA

C0h

WRITE

LPA

FFFDh

SET READ CONFIGURATION REGISTER

WRITE

RCRV

60h

WRITE

RCRV

03h

4 MEG x 16

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Table 6:

Command Codes and Descriptions

OPERATION

CODE

DEVICE

MODE

BUS

CYCLE

DESCRIPTION

READ

FFh

Read Array

First

Places the addressed partition in read array mode.

70h

Read Status
Register

First

This command places the addressed partition into read status
register mode. Reading the partition will output the contents of
the status register for the addressed partition. The device will
automatically enter this mode for the addressed partition after a
PROGRAM or ERASE operation has been initiated.

90h

Read Device
Identifier

First

Puts the addressed partition into the

read device identifier

mode so that reading the device will output the manufacturer's/
device codes, configuration register data, block lock status, or
protection register data on DQ0DQ15.

98h

Read Query

First

Puts the addressed partition into the read query mode so that
reading the partition will output common flash interface
information.

50h

Clear Status
Register

First

The WSM can set the block lock status (SR1), V

status (SR3),

program status (SR4), and erase status (SR5) bits in the status
register to "1," but it cannot clear them to "0." SR1, SR3, SR4,
and SR5 can only be cleared by a device reset or by using the
CLEAR STATUS REGISTER command.

PROGRAM

40h

Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. After the
second cycle, the device outputs status register data on the
falling edge of OE# or CE#, whichever occurs last.

10h

Program Setup

First

Equivalent to Program Setup (40h).

30h

FPA Setup

First

This program command activates FPA mode. The first write cycle
sets up the command. If the second cycle is an FPA CONFIRM
COMMAND (D0h), subsequent WRITEs provide program data.
All other commands are ignored once FPA mode begins.

D0h

FPA Confirm

Second

If the previous command was FPA SETUP (30h), the CSM latches
the address and data and prepares the device for FPA mode.

ERASE

20h

Erase Setup

First

Prepares the CSM for the ERASE CONFIRM command. If the next
command is not ERASE CONFIRM, the CSM will set both SR4 and
SR5 of the status register to a "1," place the partition into read
status register mode, and wait for another command.

D0h

Erase Confirm

Second

If the previous command was an ERASE SETUP command, then
the CSM will close the address and data latches, and it will begin
erasing the block indicated on the address pins. The device will
then output status register data on the falling edge of OE# or
CE#, whichever occurs last.

SUSPEND

B0h

Program/Erase
Suspend

First

Issuing this command will suspend the currently executing
PROGRAM/ERASE operation. The status register will indicate
when the operation has been successfully suspended by setting
either the program suspend (SR2) or erase suspend (SR6), and
the WSM status bit (SR7) to a "1" (ready). The WSM will
continue to idle in the suspend state, regardless of the state of
all input control signals except RST#, which will reset the WSM
and the remainder of the chip if RST# is driven to V

D0h

Program/Erase
Resume

First

If a PROGRAM or ERASE operation is suspended (as indicated by
SR2 or SR6), this command will resume the operation.

4 MEG x 16

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NOTE:

1. If the 60h command is not followed by D0h, 01h, 2Fh, or 03h, the CSM sets SR4 and SR5 to indicate a command

sequence error.

BLOCK LOCKING

60h

Block Lock
Setup

First

Prepares the CSM for changes to the block locking status. See
note 1.

01h

Lock Block

Second

If the previous command was BLOCK LOCK SETUP, the CSM will
latch the address and lock the block indicated on the address
bus.

D0h

Unlock Block

Second

If the previous command was BLOCK LOCK SETUP, the CSM will
latch the address and unlock the block indicated on the address
bus. If the block had been previously set to lock down, this
operation will have no effect unless WP# is driven to V

2Fh

Lock Down
Block

Second

If the previous command was BLOCK LOCK SETUP, the CSM will
latch the address and lock down the block indicated on the
address bus.

PROTECTION
PROGRAM

C0h

Protection
Register
Program Setup

First

Prepares the CSM for a PROTECTION REGISTER PROGRAM
operation. The second cycle latches address and data, and starts
the WSM's protection register program or lock algorithm. After
the second cycle, the device outputs status register data on the
falling edge of OE# or CE#, whichever occurs last. To read array
data after programming, issue a READ ARRAY command.

SET READ
CONFIGURATION
REGISTER

60h

Set Read
Configuration
Register Setup

First

Prepares the RCR to be modified. See note 1.

03h

Set Read
Configuration
Register Data

Second

If the previous command was SET READ CONFIGURATION
REGISTER SETUP, the configuration bits presented on the address
bus will be stored into the Read Configuration Register.

Table 6:

Command Codes and Descriptions (continued)

OPERATION

CODE

DEVICE

MODE

BUS

CYCLE

DESCRIPTION

4 MEG x 16

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Status Register

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is
pending or complete.

During periods when the WSM is active in a parti-

tion, that partition will default to the read status regis-
ter mode and can be polled to determine the WSM
status.

After monitoring the status register during a PRO-

GRAM/ERASE operation in a partition, that partition
will remain in read status mode until a new command
is issued to

the CSM. Table 7 defines the status register

bits.

Clear Status Register

The internal circuitry can set, but not clear, the

block lock status bit (SR1), the V

status bit (SR3), the

program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, the state
of the device does not change.

Table 7

Status Register Bit Definitions

STATUS BIT # STATUS REGISTER BIT

DESCRIPTION

SR7

WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy

SR7 indicates ERASE or PROGRAM completion in the device.
SR6SR1 are invalid while SR7 = 0. See Table 8 for valid SR7
and SR0 combinations.

SR6

ERASE SUSPEND STATUS
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in Progress/

Completed

When ERASE SUSPEND is issued, WSM halts execution and
sets both SR7 and SR6 bits to "1." SR6 bit remains set to "1"
until an ERASE RESUME command is issued.

SR5

ERASE STATUS
1 = Error in Block Erasure
0 = Successful BLOCK ERASE

When this bit is set to "1," WSM has applied the maximum
number of erase pulses to the block and is still unable to
verify successful block erasure.

SR4

PROGRAM STATUS
1 = Error in PROGRAM
0 = Successful PROGRAM

When this bit is set to "1," WSM has attempted but failed to
program a word.

SR3

STATUS

1 = V

Low Detect, Operation Abort

0 = V

= OK

The V

status bit does not provide continuous indication of

the V

level. The WSM interrogates the V

level only after

the PROGRAM or ERASE command sequences have been
entered and informs the system if V

is LOW. The V

level

is also checked before the PROGRAM/ERASE is verified by
the WSM.

SR2

PROGRAM SUSPEND STATUS
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed

When PROGRAM SUSPEND is issued, WSM halts execution
and sets both SR7 and SR2 bits to "1." SR2 bit remains set to
"1" until a PROGRAM RESUME command is issued.

SR1

BLOCK LOCK STATUS
1 = PROGRAM/ERASE Attempted on a

Locked Block; Operation Aborted

0 = No Operation to Locked Blocks

If a PROGRAM or ERASE operation is attempted to a locked
block, SR1 is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.

SR0

FAST PROGRAMMING
ALGORITHM STATUS
0 = Partition is busy, but only if SR7 = 0
1 = Another partition is busy, but only

if SR7 = 0

Addressed partition is erasing or programming. In FPA
mode, SR0 indicates a data stream word has finished
programming or verifying, depending on the FPA phase.
Refer to Table 8 for valid SR7 and SR0 combinations.

4 MEG x 16

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READ Operations

The following READ operations are available: READ

ARRAY, READ DEVICE IDENTIFIER, READ QUERY,
and READ STATUS REGISTER.

Note that READ DEVICE IDENTIFIER, READ

QUERY, and READ STATUS REGISTER will read in
either asynchronous or single burst mode.

Read Array

The array is read by entering the command code

FFh on DQ0DQ7 to each partition to be read. Control
signals CE#, ADV#, and OE# must be at a logic LOW
level (V

) and WE# and RST# must be at a logic HIGH

level (V

) to read data from the array. Data is available

on DQ0DQ15. Upon device reset, all partitions
default to the read array mode. To return the addressed
partition to read array mode, write the read array com-
mand code (FFh) on DQ0DQ7.

Read Device Identifier

The read device identifier mode outputs five types

of information: the manufacturer and device identifier,
the block locking status, the read configuration regis-
ter, and the protection register data. Two bus cycles are
required for this operation: device identifier data is
read by entering the command code 90h on DQ0DQ7
and the identification code address on the address
lines. Control signals CE#, ADV#, and OE# must be at a
logic LOW level (V

), and WE# and RST# must be at a

logic HIGH level (V

) to read device identifier data.

Data is available on DQ0DQ15. To return the
addressed partition to read array mode, write the read
array command code (FFh) on DQ0DQ7. See Table 15
on page 37 for more details.

Read Query

The read query mode outputs common flash inter-

face (CFI) data when the device is read. (See Table 26
on page 60 for more information.) Two bus cycles are
required for this operation. It is possible to access the
query by writing the read query command code 98h on
DQ0DQ7. Control signals CE#, ADV#, and OE# must
be at a logic LOW level (V

) and WE# and RST# must

be at a logic HIGH level (V

) to read data from the

query. The CFI data structure contains information
such as block size, density, command set, and electri-
cal specifications. To return the addressed partition to
read array mode, write the read array command code
(FFh) on DQ0DQ7.

Read Status Register

The status register provides the status of the device

to the external microprocessor. The status register is
read by entering the command code 70h on DQ0DQ7.
The address for both cycles must be in the same parti-
tion. Status register data is updated and latched on the
falling edge of OE#, on the falling edge of CE#, or on
the clock edge which starts a burst (whichever occurs
last). See "Burst Read Mode" on page 17 for burst oper-
ation. Latching the data prevents errors from occur-
ring if the register input changes while monitoring the
status register.

The status register outputs the data on DQ0DQ7.

Table 7 contains the status register definitions.

To return the addressed partition to read array

mode, write the read array command code (FFh) on
DQ0DQ7.

Table 8:

Status Register SR7 and SR0 Description

SR7

SR0

DESCRIPTION

The addressed partition is performing a PROGRAM/ERASE operation.
FPA: Device is finished programming or verifying data or is ready for data.

A partition other than the one currently addressed is performing a PROGRAM/ERASE operation.
FPA: the device is either programming or verifying data.

No PROGRAM/ERASE operation is in progress in any partition. Erase and program suspend bits
(SR6 and SR2) indicate whether other partitions are suspended.

Will not occur in standard PROGRAM/ERASE operations.
FPA: This combination will not occur.

4 MEG x 16

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Read Modes

The MT28F644W18/W30 supports two read config-

urations: asynchronous/page mode and burst mode.
The RCR15 bit (see Table 9) in the read configuration
register sets the read configuration. At reset, asynchro-
nous/page mode is the default configuration for all
READ operations.

Asynchronous/Page Read Mode

Asynchronous/page read mode is the default read

configuration state. To use the device in an asynchro-
nous-only application, ADV# and CLK may be tied to
V

, and WAIT# should be floated. Note that ADV# may

also be used in asynchronous mode to latch addresses
(latched asynchronous read mode).

A random access is initiated either on the falling

edge of CE#, on the falling edge of ADV#, or on a transi-
tion of the address lines (A0A21), whichever occurs
last. Access times are given by

ACE,

AADV, and

AA,

respectively.

A latched asynchronous read mode is also available

in which all address lines except A0A2 are latched. In
this mode, the rising edge of ADV# will latch the
addresses. After the addresses are latched, this mode
becomes identical to the normal mode. The latched
mode is useful when noise is present on the address
lines, which might cause a READ operation from
unwanted locations.

Page mode is a performance-enhancing extension

to the legacy asynchronous READ operation. The ini-
tial portion of the page mode cycle is the same as the
asynchronous access cycle. Subsequent READs are
performed by holding CE# LOW and toggling A0A2,
allowing random access of other words in the page.
These subsequent READs are done at the faster page
access time,

APA.

Burst Read Mode

The burst read mode is used to achieve a faster data

rate than is possible with asynchronous read mode. A
burst access is started when an active clock edge
(defined by RCR6; refer to Table 9 for more informa-
tion) occurs after ADV# goes LOW. The address is
latched when ADV# goes HIGH or on the active clock
edge, whichever occurs first. The burst read configura-
tion is set in the read configuration register.

Burst READ operations can traverse partition

boundaries, but application code is responsible for
ensuring that the operations do not extend into parti-
tions that are programming or erasing. All blocks in all
partitions are burstable. For example, if a burst starts
in partition 0, the application can keep clocking until

the partition boundary is reached, and then read from
partition 1. If the application keeps clocking beyond
partition 15 last location, then the internal counter
restarts from partition 0 first address (see Figure 5).

Figure 5: Partition Boundary Wrapping

(Bottom Boot Example)

Clock Suspend

The clock suspend feature enables the device to sus-

pend a burst sequence, to allow data to be retrieved
from another device sharing the same bus. The system
processor can resume the burst sequence where it left
off at a later time, with zero initial access latency pen-
alty. Clock suspend is most beneficial in non-cached
systems.

Clock suspend can occur at any stage of a burst,

during initial access latency, or when outputting data.
When a burst access is suspended, internal array sens-
ing continues, and any previously latched internal
data is retained. As long as the device operation condi-
tions are met, a burst sequence can be suspended and
resumed without any limit.

Clock suspend is executed when CE# is asserted, the

current address has been latched (either ADV# rising
edge or CLK edge), CLK is halted, and OE# is de-
asserted. CLK can be halted when it is at V

or V

. To

resume, OE# is re-asserted and CLK is restarted. Sub-
sequent CLK edges resume the burst sequence where
it left off.

Note that when using the clock suspend feature, the

device's WAIT# signal remains active. Multiple devices
should not share the systems's READY signal when
using the clock suspend feature. Refer to the WAIT#
signal configuration on RCR8.

Partition 0 start address

Partition boundary

Partition 0

Partition 15

000000h

Partition 0 end address

03FFFFh

Partition 15 start address

3C0000h

Partition 15 end address

3FFFFFh

Partition 1 start address

040000h

Partition 1 end address

07FFFFh

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Read Configuration Register (RCR)

The SET READ CONFIGURATION REGISTER com-

mand is a sequence used to load the read configura-
tion register (RCR). It is a two-cycle command
sequence. Read configuration setup (60h) is written,
followed by a second WRITE (03h) that specifies the
value to be written to the read configuration register.

The new RCR settings are placed on the address bus
(A0A15), and are latched on the rising edge of CE# or
WE#, whichever occurs first. Refer to Table 9 for the
RCR bit settings. After setting the RCR, the device auto-
matically returns to read array mode. Upon reset, the
RCR is set to FFCFh.

Table 9:

Read Configuration Register

BIT #

DESCRIPTION

FUNCTION

Read Mode

0 = Synchronous Burst Access Mode
1 = Asynchronous/Page Access Mode (defau

lt)

Reserved

Default = 1

1311

Latency Code

Sets the number of clock cycles before valid data out (see Figure 6

000 = Code 0 - reserved
001 = Code 1 - reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6 - reserved
111 = Code 7 - reserved (

default)

Wait Signal Polarity

0 = WAIT# signal is active LOW
1 = WAIT# signal is active HIGH (

default)

Hold Data Out

Sets the data output configuration:
0 = Hold data for one clock
1 = Hold data for two clocks (

default)

Wait Configuration

Controls the behavior of the WAIT# output signal:
0 = WAIT# asserted during delay
1 = WAIT# asserted one data cycle before delay (

default)

Burst Sequence

Specifies the order in which data is addressed in synchronous burst mode:
0 = Reserved
1 = Linear (

default)

Clock Configuration

Defines the clock edge on which the burst operation starts and data is referenced:
0 = Falling edge
1 = Rising edge (

default)

Reserved

Default = 0

Burst Wrap

0 = Burst wraps within the burst length
1 = Burst no wrap (

default)

Burst Length

Sets the number of words the device will output in burst mode:
001 = 4 words
010 = 8 words
011 = reserved
111 = Continuous burst (

default)

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WAIT# Signal Function

When performing a continuous burst, or when per-

forming a four- or eight-word burst with no wrap
selected (RCR3 = 1), the device may have an output
delay when the burst sequence crosses the first eight-
word boundary. The delay will occur only once during
any burst access. The starting address dictates the
amount of delay. If the starting address is at the end of
an eight-word boundary, the output delay will be the
maximum delay. If the starting address is aligned with
an eight-word boundary, a delay will not be seen. Like-
wise, if a burst never crosses an eight-word boundary,
no delay will be seen. For example, in a four-word
burst, no-wrap mode, possible linear burst sequences
that do not cause delays are:

0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
4-5-6-7
The WAIT# signal informs the system if an output

delay occurs. When the WAIT# signal is asserted, it
indicates invalid data. When the WAIT# signal is deas-
serted, it indicates valid data. See Figure 26 for more
details.

The WAIT# output is high impedance until the

device is active (CE# = V

). In asynchronous/page

mode, WAIT# is set to an asserted state (as defined by

RCR10). WAIT# is also set to an asserted state during
non-read-array burst operations such as burst read of
status register, query, or device identifier.

During clock suspend, WAIT# remains active

because CE# gates the WAIT# signal. The WAIT# signal
does not revert to a high-impedance state when OE# is
de-asserted and therefore can cause contention with
another device attempting to control the system's
ready signal during a clock suspend. Multiple devices
should not be connected directly to the sysem's
READY ready signal if the clock suspend feature is
used.

Read Mode

The device supports two read configurations: burst

mode, and asynchronous/page mode. The RCR15 bit
(refer to Table 9) in the read configuration register sets
the read mode. Asynchronous/page mode is the
default read mode.

Latency Counter

The latency counter (RCR13RCR11) provides the

number of clocks that must elapse after the clock edge
that starts the burst before data is valid, as shown in
Figure 6. This value depends on the input clock fre-
quency. See Table 10 for the clock frequency vs. first
access latency information.

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Figure 6: Latency Counter

NOTE:

1. CLK shown as rising edge configuration (RCR6 = 1).

VALID

OUTPUT

A0-A21

ADV#

DQ0-DQ15

CLK

O L

Code 2

Code 3

DQ0-DQ15

O L

DQ0-DQ15

O L

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

ADDRESS

UNDEFINED

DQ0-DQ15

O L

Code 4

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Code 5

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Table 10: Clock Frequency vs. First Access Latency

LATENCY COUNTER CODE

4/5

Frequency (MHz)

£40

£54

£66

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WAIT# Signal Polarity

RCR10 sets the WAIT# signal polarity. When

RCR10 = 0, WAIT# is active LOW. When RCR10 = 1, the
WAIT# signal is active HIGH. See "WAIT# Signal Func-
tion" on page 19 for more information.

Hold Data Out

The hold data out (RCR9) specifies for how many

clocks data will be held valid. (See Figure 7.)

Figure 7: Hold Data Output Configuration

NOTE:

WAIT# shown active HIGH (RCR10 = 1).

WAIT# Configuration

The wait configuration bit (RCR8) controls the

WAIT# signal behavior for all burst read modes. It
should be set according to the system and CPU charac-
teristics. The WAIT# signal can be configured to assert
either during valid data, or one data cycle before data
becomes valid (see Figure 6). See "WAIT# Signal Func-
tion" on page 19 for more information.

Burst Sequence

The burst sequence (RCR7) specifies the ordering of

data in burst mode. Linear burst order (RCR7 = 1) is the
only burst sequence supported by the device. See
Table 11 for more details.

Clock Configuration

The clock configuration (RCR6) defines the clock

edge on which the burst operation starts and data is
defined.

CLK

DQ0DQ15

Hold
Data

1 CLK

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DQ0DQ15

Hold
Data

2 CLK

VALID

OUTPUT

VALID

OUTPUT

ACLK

Note 1

WAIT# (RCR8 = 1)

WAIT# (RCR8 = 0)

WAIT# (RCR8 = 1)

WAIT# (RCR8 = 0)

KHTL

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Burst Wrap

The burst wrap option (RCR3) determines whether

the burst access wraps within the burst length or
crosses the burst length boundary. In wrap mode
(RCR3 = 0) the four- or eight-word access will wrap
within the four or eight words, respectively. In no-wrap
mode (RCR3 = 1), the device operates similarly to a
continuous burst. See Table 11 for more details.

Burst Length

The burst length (RCR2RCR0) defines the number

of words the device outputs. The device supports burst
lengths of four words, eight words, or continuous
burst. When the continuous burst option is selected,
the internal address wraps to 000000h after reaching
the maximum address.

Table 11: Sequence and Burst Length

STARTING

ADDRESS

(DEC)

WRAP

NO WRAP

4-WORD

BURST LENGTH

8-WORD

BURST LENGTH

CONTINUOUS

BURST

RCR3

LINEAR

0-1-2-3

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-...

1-2-3-0

1-2-3-4-5-6-7-0

1-2-3-4-5-6-7-...

2-3-0-1

2-3-4-5-6-7-0-1

2-3-4-5-6-7-8-...

3-0-1-2

3-4-5-6-7-0-1-2

3-4-5-6-7-8-9-...

4-5-6-7-0-1-2-3

4-5-6-7-8-9-10-...

5-6-7-0-1-2-3-4

5-6-7-8-9-10-11-...

6-7-0-1-2-3-4-5

6-7-8-9-10-11-12-...

7-0-1-2-3-4-5-6

6-7-8-9-10-11-12-13-...

...

14-15-16-17-18-19-20-..

15-16-17-18-19-20-21-..

...

0-1-2-3

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-...

1-2-3-4

1-2-3-4-5-6-7-8

1-2-3-4-5-6-7-...

2-3-4-5

2-3-4-5-6-7-8-9

2-3-4-5-6-7-8-...

3-4-5-6

3-4-5-6-7-8-9-10

3-4-5-6-7-8-9-...

4-5-6-7-8-9-10-11

4-5-6-7-8-9-10-...

5-6-7-8-9-10-11-12

5-6-7-8-9-10-11...

6-7-8-9-10-11-12-13

6-7-8-9-10-11-12...

...

7-8-9-10-11-12-13-14

7-8-9-10-11-12-13...

...

14-15-16-17-18-19-20-...

15-16-17-18-19-20-21-...

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

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MT28F644W30.fm Rev. C, Pub. 7/03 EN

Programming Operations

In addition to the traditional single word program-

ming commands (10h and 40h), another sequence is
offered to speed up the in-factory programming oper-
ations (30h). The in-factory programming operation is
compatible with the use of an external power supply
connected to the V

ball. For in-system operations,

the V

ball can be connected either to a general pur-

pose I/O ball of the host system, or the V

ball.

Conventional Word Programming

After the setup command code is entered (10h/40h)

on DQ0DQ7, followed by the data to be programmed,
the WSM takes over and correctly sequences the
device to complete the PROGRAM operation. The
PROGRAM operation may be monitored through the
status register. During this time, the CSM will only
respond to a PROGRAM SUSPEND, READ ARRAY,

READ DEVICE IDENTIFIER, READ QUERY, and READ
STATUS REGISTER command until the PROGRAM
operation has been completed, after which time, all
commands to the CSM become valid again.

Taking RST# to V

during programming aborts the

PROGRAM operation, leaving undetermined data in
the location being programmed. When programming
is aborted, a delay time of

PRD must elapse after RST#

goes LOW before the internal RESET operation is com-
plete. An additional delay of

RWH must elapse after

RESET is complete (or after RST# goes HIGH, which-
ever occurs last) before data can be read from the
device. Refer to Figure 18 and Table 17 for more infor-
mation. During programming, V

must remain above

PPLK

, and V

must remain in the voltage range pro-

vided in the recommended operating conditions.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 8: Conventional

WordProgramming Flowchart

NOTE:

1. Full status register check can be done after each word or after a sequence of words.
2. SR1, SR3, and SR4 are cleared only by the CLEAR STATUS REGISTER command, but do not prevent additional PRO-

GRAM operation attempts.

Full Status Register

Check (optional)

Write 40h,

Word Address

PROGRAM

SUSPEND Loop

Write Word Data,

Word Address

Read Status

YES

Start

Word Program

Completed

Read Status

FULL STATUS REGISTER CHECK FLOW

Word Program Passed

Range Error

YES

SR7 = 1?

YES

PROGRAM

SUSPEND?

SR3 = 0?

YES

Lock Block Error

SR4 = 0?

YES

Program Error

SR1 = 0?

BUS
OPERATION

COMMAND

COMMENTS

WRITE

WRITE
PROGRAM
SETUP

Data = 40h
Addr = Address of word to

be programmed

WRITE

WRITE
DATA

Data = Word to be

programmed

Addr = Address of word to

be programmed

READ

Status register data
Toggle OE# or CE# to
update status register.

Check SR7
1 = Ready, 0 = Busy

BUS
OPERATION COMMAND

COMMENTS

READ

Check SR3

1 = V

range error

Check SR4

1 = Data program error

Check SR1
1 = Attempted PROGRAM to
locked block. PROGRAM
aborted.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Fast Programming Algorithm (FPA)
Mode

The fast programming algorithm (FPA) is intended

for in-factory use. It enables fast data stream program-
ming. For in-factory programming, FPA minimizes
chip programming time when 11.4V

< V

< 12.6V. FPA

algorithm can also provide accelerated program with
V

= 1.8V. Executing the FPA command (30h) followed

by FPA CONFIRM (D0h), enables an entire block to be
programmed. This eliminates the need to continu-
ously update the address to be programmed.

An initial delay is required after issuing the FPA

command. (See Table 25.) If the block is locked, the
status register returns an error. When the FPA com-
mand is executed successfully, a data stream can be
programmed beginning at the first address. The

address can be held constant, or it can be incremented
within the address range. The program cycle ends
when the programmer writes FFFFh outside the
address range of the current block.

When the FPA is activated, the data must be pro-

vided in sequential order to the WSM. Immediately
after programming, verification is executed. The data
sequence and starting address are provided to the
WSM, which automatically performs a data verifica-
tion. The result is stored in the status register. Writing
FFFFh outside the memory block boundary exits the
verification cycle. Figure 9 shows the FPA flowchart.

Note that issuing a 70h command to the device after

FPA setup will be interpreted as data and will be writ-
ten to the device.

Figure 9: Fast Programming Algorithm (FPA) Flowchart (in-factory only)

NOTE:

1. When reading the status register, the address must be within the block being programmed.
2. During FPA verify, if a word fails to verify, status changes to 90h.
3. BA = Address within block.
4. WA = First word Address to be written in the block.

Start

FPA Setup

Exit

Operation

Complete

WRITE 30h

Address = WA

WRITE D0h

Address = WA

FPA Setup Time

Read

Status Register

Check V

and

Lock Errors

(SR3, SR1)

Unlock Block

SR7 = 0

SR7 = 1

FPA Setup

Done?

WRITE Data

Address = WA

Read

Status Register

WRITE FFFFh

Address

Read

Status Register

SR0 = 0

SR0 = 1

SR0 = 0

SR0 = 1

Yes

SR0 = 0

SR0 = 1

Yes

Data

Stream Ready?

Program

Done?

Last Data?

WRITE Data

Address = WA

Read

Status Register

WRITE FFFFh

Address

Read

Status Register

SR0 = 0

SR0 = 1

Verify

Stream Ready?

Verify

Done?

Last Data?

Full Status

Check Procedure

Read

Status Register

SR7 = 1

SR7 = 0

FPA

Exited?

FPA Program

FPA Verify

FPA Exit

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

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ERASE Operations

An ERASE operation must be used to initialize bits

in an array block to "1s." The commands to initiate
BLOCK ERASE are as follows: BLOCK ERASE SETUP
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Figure 10).

A two-command erase sequence protects against

accidental erasure of memory contents.

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence
of events to complete the BLOCK ERASE. During this
sequence, the block is programmed with logic 0s, the
0s are then verified, all bits in the block are erased to
logic 1 state, and finally verification is performed to
ensure that all bits are correctly erased. During an
ERASE, V

must remain above V

PPLK

, and V

must

remain in the voltage range provided in the recom-

mended operating conditions. Monitoring of the
ERASE operation is possible through the status regis-
ter. SR7 = 1 indicates the ERASE operation is complete.
SR5 = 1 indicates an ERASE failure; SR3 = 1 indicates
an invalid V

supply voltage; and SR1 = 1 indicates an

ERASE operation was attempted on a locked block.

Taking RST# to V

during an ERASE aborts the

ERASE operation leaving undetermined data in the
block being erased. When an ERASE is aborted, a delay
time of

ERD must elapse after RST# goes LOW, before

the internal RESET operation is complete. An addi-
tional delay of

RWH must elapse after the RESET is

complete (or after RST# goes HIGH, whichever occurs
last) before data can be read from the device. Refer to
Figure 18 and Table 17 for more information.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 10: Block Erase Flowchart

NOTE:

1. Full status register check can be done after each block or after a sequence of blocks.
2. SR1, SR3, SR4, and SR5 are cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are

erased before full status is checked. (These bits do not prevent additional ERASE operation attempts.)

Full Status Register

Check (optional)

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

ERASE

SUSPEND Loop

Read Status

YES

Start

BLOCK ERASE

Completed

Read Status

FULL STATUS REGISTER CHECK FLOW

BLOCK ERASE Passed

Range Error

YES

SR7 = 1?

YES

ERASE

SUSPEND?

SR3 = 0?

Command Sequence Error

YES

SR[4:5] = 1?

YES

Lock Block Error

SR5 = 0?

YES

Block Erase Error

SR1 = 0?

BUS
OPERATION

COMMAND

COMMENTS

WRITE

WRITE
ERASE
SETUP

Data = 20h
Block Addr = Address
within block to be erased

WRITE

ERASE

Data = D0h
Block Addr = Address within
block to be erased

READ

Status register data
Toggle OE# or CE# to
update status register

Check SR7
1 = Ready, 0 = Busy

BUS
OPERATION

COMMAND

COMMENTS

READ

Check SR3

1 = V

error

Check SR4 and SR5

Both = 1 = Command
sequence error

Check SR5

1 = BLOCK ERASE error

Check SR1

1 = Attempted ERASE of
locked block. ERASE
aborted.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

PROGRAM SUSPEND, PROGRAM
RESUME, ERASE SUSPEND, ERASE
RESUME Commands

During the execution of an ERASE/PROGRAM oper-

ation, the SUSPEND command (B0h) can be issued to
direct the WSM to suspend the ERASE/PROGRAM
operation. Once the WSM has reached the suspend
state, it allows the CSM to respond only to the READ
ARRAY, READ STATUS REGISTER, READ QUERY,
READ DEVICE IDENTIFIER, and PROGRAM RESUME.
Additionally, PROGRAM, PROGRAM SUSPEND, ERASE
RESUME, LOCK BLOCK, UNLOCK BLOCK, and LOCK
DOWN BLOCK are valid commands during an ERASE
SUSPEND. (See Block Locking section).

Once in erase suspend mode, array data must be

read/programmed into a block other than the one
being erased. During the PROGRAM SUSPEND opera-
tion, array data should be read from an address other
than the one being programmed. To resume the
ERASE/PROGRAM operation, a RESUME command

(D0h) needs to be issued to cause the CSM to clear the
suspend state previously set (see Figure 12). The
RESUME command (D0h) needs to be issued when the
device is in the ready state, SR7 = 1. If the RESUME
command is issued when the device is busy, SR7 = 0,
the WSM will ignore the RESUME command.

It is also possible that an ERASE in any block can be

suspended and a PROGRAM to another block within
any partition can be initiated. At this point, a PRO-
GRAM SUSPEND may be issued to allow a READ of yet
another location. After the completion of a READ oper-
ation, PROGRAM can be resumed by issuing a PRO-
GRAM RESUME command. Finally, after the device
has reached the ready state, SR7 = 1, an ERASE
RESUME will allow the WSM to finish the original
ERASE operation.

A minimum time should elapse between an ERASE

RESUME command and a subsequent ERASE SUS-
PEND command to ensure that the device achieves
sufficient cumulative erase time.

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Figure 11: Program Suspend/Program

Resume Flowchart

NOTE:

If the suspended partition was placed in read array
mode, then the following condition applies:

Issue READ ARRAY

Command

Issue PROGRAM

RESUME Command

Issue READ STATUS

Command

Issue PROGRAM

SUSPEND Command

Issue READ STATUS

Command

Same Partition

Read Status

Start

YES

SR7 = 1?

YES

Finish

Reading?

Program Resumed

YES

SR2 = 1?

Read Array Data

Write FFh

Program Partition

Program Complete

Full Status Register

Check (optional)

BUS
OPERATION

COMMAND

COMMENTS

WRITE

PROGRAM
SUSPEND

Data = B0h

WRITE

READ
STATUS

Data = 70h

READ

Status register data
Toggle OE# or CE# to
update status register

Check SR7
1 = Ready

Check SR2
1 = Suspended

WRITE

READ
MEMORY

Data = FFh

READ

Read data from block other
than that being
programmed

WRITE

PROGRAM/
RESUME

Data = D0h

BUS
OPERATION

COMMAND

COMMENTS

WRITE

READ
STATUS

Return partition to status
mode:
Data = 70h
Addr = address within same
partition

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 12: Erase Suspend/Erase Resume

Flowchart

NOTE:

If the suspended partition was placed in read array
mode or a program loop, then the following condition
applies:

NOTE:

1. See Word Programming flowchart for complete programming procedure.
2. See BLOCK ERASE flowchart for complete erase procedure.

Issue READ ARRAY

Command

Issue ERASE

RESUME Command

Issue ERASE

SUSPEND Command

Issue READ STATUS

Command

Same Partition

Issue READ STATUS

Command

Same Partition

Read Status

Start

YES

SR7 = 1?

YES

READ

or PROGRAM

Complete?

ERASE Continued

YES

SR6 = 1?

ERASE Complete

READ

READ or

PROGRAM?

PROGRAM

(Note 1)

PROGRAM Loop

BUS
OPERATION COMMAND COMMENTS

WRITE

ERASE
SUSPEND

Data = B0h

WRITE

READ
STATUS

Data = 70h
Addr = Any address in same
partition

Check SR7
1 = Ready, 0 = Busy

Check SR6
1 = Suspended
0 = Completed

WRITE

READ
ARRAY

Data = FFh
Addr = Any device address
(except block being erased)

READ or
WRITE

Read data from, or write
data to, a block other than
that being erased

WRITE

ERASE
RESUME

Data = D0h
Addr = Any address

BUS
OPERATION COMMAND COMMENTS

WRITE

READ
STATUS

Return partition to status
mode
Data = 70h
Addr = Address within same
partition

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

READ-While-PROGRAM/ERASE Concur-
rency

It is possible for the device to read from one parti-

tion while erasing/programming to another partition.
For example, during a READ CONCURRENCY opera-
tion, if a PROGRAM or ERASE operation is being per-
formed in partition x, then partition x changes to the

read status mode and an array READ operation can be
performed on any other partition. Partition x will
remain in read status mode.

The CFI and the device identifier areas are consid-

ered an additional partition separate from the array
partitions and support concurrent operations. (See
Table 12 for simultaneous operations allowed between
the protection register and the main partitions.)

Block Locking

The Flash device provides a flexible locking scheme

that allows each block to be individually locked or
unlocked with no latency.

The device offers two-level protection for the

blocks. The first level allows software-only control of
block locking (for data that needs to be changed fre-
quently), while the second level requires hardware
interaction before locking can be changed (code that
does not require frequent updates).

Control signals WP#, DQ1, and DQ0 define the state

of a block; for example, state [001] means WP# = 0,
DQ1 = 0, and DQ0 = 1. See "Reading a Block's Lock Sta-
tus" on page 34.

Table 13 defines all of the possible locking states,

Figure 13 shows the block locking state diagram, and
Figure 14 describes the locking operations.

Table 12: Simultaneous Operations Allowed in the Protection Register

PROTECTION

MAIN PARTITION

DESCRIPTION

READ

PROGRAM/ERASE

During the programming or erasing of a main partition, the protection register
may be read from any other partition.

PROGRAM

READ

During the programming of the protection register, READs are only allowed in
the main partitions. A delay of 200ns must be inserted after issuing the
PROTECTION PROGRAM command (C0h) before performing concurrent read of
the main partitions.

Table 13: Block Locking State Transition

WP#

DQ1

DQ0

NAME

ERASE/PROG

ALLOWED

LOCK

UNLOCK

LOCK

DOWN

Unlocked

Yes

To [001]

No Change

To [011]

Locked

(Default)

No Change

To [000]

To [011]

Lock Down

No Change

Unlocked

Yes

To [101]

No Change

To [111]

Locked

No Change

To [100]

To [111]

Lock Down

Disabled

Yes

To [111]

No Change

To [111]

Lock Down

Disabled

No Change

To [110]

No Change

4 MEG x 16

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Figure 13: Block Locking State Diagram

UNLOCKED

WP# = V

= 0

WP# = V

= 1

LOCKED

[000]

60h/D0h

60h/01h

60h/2Fh

Power-Up/Reset

Default

Power-Up/Reset

Default

Locked-Down

Locked-Down is disabled by

WP# = V

60h/2Fh

60h/D0h = UNLOCK command

60h/01h = LOCK command

60h/2Fh = LOCK DOWN command

= WP# hardware control (bidirectional)

= WP# hardware control (unidirectional)

60h/2Fh

60h/D0h

60h/01h

[001]

[011]

[110]

[100]

[111]

[101]

4 MEG x 16

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Figure 14: Locking Operations

Flowchart

Locked State

After a reset sequence, all blocks are locked (states

[001] or [101]). This means full protection from alter-
ation. Any PROGRAM or ERASE operations attempted
on a locked block will return an error on bit SR1 of the
status register. The status of a locked block can be
changed to unlocked or lock down using the appropri-
ate software commands. Writing the LOCK SETUP
command sequence (60h) followed by UNLOCK
BLOCK (D0h) can unlock a locked block.

Unlocked State

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked
down by writing the LOCK SETUP command (60h) fol-
lowed by LOCK BLOCK (01h), or LOCK DOWN BLOCK
(2Fh).

Locked Down State

The lock down function is dependent on the WP#

input. When WP# = 0, blocks in lock down [011] are
protected from PROGRAM, ERASE, and lock status
changes. When WP# reverts to WP# = 1, the lock down
function is disabled [111], and locked down blocks can
be individually unlocked by a software command to
the [110] state, where they can be erased and pro-
grammed. These blocks can then be relocked [111] and
unlocked [110] as desired while WP# remains HIGH.
When WP# goes LOW, blocks that were previously
locked down return to the locked down state [011]
regardless of any changes made while WP# was HIGH.
A locked or unlocked block can be locked down by
writing the LOCK SETUP command (60h) followed by
LOCK DOWN (2Fh). Resetting the device resets all
blocks, including those in lock down, to the locked
state (see Table 13).

BUS
OPERATION COMMAND

COMMENTS

WRITE

LOCK SETUP

Data = 60h
Addr = BLOCK to LOCK/UNLOCK/

LOCK DOWN (BA)

WRITE

LOCK,
UNLOCK, or
LOCK DOWN
CONFIRM

Data = 01h (LOCK BLOCK)

D0h (UNLOCK BLOCK)
2Fh (LOCK DOWN BLOCK)

Addr = BLOCK to LOCK/UNLOCK/

LOCK DOWN (BA)

WRITE
(Optional)

READ ID

Data = 90h
Addr = BA

READ
(Optional)

BLOCK LOCK
STATUS

Data = Block Lock Status Data
Addr = BBA + 02h

Confirm locking change on DQ[1:0].
See Table 13 for valid
combinations.

Write 60h,

Block Address

Write 01h/D0h/2Fh,

Block Data

Read Block Lock

Status

Write 90h,

Start

Lock Change

Complete

Optional

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Reading a Block's Lock Status

The lock status of every block can be read in the

read device identifier mode. To enter this mode, write
90h to the device. Subsequent READs at the base block
address +00002 will output the lock status of that
block. The lowest two outputs, DQ0 and DQ1, repre-
sent the lock status. DQ0 indicates the block lock/
unlock status and is set by the LOCK command and
cleared by the UNLOCK command. It is also automati-
cally set when entering lock down. DQ1 indicates lock
down status and is set by the LOCK DOWN command.
It can only be cleared by reset or power-down, not by
software. Table 13 on page 31 shows the locking state
transition scheme and Table 14 shows the write pro-
tection truth table.

Locking Operations During Erase Sus-
pend

Changes to a block's lock status can be performed

during an erase suspend by using the standard locking
command sequences to unlock, lock, or lock down.
This is useful in the case when another block needs to
be updated while an ERASE operation is in progress.

To change a block's lock status during an ERASE

operation, first write the ERASE SUSPEND command
(B0h), then check the status register until it indicates
that the ERASE operation has been suspended. Next,
write the desired LOCKING command sequence to the
desired block, and the block's lock status will be
changed. After completing any desired LOCK, READ,
or PROGRAM operations, resume the ERASE operation
with the ERASE RESUME command (D0h).

If an erase suspended block has its lock status

changed, the lock status bits will change immediately.
When the ERASE is resumed, the ERASE operation will
complete. A LOCKING operation cannot be performed
during a PROGRAM SUSPEND.

Using nested locking or program command

sequences during erase suspend can introduce ambi-
guity into status register results. Following protection
configuration setup (60h), an invalid command will
produce a command sequence error (SR4 and SR5 will
be set to "1") in the status register. If a command
sequence error occurs during an erase suspend, SR4
and SR5 will be set to "1" and will remain at "1" after
the erase suspend is resumed. When the ERASE is
complete, any possible error during the ERASE cannot
be detected via the status register because of the previ-
ous command sequence error. This is also true if an
error occurs during a PROGRAM operation error
nested within an erase suspend.

Table 14: Write Protection Truth Table

WP# RST# WRITE PROTECTION

Device inaccessible

Word program and block erase
prohibited

All lock down blocks locked

All lock down blocks can be unlocked

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Protection Register

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits of the protection register
(addresses 81h84h) are programmed at the factory
with a unique 64-bit unchangeable number. DQ0 of
the PR lock register (address 80h) is programmed to a
"0" state, locking the first 64 bits and preventing any
further programming.

The second 64 bits (addresses 85h88h) are left

erased for the user to program as desired (see
Figure 15). The user can program any information into
this area as long as DQ1 of the PR lock register (address
80h) remains unprogrammed. After DQ1 of the PR lock
register is programmed, no further programming is
allowed in the user area. ERASE operations are not
allowed on the protection register.

READ-While-WRITE operation is only allowed

between the chip protection register and main parti-
tions. Table 12 describes the simultaneous operations
allowed in the chip protection register.

Figure 15: Protection Register Memory

Map

Reading the Protection Register

The protection register is read in the device identi-

fier mode. To enter this mode, load the 90h command.
Once in this mode, READ cycles from addresses shown
in Table 15 on page 37 retrieve the specified informa-
tion. To return to the read array mode, write the READ
ARRAY command (FFh).

Programming the Protection Register

The user area of the protection register (addresses

85h88h) may be programmed by writing the PRO-
TECTION PROGRAM command (C0h), followed by the
data to be programmed at one of the addresses within
the user area. This procedure may be repeated for each
of the addresses in the user area, as long as DQ1 of the
PR lock register remains unprogrammed. Issuing a
PROTECTION PROGRAM command outside the regis-
ter's address space results in a status register error (SR4
= 1). See Figure 16 on page 36 for more information.

4 Words

Factory-Programmed

4 Words

User-Programmed

PR Lock

88h

85h

84h

81h

80h

DQ1 DQ0

4 MEG x 16

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Figure 16: Protection Register

Programming Procedure

Full Status Check

(if desired)

Write C0h,

Addr = Prot Addr

Read Status Register

Write Protection

RegisterAddress/Data

Start

YES

SR7 = 1?

YES

SR3, SR4 = 1?

Program Successful

Program Complete

Read SRD

Range Error

YES

SR3 = 0, SR4 = 1?

YES

SR1 = 1, SR4 = 1?

Programming Error

Locked-Register

Program Aborted

BUS
OPERATION COMMAND

COMMENTS

WRITE

PROTECTION
PROGRAM
SETUP

Data = C0h
Addr = Protection address

WRITE

Data = Data to program
Addr = Protection address

READ

Read SRD
Toggle CE# or OE# to
update SRD

Check SR7
1 = WSM Ready
0 = WSM Busy

Protection program operations addresses must be within
the protection register address space. Addresses outside
this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each
PROGRAM or after a sequence of PROGRAM operations.

BUS
OPERATION COMMENTS

READ

SR1 SR3 SR4

error

Protection register
program error

Only the CLEAR STATUS REGISTER command clears SR1,
SR3, and SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.

4 MEG x 16

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Locking the Protection Register

DQ0 of the PR lock register is programmed to "0" by

the factory to protect the unique device number. DQ1
of the PR lock register can be programmed by the user
to lock the user portion (upper 64 bits) of the chip pro-
tection register (refer to Figure 15). This bit is set using
the PROTECTION PROGRAM command, C0h, to pro-
gram FFFDh into the PR lock register (address 80h).

After DQ1 of the PR lock register is programmed, the

user's protection register cannot be changed. The PR
lock register will read FFFCh. PROTECTION PRO-
GRAM commands written to a locked section result in
a status register error (SR1 = 1, SR4 = 1).

NOTE:

1. Address = base + offset.
2. Different ManID devices are ordered via separate part numbers. See Figure 4 on page 9 for details.
3. Different Device ID codes are dependent on the Manufacturer's ID ordered. See Figure 4 on page 9 for details.

Table 15: Device Identifier Codes

ITEM

ADDRESS

DATA

DESCRIPTION

BASE

OFFSET

Manufacturer's ID (ManID)

Block

00h

002Ch
0089h

Micron ManID
Intel ManID

Device ID Code (DevID)

Block

01h

44C6h
44C7h

64Mb top boot device (Micron)
64Mb bottom boot device (Micron)

8864h
8865h

64Mb top boot device (Intel)
64Mb bottom boot device (Intel)

Block lock status

Block

02h

DQ0 = 0

Block is unlocked

DQ0 = 1

Block is locked

Block lock down status

Block

02h

DQ1 = 0

Block is not locked down

DQ1 = 1

Block is locked down

Read configuration register

Block

05h

Protection register lock status

Block

80h

Lock data

Protection register

Block

81h84h

Factory data

85h88h

User data

4 MEG x 16

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Program and Erase Voltages

The Flash device provides in-system programming

and erase with V

in the 0.9V1.95V range (V

). The

12V V

mode programming is offered for compatibil-

ity with existing programming equipment.

The device can withstand 100,000 PROGRAM/

ERASE operations with V

= V

1, or 1,000 PRO-

GRAM/ERASE operations with V

= V

In addition to the flexible block locking, the V

pro-

gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V

is below V

PPLK

, any PROGRAM or ERASE

operation will result in an error, prompting the corre-
sponding status register bit (SR3) to be set.

During PROGRAM and ERASE operations, the WSM

monitors the V

voltage level. PROGRAM/ERASE

operations are allowed only when V

is within the

ranges specified in Table 16.

When V

is below V

LKO

, any PROGRAM/ERASE

operation will be disabled.

Device Reset

To reset the device, the RST# signal must be asserted

(RST# = V

) for a minimum of

RP. After reset, the

device defaults to read array mode, the status register
is set to 80h, and the read configuration register
defaults to asynchronous/page read mode. A delayed
access time of

RWH from the rising edge of RST# must

elapse before data can be read from the device. The
circuitry used to generate the RST# signal needs to be
common with the system reset. Refer to the timing dia-
gram for further details.

If RST# is asserted during a PROGRAM or ERASE

operation, the operation will be aborted and the mem-
ory contents at the aborted block or address are
invalid.

Power-Up Sequence

The device is protected against accidental block era-

sure or programming during power transitions. If V

Q, and V

are connected together, it does not mat-

ter whether V

or V

powers up first.

If V

Q and/or V

are not connected to the system

supply, then V

should attain V

(MIN) before

applying V

Q and V

. Device inputs should not be

driven before supply voltage = V

(MIN). Power sup-

ply transitions should only occur when RST# is LOW.

When V

is applied within the in-factory program-

ming range (V

2), the sequence shown in Figure 17

must be followed. Applying V

within the in-system

programming range (V

1) does not require this

sequence.

Figure 17: V

and V

at Power Up

Standby Mode

supply current is reduced by applying a logic

HIGH level on CE# to enter the standby mode. In the
standby mode, the outputs are at a high impedance
state independent of OE#. Applying a logic HIGH level
on CE# reduces the current to I

s. If the device is

deselected during an ERASE operation or during pro-
gramming, the device continues to draw current until
the operation is complete.

Automatic Power Save (APS) Mode

Substantial power savings are realized during peri-

ods when the array is not being read and the device is
in active mode. During this time, the device switches
to the automatic power save (APS) mode. When the
device switches to APS mode, I

is reduced to a level

comparable to I

CCS

. Further power savings can be real-

ized by applying a logic HIGH level on CE# to place the
device in standby mode. The low level of power is
maintained until another operation is initiated. In this
mode, the I/Os retain the data from the last memory
address read until a new address is read. This mode is
entered automatically if no address or control signals
toggle.

Table 16: V

Range (V)

SYMBOL

MIN

MAX

0.9

1.95

11.4

12.6

PP2

T1 > 50µs

T2 > 1µs

4 MEG x 16

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Figure 18: Reset Operations

NOTE:

Address signals and control signals CE#, ADV#, WE#, and OE# not shown. Refer to the appropriate READ timing diagrams
for correct operation of these signals.

RST#

CCRS

RWH

PRD

ERD

Abort

Complete

Abort

Complete

RWH

PRD

ERD

RWH

RST#

Reset during
read mode

Reset during
program or block erase

PRD

ERD

Reset during
program or block erase

PRD

ERD

VALID

OUTPUT

DQ0DQ15

O L

Table 17: Reset Parameter Definitions

PARAMETER

SYMBOL

MIN

MAX

UNIT

RST# pulse width

100

RST# HIGH to output delay

RWH

150

RST# LOW during PROGRAM to RESET operation complete

PRD

µs

RST# LOW during BLOCK ERASE to RESET operation complete

ERD

µs

setup to RST# going HIGH

VCCRS

µs

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Electrical Specifications

NOTE:

1. Stresses greater than those listed in Table 18 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

2. Maximum DC voltage on V

may overshoot to +14V for periods < 20ns.

Table 18: Absolute Maximum Ratings

PARAMETERS/CONDITIONS

MIN

MAX

UNITS

NOTES

Voltage to any ball except V

, V

Q, and V

(W18)
(W30)

-0.5
-0.5

+2.45
+3.45

Voltage

-0.2 +14

Supply Voltage

(W18)
(W30)

-0.2
-0.2

+2.45
+2.45

Q Supply Voltage

(W18)
(W30)

-0.2
-0.2

+2.45

+3.465

Output Short Circuit Current

100

Operating Temperature Range

-40 +85

°C

Storage Temperature Range

-65

+125

°C

Soldering Cycle

260°C for 10s

Table 19: Recommended Operating Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Operating Temperature

-40

+85

Supply Voltage

1.65

1.95

I/o Supply Voltage

Q (W18)

1.65

2.24V

VccQ (W30)

3.3V

Input/output Capacitance: DQs

4.0

6.5

Voltage

0.9

1.95

In-factory Programming Voltage

11.4

12.6

Block Erase Cycling (V

= V

100,000

Cycles

Block Erase Cycling (V

= V

1,000

Cycles

Time For V

at V

PPH

100

Hours

Table 20: Capacitance

= +25

°C; f = 1 MHz

PARAMETER/CONDITION

SYMBOL

W18

W30

UNITS

TYP

MAX

TYP

MAX

Input Capacitance

Output Capacitance

OUT

Clock Capactitance

CLK

4 MEG x 16

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Table 21: DC Characteristics

All currents are in RMS unless otherwise noted

PARAMETER

SYM

MIN

W18

W30

UNITS NOTES

TYP

MAX

TYP

MAX

Input Low Voltage

0.4

Input High Voltage

Q 0.4

Output Low Voltage
I

= 100µA

0.1

Output High Voltage
I

= -100µA

Q 0.1

Lockout Voltage

PPLK

0.4

Lock

LKO

1.0

VccQ Lock

ILKOQ

0.9

Input Load Current

±1

µA

Output Leakage Current

±1

µA

Standby Current

CCS

7 25 µA

Asynchronous Read Current

CCR

2, 3

Page Read Current

CCR

Vcc Burst Read Current

4-word Burst Read Current @ 40 MHz
4-word Burst Read Current @ 54 MHz
4-word Burst Read Current @ 66 MHz

CCR

2
3
3

4
5
5

2
3
3

4
5
5

2, 3

Vcc Burst Read Current

8-word Burst Read Current @ 40 MHz

8-word Burst Read Current @ 54 MHz
8-word Burst Read Current @ 66 MHz

CCR

2
3
3

4
5
5

2
3
3

4
5
5

2, 3

Vcc Continuous Burst Read Current

Continous Burst Read Current @ 40 MHz
Continous Burst Read Current @ 54 MHz
Continous Burst Read Current @ 66 MHz

CCR

5
7
8

10
12

5
7
8

10
12

2, 3

Program Current

= V

1, Program in Progress

= V

2, Program in Progress

CCW

25
15

Block Erase Current

= V

1, Block Erase in Progress

= V

2, Block Erase in Progress

CCE

30
15

Program Suspend Current

CCWS

µA

Erase Suspend Current

CCES

µA

Automatic Power Save Current

CCAPS

µA

Standby Current

Program Suspend Current

PPS

PPWS

0.2
0.2

5
5

0.2
0.2

5
5

µA

4 MEG x 16

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NOTE:

1. V

may decrease to -0.4V and V

may increase to V

Q + 0.3V for durations not to exceed 20ns.

2. APS mode reduces I

to approximately I

CCS

levels.

3. Test conditions: V

= V

(MAX), CE# = V

, OE# = V

. All other inputs = V

or V

4. I

CCES

and I

CCWS

values are valid when the device is deselected. Any READ operation performed while in suspend

mode will have an additional current draw of suspend current (I

CCES

or I

CCWS

Erase Suspend Current

Read Current

PPES

PPR

0.2

µA

Program Current

= V

1, Program in Progress

= V

2, Program in Progress

PPW

0.05

0.10

0.05

0.10

Erase Current V

= V

1, Erase in Progress

Erase Current V

= V

2, Erase in Progress

PPE

0.05

0.10

0.05

0.10

Table 21: DC Characteristics

All currents are in RMS unless otherwise noted

PARAMETER

SYM

MIN

W18

W30

UNITS NOTES

TYP

MAX

TYP

MAX

4 MEG x 16

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Figure 19: AC Input/Output Reference Waveforms

NOTE:

AC test inputs are driven at V

Q for a logic 1 and V

for a logic 0. Input timing begins at V

Q/2, and output timing

ends at V

Q/2. Input rise and fall times (10% to 90%) < 5ns.

Figure 20: Output Load Circuit

NOTE:

1. Minimum recommended capacitive loading is 5pF.

Table 22: Asynchronous READ Cycle Timing Requirements

See Figure 19 and Figure 20 for timing requirements and load configuration.

PARAMETER

SYM

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

READ cycle time

Address to output delay

CE# LOW to output delay

ACE

OE# LOW to output delay

AOE

RST# HIGH to output delay

RWH

150

CE# LOW to output in Low-Z

CEZ

OE# LOW to output in Low-Z

OEZ

CE# or OE# HIGH to output High-Z

Output hold from address, CE# or OE#
transition

Address setup to ADV# HIGH

AVS

CE# LOW to ADV# HIGH

CVS

ADV# LOW to output delay

AADV

ADV# pulse width LOW

ADV# pulse width HIGH

VPH

Address hold from ADV# HIGH

AVH

Page address access

APA

Output

Test Points

Input

Q/2

Rise and Fall Levels

Input

90% V

10% V

I/O

16.7K

30pF

16.7K

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Table 23: Burst READ Cycle Timing Requirements

PARAMETER

SYM

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

CLK period

CLK

18.5

CLK frequency

CLK

MHz

CLK HIGH (LOW) time

9.5

CLK fall (rise) time

KHKL

Address valid setup to CLK

AKS

ADV# LOW setup to CLK

VKS

CE# LOW setup to CLK

CKS

CLK to output valid (latency codes 3, 4, and 5)

ACLK

CLK to output valid (latency code 2)

ACLK

Output hold from CLK

KOH

Address hold from CLK

AKH

CLK to WAIT# valid

KHTL

CE# LOW to WAIT# valid

CEWV

CE# HIGH to WAIT# High-Z

CEWZ

CE# HIGH between subsequent burst READs

CBPH

Table 24: WRITE Cycle Timing Requirements

PARAMETER

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

RST# HIGH recovery to WE# (CE#) going LOW

150

CE# (WE#) setup to WE# (CE#) going LOW

Write pulse width

Data setup to WE# (CE#) going HIGH

Address setup to WE# (CE#) going HIGH

CE# (WE#) hold from WE# (CE#) HIGH

Data hold from WE# (CE#) HIGH

Address hold from WE# (CE#) HIGH

Write pulse width HIGH

WPH

setup to WE# (CE#) going HIGH

VPS

200

hold from valid SRD

VPPH

WP# hold from valid SRD

RHH

WP# setup to WE# (CE#) going HIGH

RHS

200

WE# HIGH to OE# LOW

WOA

Write recovery before READ

WOS

WE# HIGH to output valid

AA+20

WE# HIGH to address valid

WAV

WE# HIGH to CLK valid

WCV

WE# HIGH to ADV# HIGH

WAH

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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NOTE:

1. Excludes external system-level overhead.
2. Exact results may vary based on system overhead.
3. Measurements are based on T = 25°C and nominal voltage conditions unless otherwise specified.

Table 25: ERASE and PROGRAM Timing Requirements

OPERATION

PARAMETER

DESCRIPTION

PP1

PP2

UNIT

NOTES

TYP

MAX

TYP

MAX

Erasing and Suspending

Erase Time

ERS/PB

4 KW parameter block

0.3

2.5

0.25

2.5

1, 2

ERS/MB

32 KW main block

0.7

0.4

1, 2

Suspend

Latency

SUSP/P

PROGRAM SUSPEND

µs

SUSP/E

ERASE SUSPEND

µs

Conventional Word Programming

Program

Time

PROG/W

Single word

150

130

µs

1, 3

PROG/PB

4 KW parameter block

0.03

0.07

0.03

0.07

1, 2

PROG/MB

32 KW main block

0.24

0.6

0.24

0.6

1, 2

Fast Programming Algorithm

Program

FPA/W

Single word

3.5

µs

FPA/PB

4KW parameter block

1, 2

FPA/MB

32KW main block

120

1, 2

Operation

Latency

FPA/SETUP

FPA Setup

µs

FPA/TRAN

Program-to-verify transition

2.7

5.6

2.7

5.6

µs

FPA/VERIFY

Verify

1.7

150

1.7

130

µs

4 MEG x 16

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Figure 21: Single Asynchronous READ Operation (Nonlatched Mode)

READ Timing Parameters

A0A21

CE#

OE#

WE#

DQ0DQ15

UNDEFINED

O L

VALID

OUTPUT

VALID

ADDRESS

High-Z

ACE

AOE

RWH

OEZ

CEZ

High-Z

RST#

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

ACE

AOE

RWH

150

CEZ

OEZ

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Figure 22: Latched Asynchronous READ Operation

READ Timing Parameters

A0A2

ADV#

UNDEFINED

CE#

OE#

WE#

DQ0DQ15

O L

High-Z

A3A21

AVS

VPH

AVH

AADV

ACE

CVS

AOE

RWH

OEZ

CEZ

High-Z

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

RST#

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

ACE

AOE

RWH

150

CEZ

OEZ

AVS

CVS

AADV

VPH

AVH

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Figure 23: Page Mode READ Operation

NOTE:

1. WAIT# is shown active LOW.

READ Timing Parameters

UNDEFINED

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

A0A2

ADV#

CE#

WAIT#

O L

OE#

WE#

DQ0DQ15

O L

High-Z

Note 1

A3A21

AVS

VPH

AVH

AADV

ACE

CVS

AOE

APA

OEZ

CEZ

High-Z

RWH

RST#

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

ACE

AOE

RWH

150

CEZ

OEZ

AVS

CVS

AADV

VPH

AVH

APA

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Figure 24: Single Burst READ Operation

NOTE:

1. Figure 6 on page 20 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).

READ Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

A0A21

CLK

UNDEFINED

CLK

VALID

ADDRESS

ADV#

CE#

OE#

WE#

DQ0DQ15

O L

High-Z

VALID

OUTPUT

Note 1

WAIT#

High-Z

Note 2

High-Z

AKH

AKS

AVS

AVH

VKS

VPH

CVS

CKS

ACLK

KOH

CEWV

AOE

OEZ

High-Z

CEWZ

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AOE

OEZ

AVS

CVS

VPH

AVH

AKS

VKS

CKS

ACLK

KOH

AKH

CEWZ

TBD

CLK

18.5

CEWV

9.5

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Figure 25: READ Timing Parameters for Four-Word Burst Operation

NOTE:

1. Figure 6 on page 20 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).

READ Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

A0A21

CLK

UNDEFINED

VALID

ADDRESS

ADV#

CE#

OE#

WE#

DQ0DQ15

O L

VALID

OUTPUT

Note 1

WAIT#

High-Z

Note 2

High-Z

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

AKS

AKH

AVS

AVH

VPH

VKS

CVS

CKS

AOE

ACLK

KOH

KHTL

CBPH

OEZ

CEZ

CLK

High-Z

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AOE

OEZ

CEZ

AVS

CVS

VPH

AVH

AKS

VKS

CKS

ACLK

KOH

AKH

KHTL

CLK

18.5

CBPH

9.5

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

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Figure 26: WAIT# Functionality for End-of-Word Line (EOWL) Condition

NOTE:

1. Figure 6 on page 20 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).

READ Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

A0A21

CLK

ADV#

CE#

OE#

WE#

DQ0DQ15

O L

Note 1

WAIT#

UNDEFINED

VALID

ADDRESS

VALID

OUTPUT

High-Z

Note 2

High-Z

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

AKS

AKH

AVS

AVH

VPH

VKS

CVS

AADV

ACE

CKS

CEZ

AOE

ACLK

KOH

KHTL

CEWV

OEZ

High-Z

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AKS

VKS

CKS

ACLK

KOH

AKH

KHTL

CEWV

TBD

AVS

AVH

VPH

AADV

ACE

AOE

CVS

OEZ

CEZ

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 27: WAIT# Signal in Burst Non-Read Array Operation

NOTE:

1. Figure 6 on page 20 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).

READ Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

A0A21

CLK

ADV#

CE#

OE#

WE#

DQ0DQ15

O L

WAIT#

UNDEFINED

VALID

ADDRESS

High-Z

VALID

OUTPUT

Note 1

High-Z

Note 2

High-Z

AKH

AKS

AVS

AVH

VKS

VPH

CVS

CKS

ACLK

KOH

CEZ

AOE

OEZ

High-Z

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AOE

OEZ

CEZ

AVS

CVS

VPH

AVH

AKS

VKS

CKS

ACLK

KOH

AKH

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 28: WAIT# Signal in Asynchronous READ Operation

NOTE:

1. WAIT# shown active LOW.

READ Timing Parameters

A0A21

CE#

OE#

WE#

DQ0DQ15

O L

WAIT#

UNDEFINED

High-Z

Note 1

ACE

AOE

OEZ

CEZ

High-Z

VALID

ADDRESS

VALID

OUTPUT

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

ACE

AOE

CEZ

OEZ

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 29: Two-Cycle WRITE Operation

NOTE:

1. Status register data (SRD) may be read after a two-cycle PROGRAM/ERASE sequence to determine completion of the PRO-

GRAM/ERASE algorithm.

WRITE Timing Parameters

A0A21

CE# (WE#)

OE#

WE# (CE#)

DQ0DQ15

UNDEFINED

ADV#

DATA IN

VALID

SRD

RST#

WP#

VPPH

PPLK

WPH

RHS

VPS

VPPH

RHH

WOS

WAH

WAV

Note 1

High-Z

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

AVS

AVH

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

150

AVH

7/ 7/ 9

AVS

7/ 7/ 10

WPH

7/ 7/ 10

VPS

200

VPPH

RHH

RHS

200

WOS

AA+20

WAV

WAH

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 30: Clock Suspend

READ Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

A0A21

CLK

UNDEFINED

ADV#

CE#

OE#

WE#

DQ0DQ15

O L

WAIT#

AKS

AKH

AVS

AVH

VKS

VPH

CVS

CKS

ACLK

KOH

KHTL

AOE

CLK

AOE

CBPH

OEZ

CEZ

High-Z

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

High-Z

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AOE

AVS

CVS

VPH

AVH

OEZ

AKS

VKS

CKS

CLK

18.5

ACLK

KOH

AKH

9.5

CEZ

KHKL

CBPH

KHTL

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 31: Asynchronous READ-to-WRITE Operation

READ Timing Parameters

WRITE Timing Parameters

A0A21

CE#

OE#

WE#

DQ0DQ15

UNDEFINED

O L

High-Z

AOE

ACE

VALID

OUTPUT

DATA IN

OEZ

CEZ

High-Z

VALID

ADDRESS

VALID

ADDRESS

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

ACE

AOE

OEZ

CEZ

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 32: WRITE-to-Asynchronous-READ Operation

READ Timing Parameters

WRITE Timing Parameters

A0A21

CE#

OE#

WE#

RST#

DQ0DQ15

O L

High-Z

WOA

ACE

WAV

High-Z

UNDEFINED

VALID

OUTPUT

DATA IN

AOE

VALID

ADDRESS

VALID

ADDRESS

SYMBOL

-60

-70

-80

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

ACE

AOE

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

150

WOA

WAV

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 33: Burst READ-to-WRITE Operation

NOTE:

1. Figure 6 on page 20 describes how to insert clock cycles during initial access.

READ Timing Parameters

WRITE Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

AKS

AKH

AVS

VPH

AVH

CVS

KHTL

ACLK

CEZ

AOE

KOH

WPH

Note 1

A0A21

CLK

CE#

OE#

WE#

DQ0DQ15

WAIT#

ADV#

OEZ

CBPH

WAV

High-Z

UNDEFINED

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

DATA IN

VKS

CKS

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AKS

VKS

AKH

AVS

VPH

AVH

CVS

CKS

AOE

KHTL

OEZ

CEZ

KOH

CBPH

ACLK

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

WPH

WAV

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Figure 34: Write-to-Burst READ Operation

NOTE:

1. Figure 6 on page 20 describes how to insert clock cycles during initial access.

READ Timing Parameters

WRITE Timing Parameters

NOTE:

1. Latency codes 3, 4, and 5.
2. Latency code 2.

High-Z

A0A21

CLK

CE#

OE#

WE#

RST#

DQ0DQ15

CKS

AVH

AKH

AKS

VKS

AOE

KHTL

ACLK

KOH

ACLK

WAIT#

ADV#

CBPH

WAV

WCV

WAH

UNDEFINED

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

DATA IN

VALID

OUTPUT

Note 1

SYMBOL

-606

-705

-804

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

AKS

VKS

AKH

AVH

CKS

AOE

KHTL

KOH

ACLK

CBPH

SYMBOL

-60/-70/-80

UNITS

MIN

MAX

150

WAV

WCV

WAH

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Appendix A: CFI Table

Table 26:

CFI

OFFSET

DATA

DESCRIPTION

2Ch

Manufacturer's ID (ManID)
Micron

89h

Intel

44C6h/8864h

Device ID Code (DevID)
Top boot block device ID code (Micron / Intel)

44C7h/8865h Bottom boot block device ID code (Micron / Intel)

02 0F

reserved

Reserved

10, 11

0051, 0052

"QR"

0059

"Y"

13, 14

0003, 0000

Primary OEM command set

15, 16

0039, 0000

Address for primary extended table

17, 18

0000, 0000

Alternate OEM command set

19, 1A

0000, 0000

Address for OEM extended table

0017

MIN for Erase/Write; Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

0019

MAX for Erase/Write; Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

00B4

MIN for Erase/Write; Bit 7bit 4 volts in Hex; Bit 3bit 0 100mV in BCD

00C6

MAX for Erase/Write; Bit 7bit 4 volts in Hex; Bit 3bit 0 100mV in BCD

0004

Typical timeout for single byte/word program, 2

µs, 0000 = not supported

0000

Typical timeout for maximum size multiple byte/word program, 2

µs, 0000 = not supported

000A

Typical timeout for individual block erase, 2

s, 0000 = not supported

0000

Typical timeout for full chip erase, 2

s, 0000 = not supported

0004

Maximum timeout for single byte/word program, 2

µs times typical, 0000 = not supported

0000

Maximum timeout for maximum size multiple byte/word program, 2

µs, 0000 = not

supported

0002

Maximum timeout for individual block erase, 2

s, 0000 = not supported

0000

Maximum timeout for full chip erase, 2

s, 0000 = not supported

0017

Device size, 2

bytes

0001

Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3

0000

Flash device interface description 0000 = async

2A, 2B

0000, 0000

Maximum number of bytes in multibyte program or page, 2

0002

Number of erase block regions within device (4K words and 32K words)

2D, 2E

007E, 0000

Top boot block device erase block region information 1

0007, 0000

Bottom boot block device erase block region information 1

2F, 30

0000, 0001

Top boot block device erase block region information 1

0020, 0000

Bottom boot block device erase block region information 1

31, 32

0007, 0000

Top boot block device erase block region information 2

007E, 0000

Bottom boot block device erase block region information 2

33, 34

0020, 0000

Top boot block device erase block region information 2

0000, 0001

Bottom boot block device erase block region information 2

35, 36

0000, 0000

Reserved for future erase block region information

37, 38

0000, 0000

Reserved for future erase block region information

39, 3A

0050, 0052

"PR"

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

0049

"I"

0031

Major version number, ASCII

0033

Minor version number, ASCII

3E
3F
40
41

00E6
0003
0000
0000

Optional Feature and Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = yes = 1
Bit 9 Simultaneous operation supported = yes = 1

0001

Program supported after erase suspend = yes

43, 44

0003, 0000

Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

0018

supply optimum, 00 = not supported, Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

00C0

supply optimum, 00 = not supported, Bit 7bit 4 volts in BCD; Bit 3bit 0 100mV in BCD

0001

Number of protection register fields in JEDEC ID space

48, 49

0080, 0000

Lock bytes LOW address, lock bytes HIGH address

4A, 4B

0003, 0003

factory programmed bytes, 2

user programmable bytes

0004

Page mode read capability

0003

Number of synchronous mode read configuration fields that follow

0001

Synchronous mode read capability configuration 1

0002

Synchronous mode read capability configuration 2

0007

Synchronous mode read capability configuration 3

0000

Synchronous mode read capability configuration 4

Top:0002

Number of device hardware partition regions within the device

Bot:0002

Top: 000F

Number of identical partitions within the partition region

Bot: 0001

Top: 0000

Number of identical partitions within the partition region

Bot: 0000

Top: 0011

Number of PROGRAM/ERASE operations allowed in a partition

Bot: 0011

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in program mode

Bot: 0000

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in erase mode

Bot: 0000

Top: 0001

Types of erase block regions in this partition region

Bot: 0002

Top: 0007

Partition region 1 erase block type 1 information

Bot: 0007

Top: 0000

Partition region 1 erase block type 1 information

Bot: 0000

Top: 0000

Partition region 1 erase block type 1 information

Bot: 0020

Table 26:

CFI (continued)

OFFSET

DATA

DESCRIPTION

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Top: 0001

Partition region 1 erase block type 1 information

Bot: 0000

Top: 0064

Partition 1 (erase block type 1)

Bot: 0064

Top: 0000

Partition 1 (erase block type 1)

Bot: 0000

Top: 0001

Partition 1 (erase block type 1) bits per cell; internal ECC

Bot: 0001

Top: 0003

Partition 1 (erase block type 1) page mode and synchronous mode capabilities

Bot: 0003

Bot: 61

Partition region 1 erase block type 2 information

Bot: 0006

Bot: 62

Partition region 1 erase block type 2 information

Bot: 0000

Bot: 63

Partition region 1 erase block type 2 information

Bot: 0000

Bot: 64

Partition region 1 erase block type 2 information

Bot: 0001

Bot: 65

Partition region 1 (erase block type 2)

Bot: 0064

Bot: 66

Partition region 1 (erase block type 2)

Bot: 0000

Bot: 67

Partition region 1 (erase block type 2) bits per cell

Bot: 0001

Bot: 68

Partition region 1 (erase block type 2) page mode and synchronous mode capabilities

Bot: 0003

Top: 61

Top: 0001

Number of identical partitions within the partition region

Bot: 69

Bot: 000F

Top: 62

Top: 0000

Number of identical partitions within the partition region

Bot: 6A

Bot: 0000

Top: 63

Top: 0011

Number of PROGRAM/ERASE operations allowed in a partition

Bot: 6B

Bot: 0011

Top: 64

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in program mode

Bot: 6C

Bot: 0000

Top: 65

Top: 0000

Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in erase mode

Bot: 6D

Bot: 0000

Top: 66

Top: 0002

Types of erase block regions in this partition region

Bot: 6E

Bot: 0001

Top: 67

Top: 0006

Partition region 2 erase block type 1 information

Bot: 6F

Bot: 0007

Top: 68

Top: 0000

Partition region 2 erase block type 1 information

Bot: 70

Bot: 0000

Top: 69

Top: 0000

Partition region 2 erase block type 1 information

Bot: 71

Bot: 0000

Table 26:

CFI (continued)

OFFSET

DATA

DESCRIPTION

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Top: 6A

Top: 0001

Partition region 2 erase block type 1 information

Bot: 72

Bot: 0001

Top: 6B

Top: 0064

Partition 2 (erase block type 1)

Bot: 73

Bot: 0064

Top: 6C

Top: 0000

Partition 2 (erase block type 1)

Bot: 74

Bot: 0000

Top: 6D

Top: 0001

Partition 2 (erase block type 1) bits per cell

Bot: 75

Bot: 0001

Top: 6E

Top: 0003

Partition 2 (erase block type 1) page mode and synchronous mode capabilities

Bot: 76

Bot: 0003

Top:6F

Top: 0007

Partition region 2 erase block type 2 information

Top: 70

Top: 0000

Partition region 2 erase block type 2 information

Top: 71

Top: 0020

Partition region 2 erase block type 2 information

Top: 72

Top: 0000

Partition region 2 erase block type 2 information

Top: 73

Top: 0064

Partition 2 (erase block type 2)

Top: 74

Top: 0000

Partition 2 (erase block type 2)

Top: 75

Top: 0001

Partition 2 (erase block type 2) bits per cell

Top: 76

Top: 0003

Partition 2 (erase block type 2) page mode and synchronous mode capabilities

777F

Reserved

Table 26:

CFI (continued)

OFFSET

DATA

DESCRIPTION

4 ME

G x 16

AS
YNC/

AGE

/
B

URS

FLA

MOR

PRELI

M
INA

09005

aef8098d

2b
5

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In
c.

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.

MT28

W30.

ev
.

C

,
Pu

.
7/
03
EN

c
r
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Tec

l
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,
I

c
.

Appendix B: CSM Table

Table 27: Command State Machine Transition Table

Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a
time.

CURRENT CHIP STATE

DEVICE NEXT STATE AFTER COMMAND INPUT

READ

ARRAY

(FFh)

PROGRAM

SETUP

4,5

(10h/40h)

ERASE

SETUP

4,5

(20h)

FPA

SETUP

(30h)

BLOCK
ERASE

CONFIRM,

PROGRAM/

ERASE

RESUME,

UNLOCK

BLOCK

CONFIRM

(D0h)

PROGRAM/

ERASE

SUSPEND

(B0h)

READ

STATUS

(70h)

CLEAR

STATUS

(50h)

READ

ID/

QUERY

(90h,

98h)

LOCK,

UNLOCK,

LOCK

DOWN,

RCR

SETUP

(60h)

OTP

SETUP

(C0h)

LOCK BLOCK

CONFIRM

(01h)

LOCK

DOWN
BLOCK

CONFIRM

(2Fh)

WRITE RCR

CONFIRM

(03h)

FPA EXIT

(ADDRESS

<> BA)

(FFFFh)

ILLEGAL

COMMANDS

OR FPA DATA

(OTHER CODES)

WSM

OPERATION
COMPLETES

READY

Ready

Program

Setup

Erase

Setup

FPA

Setup

Ready

Lock/RCR

Setup

OTP

Setup

Ready

N/A

LOCK/RCR SETUP

Ready (Lock Error)

Ready

Ready (Lock Error)

Ready

Ready (Lock Error)

OTP

SETUP

OTP Busy

BUSY

Ready

PROGRAM

SETUP

Program Busy

N/A

BUSY

Program Busy

Program
Suspend

Program Busy

Ready

SUSPEND

Program Suspend

Program

Busy

Program Suspend

N/A

ERASE

SETUP

Ready (Error)

Erase Busy

Ready (Error)

BUSY

Erase Busy

Erase

Suspend

Erase Busy

Ready

SUSPEND

Erase

Suspend

Program in

Erase

Suspend

Setup

Erase Suspend

Erase Busy

Erase Suspend

Lock/RCR

Setup in

Erase

Suspend

Erase Suspend

N/A

PROGRAM IN

ERASE

SUSPEND

SETUP

Program in Erase Suspend Busy

BUSY

Program in Erase Suspend Busy

Program

Suspend in

Erase

Suspend

Program in Erase Suspend Busy

Erase

Suspend

SUSPEND

Program Suspend in Erase Suspend

Program in

Erase

Suspend

Busy

Program Suspend in Erase Suspend

N/A

LOCK/RCR SETUP IN

ERASE SUPSEND

Erase Suspend (Lock Error)

Erase

Suspend

Erase Suspend (Lock Error)

Erase Suspend

(Lock Error)

N/A

FAST

PROGRAM-

MING

ALGORITHM

SETUP

Ready (Error)

FPA Busy

Ready (Error)

FPA BUSY

FPA Busy

FPA Verify

FPA Busy

FPA VERIFY

Verify Busy

Ready

FPA Verify

Ready

4 ME

G x 16

AS
YNC/

AGE

/
B

URS

FLA

MOR

PRELI

M
INA

09005

aef8098d

2b
5

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ch
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In
c.

, r

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ce
.

MT28

W30.

ev
.

C

,
Pu

.
7/
03
EN

c
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o

Tec

l
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,
I

c
.

NOTE:

1. The output state shows the type of data that appears at the outputs if the block address is the same as the command address.
2. Illegal commands are those not defined in the command set.
3. All blocks default to read array mode at power up.
4. Both cycles of two-cycle commands should be issued to the same block address. If they are issued to different blocks, the second WRITE determines the

active block.

5. If the CSM is active, both cycles of a two-cycle command are ignored.
6. The CLEAR STATUS command clears the status register error bits except when the CSM is running or during SUSPEND.
7. FPA writes are allowed only when SR0 = 0. FPA is busy if BA = address at FPA CONFIRM command. Any other commands are treated as data.
8. The current state is that of the WSM, not the block.
9. Confirm commands perform the operation and the move to the ready state.

OUTPUT NEXT STATE AFTER COMMAND INPUT

PROGRAM SETUP, ERASE

SETUP, OTP SETUP, PROGRAM

IN ERASE SUSPEND SETUP,

FPA SETUP, FPA BUSY,

VERIFY BUSY

Status

Output does

not change

LOCK/RCR SETUP, LOCK/RCR

SETUP IN ERASE SUSPEND

Status

Array

Status

OTP BUSY

Array

Status

Output does not change

Status

Output

does not

change

Status

Output does not change

Array

Output does

not change

READY, PROGRAM BUSY,

PROGRAM SUSPEND, ERASE

BUSY, ERASE SUSPEND,

PROGRAM IN ERASE SUSPEND

BUSY, PROGRAM SUSPEND IN

ERASE SUSPEND

Status

ID/

Query

Table 27: Command State Machine Transition Table (continued)

Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a
time.

CURRENT CHIP STATE

DEVICE NEXT STATE AFTER COMMAND INPUT

READ

ARRAY

(FFh)

PROGRAM

SETUP

4,5

(10h/40h)

ERASE

SETUP

4,5

(20h)

FPA

SETUP

(30h)

BLOCK
ERASE

CONFIRM,

PROGRAM/

ERASE

RESUME,

UNLOCK

BLOCK

CONFIRM

(D0h)

PROGRAM/

ERASE

SUSPEND

(B0h)

READ

STATUS

(70h)

CLEAR

STATUS

(50h)

READ

ID/

QUERY

(90h,

98h)

LOCK,

UNLOCK,

LOCK

DOWN,

RCR

SETUP

(60h)

OTP

SETUP

(C0h)

LOCK BLOCK

CONFIRM

(01h)

LOCK

DOWN
BLOCK

CONFIRM

(2Fh)

WRITE RCR

CONFIRM

(03h)

FPA EXIT

(ADDRESS

<> BA)

(FFFFh)

ILLEGAL

COMMANDS

OR FPA DATA

(OTHER CODES)

WSM

OPERATION
COMPLETES

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 35: 56-Ball VFBGA

NOTE:

1. All dimensions in millimeters.

Data Sheet Designation

Production: This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 37% Pb, 2%Ag
SOLDER BALL PAD: Ø .27mm

PIN #1 ID

ENCAPSULATION MATERIAL: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

1.00 MAX

0.70 ±0.075

0.10 C

SEATING PLANE

BALL A8

BALL A1

5.25

4.50 ±0.05

9.00 ±0.10

3.75 ±0.05

2.625 ±0.05

2.25 ±0.05

4.50

7.50 ±0.10

0.75

TYP

0.75 TYP

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS Ø 0.33

0.35 TYP

56X Ø

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

09005aef8098d2b5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT28F644W30.fm Rev. C, Pub. 7/03 EN

Revision History

Rev. C, Production ...........................................................................................................................................................7/03

· Added Intel ManID variant
· Removed "Interleaved" Burst Option
· Expanded definition for

ACLK

· Addition of CFI ManID and DevID
· Updated VFBGA package drawing and notes
· Added value for V

ILKOQ

· Added value for

CEWV and

CEWZ

Rev. B, Preliminary ..........................................................................................................................................................3/03

· Included W18 specifications
· Reformatted document
· Added Table of Contents, List of Figures, List of Tables

Original document, Rev. A, Preliminary ........................................................................................................................3/03

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Document Outline

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