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Document Outline

Features
Part Numbering Information
- Valid Part Number Combinations
Table of Contents
List of Figures
List of Tables
General Description
Architecture
Addressing
Bus Operation
Command Definitions
Error Management
Electrical Characteristics
- Vcc Power Cycling
Timing Diagrams
Package Information
Revision History

Products and specifications discussed herein are subject to change by Micron without notice.

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Features

09005aef818a56a7 pdf/ 09005aef81590bdd source

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__1.fm - Rev. H 9/05 EN

NAND Flash Memory

MT29F2G08AABWP/MT29F2G16AABWP
MT29F4G08BABWP/MT29F4G16BABWP
MT29F8G08FABWP

Features

· Organization:

· Page size:

x8: 2,112 bytes (2,048 + 64 bytes)
x16: 1,056 words (1,024 + 32 words)

· Block size: 64 pages (128K + 4K bytes)
· Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks;

8Gb: 8,192 blocks

· Read performance:

· Random read: 25µs
· Sequential read: 30ns (3V x8 only)

· Write performance:

· Page program: 300µs (TYP)
· Block erase: 2ms (TYP)

· Endurance: 100,000 PROGRAM/ERASE cycles
· Data retention: 10 years
· First block (block address 00h) guaranteed to be

valid without ECC (up to 1,000 PROGRAM/ERASE
cycles)

· V

: 2.7V3.6V

· Automated PROGRAM and ERASE
· Basic NAND command set:

· PAGE READ, RANDOM DATA READ, READ ID,

READ STATUS, PROGRAM PAGE, RANDOM DATA
INPUT, PROGRAM PAGE CACHE MODE, INTER-
NAL DATA MOVE, INTERNAL DATA MOVE with
RANDOM DATA INPUT, BLOCK ERASE, RESET

· New commands:

· PAGE READ CACHE MODE
· READ UNIQUE ID (contact factory)
· READ ID2 (contact factory)

· Operation status byte provides a software method of

detecting:
· PROGRAM/ERASE operation completion
· PROGRAM/ERASE pass/fail condition
· Write-protect status

· Ready/busy# (R/B#) pin provides a hardware

method of detecting PROGRAM or ERASE cycle
completion

· PRE pin: prefetch on power up
· WP# pin: hardware write protect

Figure 1:

48-PIN TSOP Type 1

Options Marking

· Density:

2Gb (single die)

MT29F2GxxAAB

4Gb (dual-die stack)

MT29F4GxxBAB

8Gb (quad-die stack)

MT29F8GxxFAB

· Device width:

MT29Fxx08x

x16

MT29Fxx16x

· Configuration: # of die # of CE# # of R/B#

· V

: 2.7V3.6V

· Second generation die

· Package:

48 TSOP type I (lead-free plating)

48 TSOP type I (contact factory)

· Operating temperature:

Commercial (070°C)

Extended temperature
(-40°C to +85°C)

09005aef818a56a7 pdf/ 09005aef81590bdd source

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__1.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Part Numbering Information

Micron NAND Flash devices are available in several different configurations and densi-
ties. (See Figure 2.)

Figure 2:

Part Number Chart

Valid Part Number Combinations

After building the part number from the part numbering chart above, verify that the part
number is valid using the Micron Part Marking Decoder Web site at

http://www.micron.com/partsearch

to verify that the part number is offered and valid.

If the device required is not on this list, contact the factory.

MT 29F

2G 08 A A B WP

Micron Technology

Product Family

29F = Single-Supply NAND Flash Memory

Density

2G = 2Gb

4G = 4Gb

8G = 8Gb

Device Width

08 = 8 bits

16 = 16 bits

Operating Voltage Range

A = 3.3V (2.70V3.60V)

Production Status

Blank = Production

ES = Engineering Sample

MS = Mechanical Sample

Operating Temperature Range

Blank = Commercial (0°C to +70°C)

ET = Extended (40° to +85°C)

Reserved for Future Use

Package Codes

WP = 48-pin TSOP I (Lead-free)

WG = 48-pin TSOP I (contact factory)

Generation

A = 1st Generation Die

B = 2nd Generation Die

C = 3rd Generation Die

Classification

# of die # of CE# # of R/B#

I/O

1 1 1

Common

B 2 1 1

Common

F 4 2 2

Common

09005aef818a56a7 pdf/ 09005aef81590bdd source

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29bTOC.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Minimum Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-On AUTO-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

PAGE READ 00h30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RANDOM DATA READ 05hE0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh . . . . . . . . . . . . . . . . . . . . . .25
READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

PROGRAM PAGE 80h10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PROGRAM PAGE CACHE MODE 80h15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Internal Data Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

READ FOR INTERNAL DATA MOVE 00h35h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
INTERNAL DATA MOVE 85h10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

BLOCK ERASE 60hD0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

List of Figures

09005aef818a56a7 pdf/ 09005aef81590bdd source

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29bLOF.fm - Rev. H 9/05 EN

List of Figures

Figure 1:

48-PIN TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2:

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 3:

NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4:

Pin Assignment (Top View) 48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 5:

Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 6:

Memory Map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7:

Array Organization for MT29F2G08AxB (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 8:

Array Organization for MT29F2G16AxB (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 9:

Array Organization for MT29F4G08BxB and MT29F8G08FxB (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 10:

Array Organization for MT29F4G16BxB (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 11:

READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 12:

tR and tF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 13:

Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 14:

TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 15:

First Page Power-On AUTO-READ (3V V

only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 16:

AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 17:

PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 18:

RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 19:

PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 20:

READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 21:

Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 22:

PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 23:

RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 24:

PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 25:

INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 26:

INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 27:

BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 28:

RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 29:

ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 30:

ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 31:

PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 32:

PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 33:

COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 34:

ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 35:

INPUT DATA LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 36:

SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 37:

STATUS READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 38:

PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 39:

READ Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 40:

RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 41:

PAGE READ CACHE MODE Timing Diagram, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 42:

PAGE READ CACHE MODE Timing Diagram, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 43:

PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 44:

PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 45:

READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 46:

Program Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 47:

PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 48:

PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 49:

INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 50:

PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 51:

PROGRAM PAGE CACHE MODE Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

List of Figures

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Figure 52:

BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 53:

RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 54:

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

List of Tables

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List of Tables

Table 1:

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 2:

Array Addressing: MT29F2G08AxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 3:

Array Addressing: MT29F2G16AxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 4:

Array Addressing: MT29F4G08BxB and MT29F8G08FxB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 5:

Array Addressing: MT29F4G16BxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 6:

Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 7:

Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 8:

Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 9:

Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 10:

Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 11:

Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12:

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 13:

DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 14:

Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 15:

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 16:

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 17:

AC Characteristics--Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 18:

AC Characteristics--Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 19:

PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

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2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

General Description

NAND technology provides a cost-effective solution for applications requiring high-
density solid-state storage. The MT29F2G08AxB and MT29F2G16AxB are 2Gb NAND
Flash memory devices. The MT29F4G08BxB and MT29F4G16BxB are two-die stacks that
operate as a single 4Gb device. The MT29F8G08FAB is a four-die stack that operates as
two independent 4Gb devices (MT29F4G08BxB), providing a total storage capacity of
8Gb in a single, space-saving package. Micron

NAND Flash devices include standard

NAND features as well as new features designed to enhance system-level performance.

Micron NAND Flash devices use a highly multiplexed 8- or 16-bit bus (I/O[7:0] or
I/O[15:0]) to transfer data, addresses, and instructions. The five command pins (CLE,
ALE, CE#, RE#, WE#) implement the NAND command bus interface protocol. Three
additional pins control hardware write protection (WP#), monitor device status (R/B#),
and initiate the auto-read feature (PRE--3V device only). Note that the PRE function is
not supported on extended-temperature devices.

This hardware interface creates a low-pin-count device with a standard pinout that is
the same from one density to another, allowing future upgrades to higher densities with-
out board redesign.

MT29F2G and MT29F4G devices contain 2,048 and 4,096 erasable blocks respectively.
Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes
(x8) or 1,056 words (x16). The pages are further divided into a 2,048-byte data storage
region with a separate 64-byte area on the x8 device; and on the x16 device, separate
1,024-word and 32-word areas. The 64-byte and 32-word areas are typically used for
error management functions.

The contents of each 2,112-byte page can be programmed in 300µs, and an entire 132K-
byte/66K word block can be erased in 2ms. On-chip control logic automates PROGRAM
and ERASE operations to maximize cycle endurance. ERASE/PROGRAM endurance is
specified at 100,000 cycles when using appropriate error correcting code (ECC) and
error management.

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

General Description

Figure 3:

NAND Flash Functional Block Diagram

Note:

The PRE function is not supported on extended-temperature devices.

Figure 4:

Pin Assignment (Top View) 48-Pin TSOP Type 1

Notes: 1. CE2# and R/B2# on 8Gb device only. These pins are NC for other configurations.

2. The PRE function is not supported on extended-temperature devices.

Address Register

Data Register

Cache Register

Status Register

Command Register

CE#

CLE

ALE

WE#

RE#

WP#

I/O [7:0]
I/O [15:0]

Control

Logic

I/O

Control

R/B#

Row Decode

Column Decode

NC
NC
NC
NC
NC

R/B2#

R/B#

RE#
CE#

CE2#

Vcc

Vss

NC
NC

CLE

ALE

WE#
WP#

DNU
DNU
DNU

NC
NC

x16

NC
NC
NC
NC
NC
NC

R/B#

RE#
CE#

NC
NC

Vcc

Vss

NC
NC

CLE

ALE

WE#
WP#

DNU
DNU
DNU

NC
NC

x16

Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
PRE/V

Vcc
NC
NC
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss

NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
PRE/V

Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

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2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

General Description

Notes: 1. The PRE function is not supported on extended-temperature devices.

Table 1:

Pin Descriptions

Symbol

Type

Pin Function

ALE

Input

Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register upon a LOW to HIGH
transition on WE#

When address information is not being loaded, the ALE pin

should be driven LOW.

CE#, CE2#

Input

Chip enable: Gates transfers between the host system and the NAND device. Once
the device starts a PROGRAM or ERASE operation, the chip enable pin can be de-
asserted. For the 8Gb configuration, CE# controls the first 4Gb of memory; CE2#
controls the second 4Gb. See the Bus Operation section, starting on page 16, for
additional operational details.

CLE

Input

Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, the CLE pin should be driven LOW.

PRE

(3V device only)

Input

Power-on read enable: Enables the auto-read function when at Vcc. See the bus
operation section, starting on page 16, for additional details.

RE#

Input

Read enable: Gates transfers from the NAND device to the host system.

WE#

Input

Write enable: Gates transfers from the host system to the NAND device.

WP#

Input

Write protect: Pin protects against inadvertent PROGRAM and ERASE operations.
All PROGRAM and ERASE operations are disabled when the WP# pin is LOW.

I/O[7:0]

MT29FxG08

I/O[15:0]

MT29FxG16

I/O

Data inputs/outputs: The bidirectional I/O pins transfer address, data, and
instruction information. Data is output only during READ operations; at other
times the I/O pins are inputs.

R/B#, R/B2#

Output

Ready/busy: An open-drain, active-LOW output, that uses an external pull-up
resistor. The pin is used to indicate when the chip is processing a PROGRAM or
ERASE operation. The pin is also used during a READ operation to indicate when
data is being transferred from the array into the serial data register. Once these
operations have completed, the R/B# returns to the high-impedance state. In the
8Gb configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the
4Gb of memory enabled by CE2#.

Supply

: The V

pin is the power supply pin.

Supply

: The V

pin is the ground connection.

DNU

Do not use: Must be left floating.

No connect: NC pins are not internally connected. These pins can be driven or left
unconnected.

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Architecture

These devices use NAND electrical and command interfaces. Data, commands, and
addresses are multiplexed onto the same pins. This provides a memory device with a
low pin count.

The internal memory array is accessed on a page basis. When doing reads, a page of data
is copied from the memory array into the data register. Once copied to the data register,
data is output sequentially, byte by byte on x8 devices, or word by word on x16 devices.

The memory array is programmed on a page basis. After the starting address is loaded
into the internal address register, data is sequentially written to the internal data register
up to the end of a page. After all of the page data has been loaded into the data register,
array programming is started.

In order to increase programming bandwidth, this device incorporates a cache register.
In the cache programming mode, data is first copied into the cache register and then
into the data register. Once the data is copied into the data register, programming
begins.

After the data register has been loaded and programming started, the cache register
becomes available for loading additional data. Loading the next page of data into the
cache register takes place while page programming is in process.

The INTERNAL DATA MOVE command also uses the internal cache register. Normally,
moving data from one area of external memory to another uses a large number of exter-
nal memory cycles. By using the internal cache register and data register, array data can
be copied from one page and then programmed into another without using external
memory cycles.

Addressing

NAND Flash devices do not contain dedicated address pins. Addresses are loaded using
a five-cycle sequence as shown in Figures 7 and 8, on pages 12 and 13 respectively.
Table 2 on page 12 presents address functions internal to the x8 device; Table 3 on
page 13 covers the same functions for the x16 device. See Figures 5 and 6 on page 11 for
additional memory mapping and addressing details.

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2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Addressing

Figure 5:

Memory Map x8

Figure 6:

Memory Map x16

Note:

Block address and page address = actual page address.

A11

A17

A12

A28 (4Gb: A29)

A18

A11

page 63-0

Column Address within a page

Page Address within a block

Block Address

000BF83Fh

00080000h

0007F83Fh

00040000h

0003F83Fh

1FFFF83Fh

1FFC0000h

(4Gb: 3FFFF83Fh)

(4Gb: 3FFC0000h)

Spare Address within a page

A10

A16

A11

A27 (4Gb: A28)

A17

A10

page 63-0

Column Address

Page Address within a block

Block Address

005F41Fh

0040000h

003F41Fh

0020000h

001F41Fh

FFFF41Fh

FFE0000h

Spare Address within a page

(4Gb: 1FFFFC1Fh)

(4Gb: 1FFE0000h)

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Addressing

Figure 7:

Array Organization for MT29F2G08AxB (x8)

Note:

CAx = column address; RAx = row address.

Table 2:

Array Addressing: MT29F2G08AxB

Cycle

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

First

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

Second

LOW

CA11

CA10

CA9

CA8

Third

RA19

RA18

RA17

RA16

RA15

RA14

RA13

RA12

Fourth

RA27

RA26

RA25

RA24

RA23

RA22

RA21

RA20

Fifth

LOW

RA28

Cache Register

Data Register

2,048 blocks

per device

1 Block

2,048

2,112 bytes

I/O 7

I/O 0

64 pages = 1 block

(128K + 4K) bytes

1 page

= (2K + 64 bytes)

1 block

= (2K + 64) bytes x 64 pages

= (128K + 4K) bytes

1 device = (2K + 64) bytes x 64 pages

x 2,048 blocks

2,112

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Addressing

Figure 8:

Array Organization for MT29F2G16AxB (x16)

Notes: 1. CAx = column address; RAx = row address.

2. I/O[15:8] are not used during the addressing sequence and should be driven LOW.

Table 3:

Array Addressing: MT29F2G16AxB

Cycle

I/O[15:8]

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

First

LOW

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

Second

LOW

CA10

CA9

CA8

Third

LOW

RA18

RA17

RA16

RA15

RA14

RA13

RA12

RA11

Fourth

LOW

RA26

RA25

RA24

RA23

RA22

RA21

RA20

RA19

Fifth

LOW

RA27

Cache Register

Data Register

2,048 blocks

per device

1 Block

1,024

1,056 words

I/O 15

I/O 0

64 pages = 1 block

(64K + 2K) words

1 page

= (1K + 32) words

1 block = (1K + 32) words x 64 pages

= (64K + 2K) words

1 device = (1K + 32) words x 64 pages

x 2,048 blocks

2,112

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Addressing

Figure 9:

Array Organization for MT29F4G08BxB and MT29F8G08FxB (x8)

Note:

For the 8Gb MT29F8G08F, the 4Gb array organization shown here applies to each chip
enable (CE# and CE2#).

Notes: 1. Die address boundary: 0 = 0 2Gb, 1 = 2Gb 4Gb.

Table 4:

Array Addressing: MT29F4G08BxB and MT29F8G08FxB

CAx = column address; RAx = row address.

Cycle

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

First

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

Second

LOW

CA11

CA10

CA9

CA8

Third

RA19

RA18

RA17

RA16

RA15

RA14

RA13

RA12

Fourth

RA27

RA26

RA25

RA24

RA23

RA22

RA21

RA20

Fifth

LOW

RA29

RA28

Cache Register

Data Register

4,096 blocks

1 Block

2,048

2,112 bytes

I/O 7

I/O 0

64 pages = 1 block

(128K + 4K) bytes

1 page

= (2K + 64 bytes)

1 block

= (2K + 64) bytes x 64 pages

= (128K + 4K) bytes

1 device = (2K + 64) bytes x 64 pages

x 4,096 blocks

4,224

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Addressing

Figure 10: Array Organization for MT29F4G16BxB (x16)

Notes: 1. Die address boundary: 0 = 0 2Gb, 1 = 2Gb 4Gb.

2. I/O[15:8] are not used during the addressing sequence and should be driven LOW.

Table 5:

Array Addressing: MT29F4G16BxB

CAx = column address; RAx = row address.

Cycle

I/O[15:8]

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

First

LOW

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

Second

LOW

CA10

CA9

CA8

Third

LOW

RA18

RA17

RA16

RA15

RA14

RA13

RA12

RA11

Fourth

LOW

RA26

RA25

RA24

RA23

RA22

RA21

RA20

RA19

Fifth

LOW

RA28

RA27

Cache Register

Data Register

4,096 blocks

per device

1 Block

1,024

1,056 words

I/O 15

I/O 0

64 pages = 1 block

(64K + 2K) words

1 page

= (1K + 32) words

1 block

= (1K + 32) words x 64 pages

= (64K + 2K) words

1 device = (1K + 32) words x 64 pages

x 4,096 blocks

4,224

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2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Bus Operation

The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins. I/O pins I/O[15:8] are used only for data in the x16 configura-
tion. Addresses and commands are always supplied on I/O[7:0].

The command sequence normally consists of a command latch cycle, an ADDRESS
LATCH cycle, and a DATA cycle--either READ or WRITE.

Control Signals

CE#, WE#, RE#, CLE, ALE and WP# control Flash device READ and WRITE operations.
On the 8Gb MT29F8G08FAB, CE# and CE2# each control independent 4Gb arrays. CE2#
functions the same as CE# for its own array; all operations described for CE# also apply
to CE2#.

CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the Flash memory will accept command, data, and address information.

When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption. See Figure 39 on page 48 and Figure 46 on page 53 for examples of CE# "Don't
Care" operations.

The CE# "Don't Care" operation allows the NAND Flash to reside on the same asynchro-
nous memory bus as other Flash or SRAM devices. Other devices on the memory bus
can then be accessed while the NAND Flash is busy with internal operations. This capa-
bility is important for designs that require multiple NAND devices on the same bus. One
device can be programmed while another is being read.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an address input cycle is occurring.

Commands

Commands are written to the command register on the rising edge of WE# when:

· CE# and ALE are LOW, and
· CLE is HIGH, and
· the device is not busy.
The exceptions to this are the READ STATUS and RESET commands. Commands are
transferred to the command register on the rising edge of WE#. See Figure 33 on page 45.

Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must
be written with zeros when issuing a command.

Address Input

Addresses are written to the address register on the rising edge of WE# when:

· CE# and CLE are low, and
· ALE is high, and
· the device is not busy.
Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be
written with zeros when issuing an address.

Generally all five ADDRESS cycles are written to the device. An exception to this is the
BLOCK ERASE command, which requires only three ADDRESS cycles. See the "BLOCK
ERASE Operation" section on page 35 for details.

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Bus Operation

RANDOM DATA INPUT and OUTPUT commands need only column addresses, so only
two ADDRESS cycles are required. Refer to the command descriptions to determine the
addressing requirements for each command.

Data Input

Data is written to the data register on the rising edge of WE# when:

· CE#, CLE, and ALE are LOW, and
· the device is not busy.
Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 35 on
page 46 for additional data input details.

READs

After a READ command is sent to the memory device, data is transferred from the mem-
ory array to the data register in

R. Typically

R is 25µs. When data is available in the data

The READ STATUS (70h) command or the R/B# signal can be used to determine when
the device is ready. See the STATUS READ command section on page 29 for details.

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Bus Operation

Ready/Busy#

The R/B# output provides a hardware method of indicating the completion of a PRO-
GRAM/ERASE/READ operation. The signal is typically HIGH, and transitions to LOW
after the appropriate command is written to the device. The signal pin's open-drain
driver enables multiple R/B# outputs to be OR-tied. The signal requires a pull-up resis-
tor for proper operation. The READ STATUS command can be used in place of R/B#.
Typically R/B# would be connected to an interrupt pin on the system controller. See
Figure 11 on page 19.

On the 8Gb MT29F8G08FAB, R/B# provides an indication for the 4Gb section enabled by
CE#, and R/B2# does the same for the 4Gb section enabled by CE2#. R/B# and R/B2# can
be tied together, or they can be used separately to provide independent indications for
each 4Gb section.

The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# pin. The actual value used for Rp depends on the system timing
requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10- to 90-
percent points on the R/B# waveform, rise time is approximately two time constants
(TC).

TC = R * C

where R = Rp and C = total capacitive load

The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# pin and the total load capacitance.

Refer to Figure 12 on page 19, and Figure 13 on page 20, which depict approximate Rp
values using a circuit load of 100pF.

The minimum value for Rp is determined by the output drive capability of the R/B# sig-
nal, the output voltage swing, and V

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Bus Operation

Minimum Rp

Figure 11: READY/BUSY# Open Drain

Figure 12:

R and

Notes: 1.

R and

F calculated at 10%90% points.

R dependent on external capacitance and resistive loading and output transistor

impedance.

R primarily dependent on external pull-up resistor and external capacitive loading.

10ns at 3.3V.

5. See TC values in Figure 14 on page 20

for approximate Rp value and TC.

Where

is the sum of the input currents

of all devices tied to the R/B# pin.

Rp (MIN, 3.3V part) =

(MAX) V

(MAX)

3.2V

8mA +

R/B#
Open drain output

GND

Device

3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00

-1

2 4

0 2

4 6

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Bus Operation

Figure 13: I

vs. Rp

Figure 14: TC vs. Rp

3.50mA

3.00mA

2.50mA

2.00mA

1.50mA

1.00mA

0.50mA

0.00mA

0 2000

4000 6000

8000 10000 12000

@3.60V (max)

1.20µs

1.00µs

800ns

600ns

400ns

200ns

0ns

0 2k

4k 6k

8k 10k 12k

@3.60V (max)

RC = TC
C = 100pF

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Bus Operation

Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby.

2. PRE should be tied to V

or ground. Do not transition PRE during device operations.

The PRE function is not supported on extended-temperature devices.

3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW;

X = V

or V

Table 6:

Mode Selection

CLE

ALE

CE#

WE#

RE#

WP#

PRE

Mode

Read mode

Command input

Address input

Write mode

Command input

Address input

Data input

Sequential read and data output

During read (busy)

During program (busy)

During erase (busy)

Write protect

0V/V

Standby

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Bus Operation

Power-On AUTO-READ

During power-on, with the PRE pin at V

, 3V V

devices automatically transfer the

first page of the memory array to the data register without requiring a command or
address-input sequence. As V

reaches approximately 2.5V, the internal voltage detec-

tor initiates the power-on AUTO-READ function.

R/B# will stay LOW (

RPRE) while the first page of data is copied into the data register.

See Table 18 on page 44 for the

RPRE value. Once the READ is complete and R/B# goes

HIGH, RE# can be pulsed to output the first page of data.

The PRE function is not supported on extended-temperature devices.

Figure 15: First Page Power-On AUTO-READ (3V V

only)

Notes: 1. Verified per device characterization; not 100% tested on all devices.

2. The PRE function is not supported on extended-temperature devices.

Figure 16: AC Waveforms During Power Transitions

2.5V

Vcc

CLE

CE#

WE#

ALE

PRE

R/B#

RE#

I/Ox

tRPRE

1st

2nd

3rd

n th

.....

Undefined

WE#

R/B#

WP#

Vcc

10µs

HIGH

3V device:

2.5V

3V device:

2.5V

Undefined

Don't Care

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Command Definitions

Notes: 1. Do not cross die address boundaries when using cache operations. See Tables 4 and 5 for

definition of die address boundaries.

2. Do not cross die address boundaries when using READ for INTERNAL DATA MOVE and

PROGRAM FOR INTERNAL DATA MOVE. See Tables 4 and 5 for definition of die address
boundaries.

3. RANDOM DATA READ command limited to use within a single page.
4. RANDOM DATA INPUT for PROGRAM command limited to use within a single page.

Table 7:

Command Set

Operation

Cycle 1

Cycle 2

Valid During Busy

PAGE READ

00h

30h

PAGE READ CACHE MODE START

31h

PAGE READ CACHE MODE START LAST

3Fh

READ for INTERNAL DATA MOVE

00h

35h

RANDOM DATA READ

05h

E0h

READ ID

90h

READ STATUS

70h

Yes

PROGRAM PAGE

80h

10h

PROGRAM PAGE CACHE

80h

15h

PROGRAM for INTERNAL DATA MOVE

85h

10h

RANDOM DATA INPUT for PROGRAM

85h

BLOCK ERASE

60h

D0h

RESET

FFh

Yes

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Command Definitions

READ Operations

PAGE READ 00h30h

On initial power up, each device defaults to read mode. To enter the read mode while in
operation, write the 00h30h command sequence to the command register along with
the five ADDRESS cycles.

Writing 00h to the command register starts the ADDRESS LATCH cycle. Five ADDRESS
cycles are input next. Finally the 30h command is loaded into the command register.

While monitoring the read status to determine when the

R (transfer from Flash array to

data register) is complete, the user must re-issue the READ (00h) command to make the
change from STATUS to DATA. (See Figure 43 on page 51 and Figure 44 on page 52 for
examples.) After the READ command has been re-issued, pulsing the RE# line will result
in outputting data, starting from the initial column address.

A serial page read sequence outputs a complete page of data. After 30h is written, the
page data is transferred to the data register, and R/B# goes LOW during the transfer.
When the transfer to the data register is complete, R/B# returns HIGH. At this point, data
can be read from the device. Starting from the initial column address to the end of the
page, read the data by repeatedly pulsing RE# at the maximum

RC rate. (See Figure 17

on page 24.)

Figure 17: PAGE READ Operation

RE#

CE#

ALE

CLE

I/Ox

00h

Address (5 Cycles)

Data Output (Serial Access)

30h

R/B#

WE#

Don`t Care

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Command Definitions

RANDOM DATA READ 05hE0h

The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h30h sequence).

Random data can be output after the initial page read by writing an 05hE0h command
sequence along with the new column address (two cycles).

The RANDOM DATA READ command can be issued without limit within the page.

Only data on the current page can be read. Pulsing the RE# pin outputs data sequen-
tially. See Figure 18 on page 25.

Figure 18: RANDOM DATA READ Operation

PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh

Micron NAND Flash devices have a cache register that can be used to increase READ
operation speed when accessing sequential pages in a block.

First, a normal PAGE READ (00h30h) command sequence is issued. (See Figure 19 on
page 26 for operation details.) The R/B# signal goes LOW for

R during the time it takes

to transfer the first page of data from the memory to the data register. After R/B# returns
to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the
command register. R/B# goes LOW for

DCBSYR1 while data is being transferred from

the data register to the cache register. Once the data register contents are transferred to
the cache register, another PAGE READ is automatically started as part of the 31h com-
mand. Data is transferred from the next sequential page of the memory array to the data
register during the same time data is being read serially (pulsing of RE#) from the cache
register. If the total time to output data exceeds

R, then the PAGE READ is hidden.

The second and subsequent pages of data are transferred to the cache register by issuing
additional 31h commands. R/B# will stay LOW up to

DCBSYR2. This time can vary,

depending on whether the previous memory-to-data-register transfer was completed
prior to issuing the next 31h command. If the data transfer from memory to the data reg-
ister is not completed before the 31h command is issued, R/B# stays LOW until the
transfer is complete.

It is not necessary to output a whole page of data before issuing another 31h command.
R/B# will stay LOW until the previous PAGE READ is complete and the data has been
transferred to the cache register.

To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh)
command is issued. This command transfers data from the data register to the cache
register without issuing another PAGE READ. (See Figure 19 on page 26.)

RE#

I/Ox

00h

Address

(5 Cycles)

Data Output

30h

05h

Address

(2 Cycles)

E0h

R/B#

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Figure 19: PAGE READ CACHE MODE

RE#

CE#

ALE

CLE

I/Ox

00h

Address (5 Cycles)

Data Output (Serial Access)

31h

30h

31h

3fh

R/B#

WE#

Data Output (Serial Access)

tDCBSYR1

tDCBSYR2

Don`t Care

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Command Definitions

READ ID 90h

The READ ID command is used to read the 4 bytes of identifier codes programmed into
the devices. The READ ID command reads a 4-byte table that includes Manufacturer's
ID, device configuration, and part-specific information. See Table 8 on page 28, which
shows complete listings of all configuration details.

Writing 90h to the command register puts the device into the read ID mode. The com-
mand register stays in this mode until another valid command is issued. (See Figure 20.)

Figure 20: READ ID Operation

Notes: 1. See Table 8 on page 28.

Device

Don't Care

WE#

CE#

ALE

CLE

RE#

I/Ox

Address, 1 Cycle

90h

00h

Manufacturer

Byte 2

Byte 0

Byte 1

Byte 3

tAR

tREA

tWHR

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Command Definitions

Notes: 1. b = binary, h = hex

2. The MT29F8G08FAB device ID code reflects the configuration of each 4Gb section.

Table 8:

Device ID and Configuration Codes

Options

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

Value

Notes

Byte 0

Manufacturer ID

Micron

2Ch

Byte 1

Device ID

MT29F2G08AAB

2Gb, x8, 3V

DAh

MT29F2G16AAB

2Gb, x16, 3V

CAh

MT29F4G08BAB

4Gb, x8, 3V

DCh

MT29F4G16BAB

4Gb, x16, 3V

CCh

MT29F8G08FAB

8Gb, x8, 3V

DCh

Byte 2

Byte value

Don't Care

XXh

Byte 3

Page size

2KB

01b

Spare area size (bytes)

01b

Block size (w/o spare)

128KB

01b

Organization

x16

Reserved

Byte value

15h

Byte value

x16

55h

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Command Definitions

READ STATUS 70h

These NAND Flash devices have an 8-bit status register that the software can read dur-
ing device operation. On the x16 device, I/O[15:8] are "0" when reading the status regis-
ter. Table 9 describes the status register.

After the READ STATUS command has been issued to the NAND Flash device, all subse-
quent READ cycles will output data from the status register until another command is
issued. Note that the RE# pin can be toggled multiple times without issuing a new READ
STATUS command, as shown in Figure 21. Each time the RE# pin is toggled, the updated
status will be output on I/O[7:0].

In addition, after a READ STATUS command has been issued to the NAND Flash device,
the status register provides continually updated output on I/O[7:0] as long as CE# and
RE# are held LOW, i.e., RE# does not have to be toggled.

Note that MT29FxGxxxAB devices do not support a READ STATUS operation in which
the READ STATUS (70h) command is repeatedly issued after each RE# toggle.

Additional details regarding READ STATUS implementation are available in technical
note TN-29-13 at:

www.micron.com/products/nand/massstorage/technote

Figure 21: Status Register Operation

While monitoring the read status to determine when the

R (transfer from Flash array to

data register) is complete, the user must re-issue the READ (00h) command to make the
change from STATUS to DATA. After the READ command has been re-issued, pulsing
the RE# line will output data, starting from the initial column address.

70h

CE#

CLE

WE#

RE#

I/Ox

Status

Toggle RE# as required

Status

tREA

tCLR

tCLEA

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Command Definitions

Notes: 1. Status register bit 5 is "0" during the actual programming operation. If cache mode is

used, this bit will be "1" when all internal operations are complete.

2. Status register bit 6 is "1" when the cache is ready to accept new data. R/B# follows bit 6.

See Figure 19 on page 26, and Figure 24 on page 32.

Table 9:

Status Register Bit Definition

Bit

Page

Program

Program Page

Cache Mode

Page Read

Cache Mode

Block Erase

Definition

Pass/fail

Pass/fail (N)

Pass/fail

"0" = Successful PROGRAM/ERASE
"1" = Error in PROGRAM/ERASE

Pass/fail (N-1)

"0" = Successful PROGRAM/ERASE
"1" = Error in PROGRAM/ERASE

"0"

Ready/busy

"0" = Busy
"1" = Ready

Ready/busy

cache

Ready/busy

cache

Ready/busy

"0" = Busy
"1" = Ready

Write protect

Write protect "0" = Protected

"1" = Not protected

[15:8]

"0"

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Command Definitions

PROGRAM Operations

PROGRAM PAGE 80h10h

Micron NAND Flash devices are inherently page-programmed devices. Within a block,
the pages must be programmed consecutively from the least significant bit (LSB) page of
the block to most significant bit (MSB) pages of the block. Random page address pro-
gramming is prohibited.

Micron NAND flash devices also support partial-page programming operations. This
means that any single bit can only be programmed one time before an erase is required;
however, the page can be partitioned such that a maximum of eight programming oper-
ations are allowed before an erase is required.

SERIAL DATA INPUT 80h

PAGE PROGRAM operations require loading the SERIAL DATA INPUT (80h) command
into the command register, followed by five ADDRESS cycles, then the data. Serial data
is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h)
command is written after the data input is complete. The internal write state machine
automatically executes the proper algorithm and controls all the necessary timing to
program and verify the operation. Write verification only detects "1s" that are not suc-
cessfully written to "0s."

R/B# goes LOW for the duration of array programming time,

PROG. The READ STATUS

REGISTER (70h) command and the RESET (FFh) command are the only commands valid
during the programming operation. Bit 6 of the status register will reflect the state of
R/B#. When the device reaches ready, read bit 0 of the status register to determine if the
program operation passed or failed. (See Figure 22.) The command register stays in read
status register mode until another valid command is written to it.

RANDOM DATA INPUT 85h

After the initial data set is input, additional data can be written to a new column address
with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-
mand can be used any number of times in the same page prior to issuing the PAGE
WRITE (10h) command. See Figure 23 for the proper command sequence.

Figure 22: PROGRAM and READ STATUS Operation

Figure 23: RANDOM DATA INPUT

I/Ox

80h

Address (5 Cycles)

10h

70h

R/B#

tPROG

Status

I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error

I/Ox

80h

Address (5 Cycles)

85h

Address (2 Cycles)

10h

70h

R/B#

tPROG

Status

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Command Definitions

PROGRAM PAGE CACHE MODE 80h15h

Cache programming is actually a buffered programming mode of the standard PAGE
PROGRAM command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by five cycles of address, and a full or
partial page of data. The data is initially copied into the cache register, and the CACHE
WRITE (15h) command is then latched to the command register. Data is transferred
from the cache register to the data register on the rising edge of WE#. R/B# goes LOW
during this transfer time. After the data has been copied into the data register and R/B#
returns to HIGH, memory array programming begins.

When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and sub-
sequent programming passes, transfer from the cache register to the data register is held
off until current data register content has been programmed into the array.

Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h)
command to determine when the cache register is ready to accept new data. The R/B#
pin always follows bit 6.

Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.

If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the
CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used
every time, including the last page of the programming sequence, status register bit 5
must be used to determine when programming is complete. (See Figure 24.)

Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a "1" (ready state). The pass/fail status of the current PROGRAM opera-
tion is returned with bit 0 of the status register when bit 5 of the status register is a "1"
(ready state). (See Figure 24.)

Figure 24: PROGRAM PAGE CACHE MODE Example

Notes: 1. See Note 3, Table 19 on page 44.

2. Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass fail. RE# can stay LOW or

pulse multiple times after a 70h command.

tCBSY

R/B#

I/Ox

R/B#

I/Ox

Address &

Data Input

80h

15h

Address &

Data Input

80h

15h

Address &

Data Input

80h

15h

Address &

Data Input

80h

10h

tCBSY

tLPROG

tCBSY

Address &

Data Input

80h

15h

Address &

Data Input

80h

10h

Status

Output

70h

tPROG

Status

Output

70h

A: Without status reads.

B: With status reads.

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Command Definitions

Internal Data Move

An internal data move requires two command sequences. Issue a READ for INTERNAL
DATA MOVE (00h35h) command first, then the INTERNAL DATA MOVE (85h10h)
command. Data moves are only supported within the die from which data is read.

READ FOR INTERNAL DATA MOVE 00h35h

This READ command is used in conjunction with the INTERNAL DATA MOVE (85h
10h) command. First, (00h) is written to the command register, then the internal source
address is written (five cycles). After the address is input, the READ for INTERNAL DATA
MOVE (35h) command writes to the command register. This transfers a page from
memory into the cache register.

The written column addresses are ignored even though all five ADDRESS cycles are
required.

The memory device is now ready to accept the INTERNAL DATA MOVE (85h10h) com-
mand. Please refer to the description of this command in the following section.

INTERNAL DATA MOVE 85h10h

After the READ for INTERNAL DATA MOVE command has been issued and R/B# goes
HIGH, the INTERNAL DATA MOVE command can be written to the command register.
This command transfers the data from the cache register to the data register and program-
ming of the new destination page begins. After the INTERNAL DATA MOVE command
and address sequence are written to the device, R/B# goes LOW while the internal con-
trol logic automatically programs the new page. The READ STATUS command and bit 6
of the status register can be used instead of the R/B# line to determine when the write is
complete. Bit 0 of the status register indicates if the operation was successful.

The RANDOM DATA INPUT (85h) command can be used during the INTERNAL DATA
MOVE command sequence to modify a word or multiple words of the original data.
First, data is copied into the cache register using the 00h35h command sequence, then
the RANDOM DATA INPUT (85h) command is written along with the address of the data
to be modified next. New data is input on the external data pins. This copies the new
data into the cache register.

When 10h is written to the command register, the original data plus the modified data is
transferred to the data register, and programming of the new page is started. The RAN-
DOM DATA INPUT command can be issued as many times as necessary before starting
the programming sequence with 10h. (See Figures 25 and 26 on page 34.)

Because the INTERNAL DATA MOVE operation does not utilize external memory, ECC
cannot be used to check for errors before programming the data to a new page. This can
lead to a data error if the source page contains a bit error due to charge loss or charge
gain. In the case that multiple INTERNAL DATA MOVE operations are performed, these
bit errors may accumulate without correction. For this reason, it is highly recommended
that systems utilizing the INTERNAL DATA MOVE operation use a robust ECC scheme
that can correct two or more bits per sector.

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Command Definitions

Figure 25: INTERNAL DATA MOVE

Figure 26: INTERNAL DATA MOVE with RANDOM DATA INPUT

I/Ox

00h

Address

(5 Cycles)

35h

85h

Address

(5 Cycles)

10h

70h

R/B#

tPROG

Status

I/Ox

00h

Address

(5 Cycles)

35h

85h

Address

(5 Cycles)

Data

85h

Address

(2 Cycles)

Unlimited number

of repetitions.

10h

70h

Status

R/B#

tPROG

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Command Definitions

BLOCK ERASE Operation

BLOCK ERASE 60hD0h

Erasing occurs at the block level. For example, the MT29F2G08xxB device has 2,048
erase blocks organized as 64 2,112-byte (2,048 + 64 bytes) pages per block. Each block is
132K bytes (128K + 4K bytes). The BLOCK ERASE command operates on one block at a
time. (See Figure 27.)

Three cycles of addresses A[28:18] are required for the x8 device, and three cycles of
addresses [27:17] are required for the x16 device. Although addresses A[17:12] (x8) and
A[16:11] (x16) are loaded, they are a "Don't Care" and are ignored for BLOCK ERASE
operations. (See Figures 5 and 6 on page 11 for addressing details.)

The actual command sequence is a two-step process. The ERASE SETUP (60h) com-
mand is first written to the command register. Then three cycles of addresses are written
to the device. Next, the ERASE CONFIRM (D0h) command is written to the command
register. At the rising edge of WE#, R/B# goes LOW and the internal write state machine
automatically controls the timing and erase-verify operations. R/B# stays LOW for the
entire

BERS erase time.

The READ STATUS REGISTER command can be used to check the status of the ERASE
operation. When bit 6 = "1" the erase operation is complete. Bit 0 indicates a pass/fail
condition where "0" = pass. (See 35, and Table 9 on page 30.)

Figure 27: BLOCK ERASE Operation

RE#

CE#

ALE

CLE

I/Ox

60h

Address Input (3 Cycles)

Status

D0h

70h

R/B#

WE#

BERS

Don`t Care

I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error

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Command Definitions

RESET Operation

RESET FFh

The RESET command is used to put the memory device into a known condition and to
abort a command sequence in progress.

RANDOM READ, PROGRAM, and ERASE commands can be aborted while the device is
in the busy state. The contents of the memory location being programmed or the block
being erased are no longer valid. The data may be partially erased or programmed, and
is invalid. The command register is cleared and is ready for the next command.

The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes low for

RST after the RESET command is written to the

command register. (See Figure 28 and Table 10.)

Figure 28: RESET Operation

Table 10:

Status Register Contents After RESET Operation

Condition

Status

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Hex

WP# HIGH

Ready

E0h

WP# LOW

Ready and write protected

60h

CLE

CE#

WE#

R/B#

I/Ox

RST

RESET

Command

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Command Definitions

WRITE PROTECT Operation

The WRITE PROTECT feature protects the device against inadvertent PROGRAM and
ERASE operations. All PROGRAM and ERASE operations are disabled when WP# is LOW.
For WRITE PROTECT timing details, see Figures 29 through 32.

Figure 29: ERASE Enable

Figure 30: ERASE Disable

Figure 31: PROGRAM Enable

tWW

60h

D0h

WE#

I/Ox

WP#

R/B#

tWW

60h

D0h

WE#

I/Ox

WP#

R/B#

tWW

80h

10h

WE#

I/Ox

WP#

R/B#

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Command Definitions

Figure 32: PROGRAM Disable

tWW

80h

10h

WE#

I/Ox

WP#

R/B#

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Error Management

Micron NAND devices are specified to have a minimum of 2,008 (N

) valid blocks out

of every 2,048 total available blocks. This means the devices may have blocks that are
invalid when they are shipped. An invalid block is one that contains one or more bad
bits. Additional bad blocks may develop with use. However, the total number of avail-
able blocks will not fall below N

during the endurance life of the product.

Although NAND memory devices may contain bad blocks, they can be used quite reli-
ably in systems that provide bad-block mapping, replacement, and error correction
algorithms. This type of software environment ensures data integrity.

Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the Flash device.

The first block in each Micron NAND device is guaranteed to be free of defects when
shipped from the factory (up to 1,000 PROGRAM/ERASE cycles). This provides a reliable
location for storing boot code and critical boot information.

Before NAND devices are shipped from Micron, they are erased. The factory identifies
invalid blocks before shipping by programming data other than FFh (x8) or FFFFh (x16)
into the first spare location (column address 2,048 for x8 devices, or 1,024 for x16
devices) of the first 2 pages of each bad block.

System software should check the first spare address on the first 2 pages of each block
prior to performing any erase or programming operations on the Flash device. A bad
block table can then be created, allowing system software to map around these areas.
Factory testing is performed under worst-case conditions. Because blocks marked "bad"
may be marginal, it may not be possible to recover this information if the block is erased.

Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the Flash device, certain precautions
must be taken, such as:

· Always check status after a WRITE, ERASE, or DATA MOVE operation.
· Use some type of error detection and correction algorithm to recover from single-bit

errors.

· Use a bad-block replacement algorithm.

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Electrical Characteristics

Stresses greater than those listed under "Absolute Maximum Ratings" may cause per-
manent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not guaranteed. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.

Table 11:

Absolute Maximum Ratings by Device

Device

Symbol

Min

Max

Unit

MT29FxGxxxAx

Supply voltage on any pin relative to Vss

0.6

+4.6

MT29FxGxxxAx

Storage temperature

STG

+150

°C

Short circuit output current, I/Os

Table 12:

Recommended Operating Conditions

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Operating temperature

Commercial

+70

Extended

+85

supply voltage

Vcc

2.7

3.3

3.6

Supply voltage

Vss

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Electrical Characteristics

Power Cycling

Micron NAND Flash devices are designed to prevent data corruption during power tran-
sitions. V

is internally monitored. When V

goes below 1.1V, PROGRAM and ERASE

functions are disabled. WP# provides additional hardware protection. WP# should be
kept at V

during power cycling. When V

reaches 1.1V, a minimum of 10µs should be

allowed for the Flash to initialize before executing any commands. (See Figure 16 on
page 22.)

Note:

The PRE function is not supported on extended-temperature devices.

Table 13:

DC and Operating Characteristics

Parameter

Conditions

Symbol

Min

Typ

Max

Unit

Sequential read current

CYCLE = 30ns,

CE# = V

OUT

= 0mA

Icc1

Program current

Erase current

Standby current (TTL)

CE# = V

PRE = WP# = 0V/V

Standby current (CMOS)
MT29F2GxxAAB

CE# = V

- 0.2V,

PRE = WP# = 0V/V

µA

Standby current (CMOS)
MT29F4GxxBAB
MT29F8G08FAB

CE# = V

- 0.2V,

PRE = WP# = 0V/V

100

µA

Input leakage current

= 0V to V

±10

µA

Output leakage current

OUT

= 0V to V

±10

µA

Input high voltage

I/O [70], I/O [150]

CE#, CLE, ALE, WE#,
RE#, WP#, PRE, R/B#

0.8 x Vcc

+ 0.3

Input low voltage (all inputs)

-0.3

0.8

Output high voltage

= -400µA

2.4

Output low voltage

= 2.1mA

0.4

Output low current (R/B#)

= 0.4V

(R/B#)

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Electrical Characteristics

Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad

blocks upon shipment. Additional bad blocks may develop over time; however, the total
number of available blocks will not drop below N

during the endurance life of the

device. Do not erase or program blocks marked invalid by the factory.

2. Block 00h (the first block) is guaranteed to be valid and does not require error correction

up to 1,000 PROGRAM/ERASE cycles.

Notes: 1. These parameters are verified in device characterization and are not 100% tested.

2. Test conditions: T

= 25°C; f = 1 MHz; V

= 0V.

Notes: 1. Verified in device characterization; not 100% tested.

Table 14:

Valid Blocks

Parameter

Symbol

Device

Min

Max

Unit

Notes

Number of valid blocks

MT29F2GxxAAB

2,008

2,048

Blocks

1, 2

MT29F4GxxBAB

4,016

4,096

MT29F8G08FAB

8,032

8,192

Table 15:

Capacitance

Description

Symbol

Device

Max

Unit

Notes

Input capacitance

MT29F2GxxAAB

1, 2

MT29F4GxxBAB

MT29F8G08FAB

Input/output capacitance (I/O)

MT29F2GxxAAB

1, 2

MT29F4GxxBAB

MT29F8G08FAB

Table 16:

Test Conditions

Parameter

Value

Notes

Input pulse levels--MT29FxGxxxAB

0.0V to 3.3V

Input rise and fall times

5ns

Input and output timing levels

Output load

MT29FxGxxxAB (V

= 3.0V ±10%)

1 TTL GATE and CL = 50pF

MT29FxGxxxAB (V

= 3.3V ±10%)

1 TTL GATE and CL = 100pF

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Electrical Characteristics

Notes: 1. Timing for

ADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends

with the first rising edge of WE# for data input.

2. For PROGRAM PAGE CACHE MODE operations, the x16 AC characteristics apply for both

x16 and x8 devices.

Table 17:

AC Characteristics--Command, Data, and Address Input

Parameter

Symbol

x16

Unit

Notes

Min

Max

Min

Max

ALE to data start

ADL

100

ALE hold time

ALH

ALE setup time

ALS

CE# hold time

CLE hold time

CLH

CLE setup time

CLS

CE# setup time

Data hold time

Data setup time

Write cycle time

WE# pulse width HIGH

WE# pulse width

WP# setup time

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2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Electrical Characteristics

Notes: 1. For PROGRAM PAGE CACHE MODE operations, the x16 AC Characteristics apply for both

x16 and x8 devices.

2. Transition is measured ±200mV from steady-state voltage with load. This parameter is

sampled and not 100% tested.

3. If RESET (FFh) command is loaded at ready state, the device goes busy for maximum 5µs.
4. Do not issue a new command during

WB, even if R/B# is ready.

5. The PRE function is not supported on extended-temperature devices.

Notes: 1. Eight total to the same page.

CBSY MAX time depends on timing between internal program completion and data in.

LPROG =

PROG (last page) +

PROG (last 1 page) cmd load time (last page) addr load

time (last page) data load time (last page).

Table 18:

AC Characteristics--Normal Operation

Parameter

Symbol

x16

Unit

Notes

Min

Max

Min

Max

ALE to RE# delay

CE# access time

CEA

CE# HIGH to output High-Z

CHZ

CLE access time

CLEA

CLE to RE# delay

CLR

Cache busy in page read cache
mode (first 31h)

DCBSYR1

µs

Cache busy in page read cache
mode (next 31h and 3Fh)

DCBSYR2

DCBSYR1

µs

Ouput High-Z to RE# LOW

Data output hold time

Data transfer from Flash array to
data register

µs

READ cycle time

RE# access time

REA

RE# HIGH hold time

REH

RE# HIGH to output High-Z

RHZ

RE# pulse width

Data transfer from Flash array to
data register at power-up with
PRE enabled @ 3.3V Vcc

RPRE

µs

Ready to RE# LOW

Reset time
(READ/PROGRAM/ERASE)

RST

5/10/500

µs

WE# HIGH to busy

100

3, 4

WE# HIGH to RE# LOW

WHR

Table 19:

PROGRAM/ERASE Characteristics

Parameter

Symbol

Typ

Max

Unit

Notes

Number of partial page programs

NOP

Cycle

Block erase time

BERS

Busy time for cache program

CBSY

700

µs

Last page program time

LPROG

Page program time

PROG

300

700

µs

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Timing Diagrams

Figure 33: COMMAND LATCH Cycle

Note:

x16: I/O[15:8] must be set to "0.

Figure 34: ADDRESS LATCH Cycle

Note:

x16: I/O [15:8] must be set to "0."

WE#

CE#

ALE

CLE

I/Ox

COMMAND

ALH

ALS

CLH

CLS

Don`t Care

WE#

CE#

ALE

CLE

I/Ox

Address

tWP

tWH

tCS

tDH

tDS

tALS

tALH

tCLS

Don`t Care

Undefined

tWC

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Timing Diagrams

Figure 35: INPUT DATA LATCH

Notes: 1. D

Final = 2,111 (x8) or 1,055 (x16).

Figure 36: SERIAL ACCESS Cycle After READ

WE#

CE#

ALE

CLE

I/Ox

ALS

CLH

Final1

Don`t Care

CE#

RE#

I/Ox

REH

CEA

REA

Don`t Care

RHZ

CHZ

RHZ

R/B#

OUT

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Timing Diagrams

Figure 37: STATUS READ Cycle

Figure 38: PAGE READ

RE#

CE#

WE#

CLE

I/Ox

RHZ

WHR

CLEA

CLR

CLS

CLH

CHZ

REA

70h

Status Output

Don`t Care

CEA

OUT

N + 1

OUT

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Busy

00h

30h

CLR

RHZ

Don`t Care

Col

Add 1

Col

Add 2

Row

Add 1

Row

Add 2

Row

Add 3

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Timing Diagrams

Figure 39: READ Operation with CE# "Don't Care"

Figure 40: RANDOM DATA READ

RE#

CE#

REA

CEA

RE#

CE#

ALE

CLE

I/Ox

Out

R/B#

WE#

Data Output

Don`t Care

Address (5 Cycles)

00h

30h

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Busy

Col

Add 1

Col

Add 2

Row

Add 1

Row

Add 2

Row

Add 3

00h

Don't Care

OUT

M + 1

Col

Add 1

Col

Add 2

05h

E0h

REA

CLR

CLEA

OUT

N + 1

30h

WHR

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Timing Di

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Figure 41: PAGE READ CACHE MODE Timing Diagram, Part 1 of 2

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Column Address 0

OUT

Page Address

M + 1

CEA

CLH

CLS

Don't Care

tRR

tDCBSYR1

tDCBSYR2

Column Address 0

Continued to 1

of next page

tREA

30h

OUT

Column Address

00h

Page Address

31h

Col

Add 1

Col

Add 2

Row

Add 1

Row

Add 2

Row

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00h

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Timing Di

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Figure 42: PAGE READ CACHE MODE Timing Diagram, Part 2 of 2

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Page Address

M + 1

Don't Care

Page Address

M + 2

Column Address 0

Continued from 1

of previous page

Page Address

M + x

Column Address 0

CLH

REA

CEA

DCBSYR2

Column Address 0

OUT

31h

OUT

3Fh

OUT

CLS

OUT

31h

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Timing Di

agrams

Figure 43: PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2

tWC

WE#

CE#

ALE

CLE

RE#

I/Ox

30h

70h

Status

OUT

Column Address 0

OUT

Column Address

00h

Page Address

M + 1

Page Address

tCEA

tDS

tCLH

tCLS

tCS tCH

tDH

Don't Care

31h

Column Address 0

70h

Status

I/O 6 = 0, Cache Busy

= 1, Cache Ready

I/O 5 = 0, Busy
=

Ready

Continued to 1

of next page

Col

Add 1

Col

Add 2

Row

Add 1

Row

Add 2

Row

Add 3

00h

tRC

tREA

70h

Status

I/O 6 = 0, Cache Busy

= 1, Cache Ready

090

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Timing Di

agrams

Figure 44: PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2

WE#

CE#

ALE

CLE

RE#

I/Ox

Page Address

M + 1

Don't Care

Page Address

M + 2

Column Address 0

Continued from 1

of previous page

Page Address

M + x

Column Address 0

REA

CEA

Column Address 0

OUT

31h

OUT

3Fh

OUT

31h

70h

Status

I/O 6 = 0, Cache Busy

= 1, Cache Ready

70h

Status

I/O 6 = 0, Cache Busy

= 1, Cache Ready

70h

Status

I/O 6 = 0, Cache Busy

= 1, Cache Ready

00h

CLH

CLS

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Timing Diagrams

Figure 45: READ ID Operation

Figure 46: Program Operation with CE# "Don't Care"

Device ID

Don't Care

WE#

CE#

ALE

CLE

RE#

I/Ox

Address, 1 Cycle

90h

00h

Manufacturer ID

Byte 2

Byte 0

Byte 1

Byte 3

REA

WHR

CLE

CE#

WE#

ALE

I/Ox

Address (5 Cycles)

Data Input

10h

WE#

CE#

Don`t Care

Data Input

80h

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Timing Diagrams

Figure 47: PROGRAM PAGE Operation

Figure 48: PROGRAM PAGE Operation with RANDOM DATA INPUT

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

ADL

SERIAL DATA

INPUT Command

x8 device: m = 2,111 byte

x16 device: m = 1,055 byte

PROGRAM

Command

READ STATUS

Command

1 up to m Byte

Serial Input

80h

Col

Add 1

Col

Add 2

Row

Add 1

Row

Add 2

Row

Add 3

70h

Status

10h

PROG

Don`t Care

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

SERIAL DATA

INPUT Command

Serial Input

80h

Col

Add 1

Col

Add 2

Row

Add 1

Row

Add 2

Row

Add 3

N+1

ADL

RANDOM DATA

INPUT Command

Column Address

PROGRAM

Command

READ STATUS

Command

Serial Input

85h

PROG

Don`t Care

Col

Add 1

Col

Add 2

N+1

70h

Status

10h

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Timing Diagrams

Figure 49: INTERNAL DATA MOVE

Figure 50: PROGRAM PAGE CACHE MODE

Note:

PROGRAM PAGE CACHE MODE operations must not cross die address boundaries.

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

tPROG

tWB

Busy

READ STATUS

Command

INTERNAL

DATA MOVE

Don`t Care

tADL

Col

Add 2

Row

Add 1

Row

Add 2

70h

10h

Status

Data

Row

Add 3

Col

Add 1

00h

35h

Col

Add 2

Row

Add 1

Row

Add 2

Row

Add 3

Col

Add 1

85h

Data

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

15h

tCBSY

tWB

tWB tPROG

Col

Add 1

80h

10h

70h

Status

Col

Add 2

Row

Add 2

Row

Add 1

Col

Add 1

Col

Add 2

Row

Add 2

Row

Add 1

Row

Add 3

Last Page - 1

Last Page

SERIAL DATA

INPUT

Serial Input

PROGRAM

tWC

Don`t Care

80h

tADL

Row

Add 3

090

05aef

818

a56a

7 pdf/ 09

005a

ef81

590bdd source

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Timing Di

agrams

Figure 51: PROGRAM PAGE CACHE MODE Ending on 15h

WE#

CE#

ALE

CLE

RE#

I/Ox

15h

Col

Add 1

80h

15h

70h

Status

70h

Status

70h

Status

Col

Add 2

Row

Add 2

Row

Add 1

Row

Add 3

Col

Add 1

Col

Add 2

Row

Add 2

Row

Add 1

Row

Add 3

Last Page

Last Page -1

SERIAL DATA

INPUT

Serial Input

PROGRAM

tWC

Don`t Care

80h

Poll status until:
I/O6 = 1,

Ready

To ensure PROGRAM success, last 2 pages:
I/O5 = 1,

Ready

I/O0 = 0,

Last page PROGRAM successful

I/O1 = 0,

Last page -1 PROGRAM successful

tADL

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Timing Diagrams

Figure 52: BLOCK ERASE Operation

Notes: 1. See Table 8 on page 28 for actual values.

Figure 53: RESET Operation

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

AUTO BLOCK

ERASE SETUP

Command

ERASE

Command

READ STATUS

Command

Busy

Row Address

60h

Row

Add 1

Row

Add 2

Row

Add 3

70h

Status

D0h

tWC

tBERS

tWB

Don`t Care

CLE

CE#

WE#

R/B#

I/Ox

RST

RESET

Command

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Package Information

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__2.fm - Rev. H 9/05 EN

Package Information

All dimensions in millimeters; MIN/MAX, or typical, as noted.

Figure 54: Package Dimensions

Note:

For design guidelines using the 8Gb device, see Technical Note 2909, at:

www.micron.com/products/nand/massstorage/technote

1.20 MAX

0.15

+0.03
-0.02

0.20 ±0.05

SEE DETAIL A

0.50 TYP

18.40 ±0.08

20.00 ±0.25

12.00 ±0.08

DETAIL A

0.50 ±0.1

0.80

0.10

+0.10

-0.05

0.10

0.25

GAGE

PLANE

0.25

PIN #1 INDEX

PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn

PLASTIC PACKAGE MATERIAL: NOVOLAC EPOXY

PACKAGE WIDTH AND LENGTH DO NOT
INCLUDE MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2gb_nand_m29b__2.fm - Rev. H 9/05 EN

2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory

Revision History

Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/05
· Updated READ STATUS 70h description.

Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/05
· Clarified READ STATUS 70h description on page 29.
· Updated Figure 21 on page 29 and moved up under new description.

Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/05
· Revised endurance feature on page 1: deleted "with ECC and invalid block mapping."
· Updated

R functional description.

· Added data retention period.
· Clarified AC characteristics.

Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/05
· Replaced DNU definition in Table 1 on page 9.

Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/05
· Updated address latch diagram.

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/05
· Added WRITE PROTECT.
· Updated standby current descriptions.

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/05
· Updated package drawing.

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/05
· Initial Release

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT29F4G08BABWP